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Wafer-Scale Fabrication of NanodevicesUsing Nanoimprint Lithography at All Litho Levels

Stephen Y. ChouPrinceton University

andNanonex Corp

Supported in part by DARPA and ONR

Outline

Nanodevices made by Princeton and Nanonex60 nm MOSFETs on 4” wafers

Single electron transistors with 8 nm dot

Microwave transistors with 40 nm gate

Nanooptical devices (e.g. 20 nm fins)

Nanomagnetic devices (e.g. 10 nm bits)

Nanobio devices (e.g. 10 nm channels)

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Sub-5 nm Features and 14nm Pitch Nanonimprint

5 nm Line

6 nm Line

14 nm Pitch

14 nmPitch14 nmPitch6 nm

• Yet, feature size & pitch still limited by mold making, they can go smaller!• One litho method suitable for all nodes

NanoStructure Laboratory

PRINCETON UNIVERSITY

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60 nm Channel MOSFETs on 4” Wafer Using Nanoimprint Lithography At All Lithography Levels

0.0 0.5 1.0 1.5 2.00.0

0.1

0.2

0.3

0.4

0.5

∆Vg = 0.2 V Vg = 2.0 V

VDS (V)

I D(m

A)

1. Imprint #1: Active Area

4. Imprint #4: Metal

2. Imprint #2: Gate

3. Imprint #3: Via

60 nm channel MOSFETs on 4” wafer

NanoStructure LaboratoryPRINCETON UNIVERSITY

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Surface Topology of MOSFETs with All (4) Layers Fabricated by NIL

NanoStructure LaboratoryPRINCETON UNIVERSITY

1 µm

170 nm

140 nm

Gate

Active area

Via Metal contact

AFM image

Layer 1: Active area

Layer 2: Gate

Layer 3: Via

Layer 4: Metal contact

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Early Alignment Data of 8 Multilevel NIL Runs In MOSFETs Fabrication

X-Direction:

4"~ 4 cm

X

Y

2

3

4 5

7

89

Y-Direction:

Imprintnum ber

1 2 3 4 5 6 7 8 9 Aves σs

1 -1 -0.5 0 +0.25 +0.5 0 -0.5 -1 -0.5 0.5 0.32 +1 +1 +0.5 0 -0.5 -0.5 0 +1 +0.5 0.5 0.43 +1.5 +1.5 +1 0 -0.5 0 +0.5 +1 +0.5 0.8 0.64 -1 -1 -0.5 -0.5 0 -0.5 -0.5 -0.5 -0.5 0.5 0.35 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 0 0 0 0.3 0.26 +0.25 0 +0.5 +1 +0.75 +0.5 +0.5 0 +0.5 0.4 0.37 -1 -1 -0.5 0 +0.25 0 -0.5 -1 -0.25 0.5 0.48 +0.5 0 -0.5 -0.5 +0.5 -0.5 -0.5 +0.25 -0.25 0.3 0.2Avemulti 0.7 0.7 0.6 0.4 0.6 0.4 0.4 0.6 0.5 0.5σmulti

0.3 0.5 0.4 0.4 0.2 0.3 0.4 0.4 0.3 0.2

Im p rin tn u m b e r

1 2 3 4 5 6 7 8 9 A v e s σ s

1 + 1 .5 + 1 + 1 .2 5 + 1 .2 5 + 1 .5 + 1 .5 + 2 + 1 .5 + 1 .5 1 .3 0 .42 -0 .5 -0 .5 0 0 -0 .5 -0 .5 -1 + 1 -0 .5 0 .6 0 .33 + 1 + 1 + 1 .5 + 1 .5 + 1 0 0 0 + 0 .5 0 .7 0 .64 + 1 + 1 + 1 + 1 .5 + 1 .5 + 1 .5 + 1 .5 + 1 .5 + 1 1 .2 0 .25 0 0 0 0 0 -0 .5 0 0 0 0 .1 0 .26 0 0 0 0 0 0 0 0 0 0 07 + 0 .5 0 0 0 0 + 0 .5 + 1 + 1 + 0 .2 5 0 .4 0 .38 0 0 0 0 0 -0 .5 -0 .5 -0 .5 0 0 .2 0 .2

A ve m u lti0 .7 0 .6 0 .6 0 .6 0 .6 0 .8 0 .9 0 .8 0 .6 0 .6

σ m u lti0 .5 0 .5 0 .6 0 .6 0 .6 0 .6 0 .7 0 .6 0 .5 0 .5

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Moiré Alignment Marks for NIL

aligned misaligned

Preliminary Result of Single Point Alignment (Sub-100 nm)

8NanoStructure LaboratoryPRINCETON UNIVERSITY

0 50 100 1500

50

100

150

0

2

4

6

8

10

12

14

0 2 4 6 8 10 12 14

Y m

isal

ignm

ent (

nm)

X misalignment (nm)

Data point

mean: 91.5σ:17.9

mean: 71.9 σ: 12.5

data count

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N-MOSFET Ring Oscillators by NILVdd

GNDOutputStage 1 Stage 2 Stage 3 Stage n

Layer 1 Layer 2 Layer 3 Layer 4

Layout includes ring oscillators of 3, 5, 11, 21, 27, 31, 51, 101 stages.

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First Single-Electron Memory with 8 nm Dot Using NIL

Buried Oxide

Substrate

Floating Dot

Poly Si Control Gate

Source

Drain

5 nm

Buried OxideSubstrate

SiPoly Si

Tunneling OX

PMMA

Quantum dotsSource / Drain

Mesa

0 2 4 6 8 10

-0.05

-0.04

-0.03

-0.02

-0.01

0.00

0.01

*same result for 1 ms pulsePulse duration 1 µs

V t (V)

Control Gate Voltage (V)10 15 20 25 30

0

1

2

3

4

Num

ber o

f Dev

ices

Threshold Voltage Shift (mV)

NanoStructure LaboratoryPRINCETON UNIVERSITY

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Microwave FETs with 40nm Gate By Nanoimprint Lithography (3D Patterning)

1 2

3 4

6 inch

40 nm

Entire 6” Wafer 60,000X View of Gate

700X View of Gate

NanoStructure Laboratory

PRINCETON UNIVERSITY

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Subwavelength Optical Elements (SOEs) –Optical Chips by NIL

• Antireflective surfaces• Waveplates• Polarizers• Filters• Add/drop channel switches (tunable)• Couplers• Subwavelength binary lenses and

zone plates• Photonic crystals• High-speed photodetectors• High-speed lasers• And much more …….

Λ < λ

Key Uniqueness:• New functions unavailable in bulk optics

• Ultra-thin (e.g., < 1 µm)• Different optical functions by the same

materials but different nanopatterns• Large-scale monolithic integration on-chip• Low cost, mass production

Examples of SOEs

Antireflection of 200 nm pitchWaveplate with 20 nm fins Zone plate of 70 nm min. feature

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Ultra-High Density Magnetic Memories (Discrete Bits or Tracks) by Nanoimprint Lithography

MFM image of 65 Gbit/in2 quantized magnetic diskSEM micrograph of nanomagnetic pillars of a 65 Gbit/in2 density

Schematic of quantized magnetic disk. SEM micrograph of a 400 Gdot/in2 density and 10 nm dots and 40 nm pitch by nanoimprint

Magnetic

Nonmagnetic

Substrate

N

N

N

N

N

S

S

S

S

S

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Nano-Channel DNA Sorter by Nanoimprint

• Channel width (>50 nm )• Narrower than DNA

Persistent length• DNA automatically stretch

DNA molecules straight• DNA length = DNA molecular

weight

100 nm

Collaboration with Prof. Bob Austin Group

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Nanonex-1000• thermal plastic resist and

substrates• sub-60 sec/wafer• no alignment• 2”, 4”, 6”, and 8” wafers with a

single “smart” sample holder• Upgradable to NX-2000 & 3000• opto, displays, bio, data storage,

materials, …, appls

Nanonex-2000• versatile for all forms of imprinting:

thermal plastic resists, uv-curable resists, and embossing

• sub-60 sec/wafer• no alignment• 2”, 4”, 6”, and 8” wafers with a single

“smart” sample holder• Upgradable to NX-2000 & 3000• opto, displays, bio, data storage,

materials, …, appls

Nanonex-3000• alignment (submicron)• sub-60 sec/wafer• thermal plastic resist and uv

curable• 2”, 4”, 6”, and 8” wafers• micro-wave, opto, displays,

bio, data storage, materials, …, appls

Nanonex NIL Machines for Nanodevices Fabrication

Summary

Nanoimprint lithography (NIL) has shown 5 nm feature size and 14 nm pitch, and can go smaller!

NIL has been used to fabricate a variety of nanodevices with feature sizes and pitch far beyond capabality of many other litho tools.

NIL alignment accuracy is continuously approving.

NIL is being introduced as production tools in certain non-semiconductor sectors.

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Acknowledgment

• Peter Klauss

• Jay Guo

• Jim Wang

• Linhshu Kong

• Wei Zhang

• Larry Zhuang

• Gary Li

• Rich Yu

• Hua Tan

• Jian Gu

• Mike Austin

• Paru Deshpende

• Allan Chang

• Harry Gao

• Bob Austin

• Han Cao

• Other NSL members

• Other Nanonex employees

• Supported in part by DARPA and ONR

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