Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting...

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Wafer Fabrication Part II

Transcript of Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting...

Page 1: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

Wa fe r F a b ric a tio n P a rt II

Page 2: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

22

Introduction to Wafer Fabrication

• Introduction to TMEC• History from Edison’s Light Bulb to Pentium 4• Semiconductor Materials • Wafer Preparation• Wafer Fabrication Processes• Thin Film Deposition Process• Patterning Process• Etching Process• Doping Process• Contamination

Page 3: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

33

Microelectronics Fabrication

Lithography

Etching

Doping

Thin Film Deposition

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44

Wafer Fabrication Processes

CMOS Process Bipolar Process

BiCMOS Process

Technologie 0.25µm BiCMOS SiGe,Philips

Page 5: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

55

CMOS Process Flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

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66

Wafer

p-type Cz wafer

p-type

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77

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

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88

Initial oxidation: O2/H2 (Thickness: 420 nm)

p-type

n-well

SiO2

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99

n-well

Photolithography : NWELL

p-type

Photoresist (PR)

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1010

n-well

Dry etch oxide

p-type

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1111

n-well

n-well implantation : Phosphorus (3x1012 cm-3, 100 keV)

p-type

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1212

Resist strip

p-type

n-well

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1313

n-well drive : Anneal : N2

Differential Oxidation : O2/H2 Anneal : N2

p-type

n-well

n-well

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1414

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

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1515

Active

Wet etch all oxide + Pad oxidation (20 nm)

p-type

n-well

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1616

Deposition : Nitride (150 nm)

p-type

n-well

Active

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1717

Photolithography : ACTIVE

p-type

n-well

Active

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1818

Dry etch nitride

p-type

n-well

Active

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1919

Resist strip

p-type

n-well

Active

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2020

Photolithography : NFIELD

p-type

n-well

Active

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2121

NField implantation : Boron (8x1013 cm-3, 60 keV)

p-type

n-well

Active

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2222

Resist strip

p-type

n-well

Active

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2323

Field oxidation : O2/H2

p-type

n-well

Active

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2424

Active

Wet etch Nitride

p-type

n-well

Active

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2525

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

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2626

Gate

Etch Pad oxide + WR oxidation : H2/O2 (50 nm)

p-type

n-well

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2727

Photolithography : NFIELD

p-type

n-well

Gate

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2828

APT Implantation : Boron (6.5x1011 cm-3, 110 keV)

p-type

n-well

Gate

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2929

Resist strip

p-type

n-well

Gate

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3030

Anneal : N2

p-type

n-well

Gate

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3131

Etch WR oxide + Gate oxidation (25 nm)

p-type

n-well

Gate

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3232

VTA implantation : Boron (8x1011 cm-3, 20 keV)

p-type

n-well

Gate

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3333

Poly deposition

p-type

n-well

Gate

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3434

TEOS deposition

p-type

n-well

Gate

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3535

Poly implantation : Phosphorus (1.2x1016 cm-3, 50 keV)

p-type

n-well

Gate

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3636

Anneal : N2

p-type

n-well

Gate

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3737

Wet etch TEOS

p-type

n-well

Gate

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3838

Photolithography : POLY

p-type

n-well

Gate

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3939

Dry etch poly

p-type

n-well

Gate

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4040

Resist strip

p-type

n-well

Gate

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4141

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

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4242

Junctions

Oxidation : O2

p-type

n-well

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4343

Photolithography : NPLUS

p-type

n-well

Junctions

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4444

Nplus implantation : Phosphorus (1014 cm-2, 70 keV)Arsenic (6x1015 cm-2, 130 keV)

p-type

n-well

Junctions

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4545

Resist strip

p-type

n-well

Junctions

Page 46: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

4646

Photolithography : PPLUS

p-type

n-well

Junctions

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4747

Pplus implantation :Boron (5x1015 cm-2, 20 keV)

p-type

n-well

Junctions

Page 48: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

4848

Resist strip

p-type

n-well

Junctions

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4949

Coat front + Backside etch

p-type

n-well

Junctions

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5050

Resist strip

p-type

n-well

Junctions

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5151

Rapid thermal anneal : N2

p-type

n-well

Junctions

Page 52: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

5252

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. Interlayer Dielectric (ILD)7. Contacts and metal 18. Vias and metal 29. Passivation

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5353

Interlayer Dielectric

TEOS deposition : UTEOS

p-type

n-well

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5454

SOG coatSOG cureSOG coatSOG Cure

p-type

n-well

Interlayer Dielectric

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5555

PSG depositionPSG densification

p-type

n-well

Interlayer Dielectric

Page 56: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

5656

Coat frontBackside etch

p-type

n-well

Interlayer Dielectric

Page 57: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

5757

Resist strip

p-type

n-well

Interlayer Dielectric

Page 58: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

5858

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

Page 59: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

5959

Contacts and Metal1

Photolithography : CONTACT

p-type

n-well

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6060

Dry etch contacts : isotropic + anisotropic

p-type

n-well

Contacts and Metal1

Page 61: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

6161

Resist strip

p-type

n-well

Contacts and Metal1

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6262

Contract cleanMetal 1 sputtering : TiTiN

AlSiCu TiN

p-type

n-well

Contacts and Metal1

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6363

Photolithography : METAL1

p-type

n-well

Contacts and Metal1

Page 64: Wafer Fabrication Part II - NECTEC · 5 CMOS Process Flow p-type Silicon Substrate 1. Starting wafer 2. n-well 3. Active 4. Gate 5. Junction 6. ILD 7. Contacts and metal 1 8. Vias

6464

Dry etch Metal 1

p-type

n-well

Contacts and Metal1

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6565

Resist strip

p-type

n-well

Contacts and Metal1

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6666

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

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6767

Via and Metal2

Plasma oxide deposition

p-type

n-well

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6868

SOG coatSOG cure

p-type

n-well

Via and Metal2

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6969

Plasma oxide deposition

p-type

n-well

Via and Metal2

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7070

Photolithography : VIA

p-type

n-well

Via and Metal2

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7171

Dry etch vias : isotropic + anisotropic

p-type

n-well

Via and Metal2

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7272

Resist strip

p-type

n-well

Via and Metal2

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7373

Metal2 sputtering : AlsiCu TiN

p-type

n-well

Via and Metal2

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7474

Photolithography : METAL2

p-type

n-well

Via and Metal2

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7575

Dry etch metal2

p-type

n-well

Via and Metal2

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7676

Resist strip

p-type

n-well

Via and Metal2

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7777

Process flow

p-type Silicon Substrate

1. Starting wafer2. n-well3. Active4. Gate5. Junction6. ILD7. Contacts and metal 18. Vias and metal 29. Passivation

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7878

Passivation

PECVD nitride deposition, Photolithography : PASS, Dry etch nitride, Resist strip, Sintering : Forming gas

p-type

n-well


Vias enterales

Vias enterales

Manual VIAS

Manual VIAS

Personal Data...12) PI, Alberta Innovates Technology Solutions, Nanoworks (Micralyne), “Wafer Level Packaged MEMS Inertial Sensors with Through Silicon Vias for Use in Seismic Sensing

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Graphics Design Boonlert Aroonpiboon NECTEC boonlert@nectec.or.th .

Graphics Design Boonlert Aroonpiboon NECTEC [email protected] .

Through Silicon Vias in MEMS packaging, a review · 2019-12-12 · The vias need to be electrically insulated to avoid electrical shorting to the bulk of the wafer. A dielectric layer

Through Silicon Vias in MEMS packaging, a review · 2019-12-12 · The vias need to be electrically insulated to avoid electrical shorting to the bulk of the wafer. A dielectric layer

VIAS symposiumbundel

VIAS symposiumbundel

Vias Biliares

Vias Biliares

Vias terrestres

Vias terrestres

WAFER-LEVEL PACKAGED MEMS SWITCH WITH · PDF fileABSTRACT A miniaturized wafer-level packaged MEMS acceleration switch with through silicon vias (TSVs) was fabricated, based on technologies

WAFER-LEVEL PACKAGED MEMS SWITCH WITH · PDF fileABSTRACT A miniaturized wafer-level packaged MEMS acceleration switch with through silicon vias (TSVs) was fabricated, based on technologies