w w w . c h i n a f i x . c o m - Assistenza PC · 870-5071 870-1940 ALL ALT POGO PIN W_O CAP ......

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Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

IV ALL RIGHTS RESERVED

II NOT TO REPRODUCE OR COPY IT

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APPDCK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISIONREV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.


TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DRAWING

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL


J110 MLB SCHEMATIC

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

Schematic / PCB #’s

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

PRODUCT SAFETY REQUIREMENTS:

09/25/14

ALIASES RESOLVED

1 OF 73

<PART_DESCRIPTION>

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35 WILL_J435012/17/2012

SMC

34 J43_MLB4801/17/2013

IPD Connector

33 J43_MLB4602/20/2013

External A USB3 Connector

32 J43_MLB4009/14/2012

Camera 2 of 2

31 J43_MLB13901/09/2013

Camera 1 of 2

30 J43_MLB3702/20/2013

SSD Connector

29 J43_MLB3510/02/2012

Wireless Connector

28 T29_RR32

10/26/2012

Thunderbolt Connector A

27 WILL_J4330

12/17/2012

TBT Power Support

26 T29_RR29

12/17/2012

Thunderbolt Host (2 of 2)

25 T29_RR28

01/19/2013


24 J43_MLB2709/21/2012

LPDDR3 DRAM Termination

23 MASTER26MASTER

LPDDR3 DRAM Channel B (32-63)

22 MASTER25MASTER


21 MASTER24MASTER

LPDDR3 DRAM Channel A (32-63)

20 MASTER23MASTER


19 WILL_J432202/04/2013

DDR3 VREF MARGINING

18 J43_MLB2001/17/2013

Project Chipset Support

17 J43_MLB11901/09/2013

Chipset Support

16 WILL_J431812/17/2012

CPU/PCH Merged XDP

15 WILL_J431601/14/2013

PCH GPIO/MISC/LPIO

14 WILL_J431509/13/2012

PCH PCIe/USB/LPC/SPI/SMBus

13 J43_MLB1402/20/2013

PCH PM/PCI/GFX

12 WILL_J431312/17/2012

PCH Audio/JTAG/SATA/CLK

11 WILL_J431209/13/2012

PCH Decoupling

10 LABEL_J411001/11/2013

CPU Decoupling

9 J43_MLB910/02/2012

CPU/PCH GROUNDS

8 J43_MLB810/02/2012

CPU/PCH POWER

7 WILL_J43709/13/2012

CPU DDR3/LPDDR3 Interfaces

6 WILL_J436

09/13/2012

CPU Misc/JTAG/CFG/RSVD

5 WILL_J435

09/13/2012

CPU GFX/NCTF/RSVD

4 MASTER4

MASTER

PD Parts

3 MASTER3

MASTER

BOM Variants

2 J43_MLB201/17/2013

BOM Configuration

120 MASTER

MASTER

Reference73

118 J43_MLB

09/13/2012

Project Specific Constraints72

117 CHINMAY_J41

09/13/2012

SMC Constraints71

116 CHINMAY_J41

09/07/2012

Camera Constraints70

115 CHINMAY_J41

09/07/2012

Thunderbolt Constraints69

114 CHINMAY_J41

09/07/2012

Memory Constraints68

113 J43_MLB

09/14/2012

PCH Constraints 267

112 CLEAN_J41

11/13/2012

PCH Constraints 166

111 J43_MLB

09/21/2012

CPU Constraints65

110 J43_MLB

10/24/2012

PCB Rule Definitions64

105MASTER

MASTER

Project FCT/NC/Aliases63

104WILL_J43

12/17/2012

Func Test / No Test62

102MASTER

MASTER

Signal Aliases61

100WILL_J43

12/17/2012

Power Aliases60

95 CLEAN_J41

11/13/2012

LIO Connector59

83 J43_MLB

09/11/2012

Internal DisplayPort Connector58

81 J43_MLB

09/16/2012

Power Control57

80 J43_MLB

10/04/2012

Power FETs56

78 J43_MLB

10/04/2012

Misc Power Supplies55

77 J43_MLB

09/13/2012

LCD/KBD Backlight Driver54

76 J43_MLB

09/10/2012

1.05V S0 Power Supply53

75 J43_MLB

10/02/2012

5V S4RS3 / 3.3V S5 Power Supply52

74 J43_MLB

09/17/2012

LPDDR3 Supply51

73 J43_MLB

09/21/2012

CPU VR12.5 VCC Power Stage50

72 J43_MLB

10/09/2012

CPU VR12.6 VCC Regulator IC49

71 J43_MLB

09/14/2012

PBus Supply & Battery Charger48

70 J43_MLB

09/13/2012

DC-In & G3H Supply47

69 MASTER

MASTER

Battery Connector & Hall Effect46

64 J43_MLB

09/04/2012

Audio: Speaker Amp45

61 YHARTANTO_J44

01/09/2013

SPI Debug Connector44

60 J43_MLB

09/13/2012

Fan43

58 J43_MLB

02/20/2013

Thermal Sensors42

56SID_J41

02/26/2013

Debug Sensors 141

55SID_J41

02/26/2013

Voltage & Load Side Current Sensing40

54SID_J41

02/26/2013

High Side Current Sensing39

53J43_MLB

09/28/2012

SMBus Connections38

52 J43_MLB

02/20/2013

SMC Project Support37

51 WILL_J43

12/17/2012

SMC Shared Support36

Page(.csa)

SyncContentsDate Date(.csa)

ContentsPage Sync

LAST_MODIFIED=Thu Sep 25 10:26:20 2014

ABBREV=DRAWING

TITLE=MLB

1 MASTER1MASTER

Table of Contents

SCH1 CRITICALSCHEM,MLB,J110051-00384

PCB1 CRITICALPCBF,MLB,J110820-00164

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TABLE_BOMGROUP_ITEM



BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Module Parts

DRAM Parts

CFG 0

00

1 0

0 1

CPU DRAM CFG Chart

CFG 1

HYNIX

VENDOR

SAMSUNG

MICRON

0

1

CFG 2

1

0

1

1

0

1

0

1

CFG 3

RSVD

16GB

8GB

4GB

SIZE

ELPIDA

Current Sensor Configuration

CPU DRAM SPD Straps

Programmable Parts

Alternate PartsBOM Groups

U6100 CRITICAL BOOTROM_MAC:BLANK1 IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1335S00006

DRAM_TYPE:HYNIX_8GB333S0681333S0785 ALL ALT STANDOFF W_O MYLAR

333S0677333S0787 ALT STANDOFF W_O MYLARALLDRAM_TYPE:HYNIX_4GB

ALT STANDOFF W_O MYLAR860-1328 ALL860-3690

ALL860-1327860-3428 ALT STANDOFF W_O MYLAR

870-1940870-5071 ALL ALT POGO PIN W_O CAP

870-5074 870-1938 ALT POGO PIN W_O CAPALL

107S0248107S0250 Cyntec alt to TFTALL

107S0255 107S0240 Cyntec alt to TFTALL

152S1804152S1876 TDK alt to TokoALL

376S0761 ALL Renesas alt to Vishay376S00014

SYNC_DATE=01/17/2013SYNC_MASTER=J43_MLB

BOM Configuration

138S0638138S0841 ALL Murata alt to Samsung

197S0544197S0542 NDK alt to TXCALL

377S0104377S0155 ALL OnSemi alt to Infineon

Taiyo alt to Samsung138S0638138S0681 ALL

197S0544197S0545 Epson alt to TXCALL

128S0220128S0398 Kemet alt to SanyoALL

ALL Kemet alt to Sanyo128S0397 128S0325

128S0386 ALL128S0284 Kemet alt to Sanyo

353S3452 Maxim alt to MicrochipALL353S1286

Diodes alt to Fairchild376S0604376S1053 ALL

Diodes alt to ST MicroALL371S0558371S0713

ALL128S0376128S0371 Kemet alt to Sanyo

152S1757 Cyntec alt to NECALL152S1821

197S0343 ALL NDK crystal alt to TXC197S0480

107S0254 107S0241 ALL Cyntec sense R alt to TFT

138S0648138S0703 Murata alt to Taiyo YudenALL

152S1301152S0586 ALL Dale/Vishay alt to Cyntec

372S0186 NXP alt to Diodes372S0185 ALL

ALL197S0478197S0479 200uW Epson alt to NDK

138S0660138S0684 Murata alt to Taiyo YudenALL

376S1032 376S0855 Toshiba alt for Diodes dualALL

376S1089 ALL NXP alt for Diodes single376S1128

MLB_DEBUG:PROD BKLT:PROD,SAMCONN,XDP,ISNS:PROD

MLB_DEBUG:ENG XDP,SAMCONN

XDP_CONNMLB_DEVEL:PVT

MLB_DEVEL:ENG ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG

MLB_COMMON ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:PVT,MLB_PROGPARTS

MLB_DEBUG:PVT BKLT:PROD,XDP,SAMCONN,ISNS:ENG,DBGLED,XDP_CONN

ALL Epson crystal alt to TXC197S0481 197S0343

376S0855 ALL NXP alt for Diodes dual376S1129

CRITICALU5000 SMC:BLANK1338S1214 IC,SMC12-B1,40MHZ/50DMIPS MCU,157BGA

RAMCFG0:H,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:MICRON_8GBDDR3:MICRON_8GB

DDR3:MICRON_16GB RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:MICRON_16GB

DDR3:HYNIX_16GB RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:HYNIX_16GB

DDR3:SAMSUNG_16GB RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:SAMSUNG_16GB

DDR3:ELPIDA_16GB RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:ELPIDA_16GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GBDDR3:MICRON_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GBDDR3:ELPIDA_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GBDDR3:SAMSUNG_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GBDDR3:ELPIDA_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GBDDR3:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GBDDR3:HYNIX_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GBDDR3:HYNIX_4GB

ISNS:PROD CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO

ISNS:ENG CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES

CRITICAL4 DRAM_TYPE:MICRON_4GBU2300,U2400,U2500,U2600IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA333S0793

4 CRITICALU2300,U2400,U2500,U2600 DRAM_TYPE:SAMSUNG_8GBIC,SDRAM,23NM,16GB,LPDDR3-1600,178P FBGA333S00003

333S0791 IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL4 DRAM_TYPE:ELPIDA_8GB

333S0793 IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA CRITICAL4 U2300,U2400,U2500,U2600 DRAM_TYPE:ELPIDA_4GB

U2300,U2400,U2500,U2600 CRITICAL4 DRAM_TYPE:SAMSUNG_4GBIC,SDRAM,23NM,8GB,LPDDR3-1600,178P FBGA333S00001

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL4 DRAM_TYPE:HYNIX_4GB333S0677

CRITICALQ7310,Q73202 MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN VCORE_FET:VSHY376S1194

Q7311,Q7321MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN CRITICAL2 VCORE_FET:VSHY376S1193

900-0090 SOLDERPASTE1 CRITICAL

NEW_LABELLABEL,MLB,J41/J43825-7987 1

MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN2 CRITICALQ7311,Q7321 VCORE_FET:REN376S00037

825-7670 LABEL,TEXT,MLB,K21/K781 LABEL

MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN CRITICALQ7310,Q73202 VCORE_FET:REN376S00036

946-5477 CRITICALGLUE1 UV GLUE,MLB,J41_J43

U3900 CRITICAL1338S1264 IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

J110_MLB607-6811 1 J6955 CRITICALASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

1 CRITICALU0500 CPU:1.6GHZBDW,QGHB,D0,1.6,15W,2+2,0.6,4M,B1168337S00073

CPU:2.1GHZ1 CRITICALU0500337S00029 BDW,QGH9,D0,1.8,15W,2+2,0.7,4M,B1168

U2300,U2400,U2500,U26004 CRITICAL333S0791 IC,SDRAM,16GB,LPDDR3-1600,178P FBGA DRAM_TYPE:MICRON_8GB

4 CRITICAL DRAM_TYPE:HYNIX_8GBU2300,U2400,U2500,U2600333S0681 IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

U28901 CRITICAL TBTROM:BLANKEEPROM,4MBIT,SPI,50MHZ,1.8V,USON8335S0915

MLB_MISC PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS,SSD_LPSR:S3

DRAM_TYPE:ELPIDA_16GB333S0789 IC,SDRAM,25nm,32Gb,LPDDR3-1600,178P FBGA CRITICAL4 U2300,U2400,U2500,U2600

U2890 TBTROM:PROG1 CRITICALT29,EEPROM,FALCON RIDGE(V27.1), PROtO 0,J110/J113341S00159

U6100 CRITICAL BOOTROM:PROG1 IC,EFI ROM(V0108), PROTO 0,J110/J113341S00153

U61001 CRITICAL BOOTROM_NUM:BLANKIC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1335S00007

CRITICALU28001338S00069 IC,TBT,FR-2C,288, 12X12 FC-CSP,TRAY

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Apple Inc.


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TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD



TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

Sub-BOMs

Alternate Parts

BOM Groups

Programmable Parts

BOM Variants

U5000 CRITICAL1 SMC:PROG341S00147 IC,SMC-A3,EXT,Vxxxx,PROTO 0,J110

BOOTROM:PROG,SMC:PROG,TBTROM:PROGMLB_PROGPARTS

685-00045 VCORE FET,VSHY,J1101 CRITICAL VCORE_FETSVCOREFETS

685-00043 CMN PTS,PCBA,MLB,J110 CRITICAL MLB_CMNPTS1 CMNPTS

Renesas alt to VishayALL685-00044 685-00045

Elpida CAM DRAM alt to HynixALL333S0704 333S0700

BOM Variants

SYNC_MASTER=MASTER SYNC_DATE=MASTER

639-00613 MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_4GB,ALTERNATEPCBA,MLB,BETTER,HY-4GB,X430

PCBA,MLB,BETTER,HY-8GB,X430 MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_8GB,ALTERNATE639-00614

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_4GB,ALTERNATE639-00616 PCBA,MLB,BETTER,SM-4GB,X430

639-00621 PCBA,MLB,BETTER,EL-4GB,X430 MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,BETTER,SM-8GB,X430639-00617 MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

639-00622 MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_8GBPCBA,MLB,BETTER,EL-8GB,X430

639-00695 PCBA,MLB,BETTER,EL-16GB,X430 MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_16GB

MLB_COMMON,J110_MLB685-00043 CMN PTS,PCBA,MLB,X430

VCORE_FET:RENVCORE FET,REN,X430685-00044

VCORE_FET:VSHYVCORE FET,VSHY,X430685-00045

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4x 860-00165

2x MDP connector

2x USB connector

998-3975

2x TBT chip

2x TBT pin diodes

998-3975

Can Slots

998-2691

998-2691

998-3975

998-2691

998-3975

DisplayPort Pogo

EMI I/O Pogo Pins

USB/SD Card Pogo

870-1940

870-1938

860-1327

SSD BossX21 Boss

860-1327860-1327

Fan Boss

998-2691

CPU Heat Sink Mounting Bosses

PD Module Parts

1

Z0415STDOFF-4.5OD1.9H-SM

1


1


1

ZS0405

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

1

ZS0407

SM

POGO-2.0OD-2.95H-K86-K87

CRITICAL

1

SL0401TH-NSP

SL-1.1X0.4-1.4x0.7

1

SL0402TH-NSP

SL-1.1X0.4-1.4x0.7

1

SL0404

SL-1.1X0.45-1.4x0.75

TH-NSP1

SL0403

SL-1.1X0.45-1.4x0.75

TH-NSP

1

SL0406

SL-1.1X0.4-1.4x0.7

TH-NSP

1

SL0408TH-NSP

SL-1.1X0.45-1.4x0.75

1

SL0405

SL-1.1X0.4-1.4x0.7

TH-NSP

1

SL0407TH-NSP

SL-1.1X0.45-1.4x0.75

1

Z04104.5OD1.85ID-1.78H-SM

1

Z04124.5OD1.85ID-1.78H-SM

1

Z04134.5OD1.85ID-1.78H-SM

1

Z04114.5OD1.85ID-1.78H-SM


PD Parts

CAN,TBT,J11/J13 CRITICAL1 TBTFENCE806-3142

MDPCAN CRITICALCAN,MDP,J11/J131806-3216

CAN,COVER,TBT,J11/J13806-3215 1 TBTCOVER CRITICAL

806-5107 CAN,TOPSIDE,ALT,J41/J43 TBTTOPSIDE_2P_FENCE CRITICAL1

806-3083 1 SHLD,USB,MLB,J11/J13 USBCAN CRITICAL

CRITICAL1725-1792 INSULATOR,CPU,J41/J43 CPU_INSULATOR

806-5108 CAN,TOPSIDE,COVER,ALT,J41/J43 TBTTOPSIDE_2P_COVER CRITICAL1

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OUT

BI

BI

DDI

EDP

SYM 1 OF 19

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN

EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

SYM 17 OF 19

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

SPARE

SYM 18 OF 19

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

TP

TP

TP

TP

TP

TP

TP

TP

NC NCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNCNC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Other corner test signals connected in

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints.

NO_TESTNO_TEST

daisy-chain fashion. Continuity should

exist between both TP’s on each corner.

eDP Port Assignment:

Internal panel

DDI Port Assignments:

TBT Sink 0

TBT Sink 1

(MUXed with HDMI

if necessary)

18 25 65

18 25 65

58 65

58 65

62

62

62

62

62

62

58 65

58 65

B49

C46

B47

B46

A49

C47

A47

C45

D20

A43

B45

A45

B53

B50

B54

C50

A53

C49

C53

C51

B57

A55

C58

C55

A57

B55

B58

C54

U0500BROADWELL-ULT

2C+GT2

CRITICAL

OMIT_TABLE

BGA

C2

C1

B63

B62

B61

B3

B2

AY62

AY61

AY60

AY3

AY2

AW63

AW62

AW61

AW3

AW2

AW1

AV1

A62

A61

A60

A4

A3

U0500BROADWELL-ULT

2C+GT2BGA

OMIT_TABLE

CRITICAL

U10

T23

R23

N23

J21

H22

F22

D15

AY14

AW14

AV44

AU44

AU15

AU10

AT2

AP7

AM11

AL1

U0500

2C+GT2BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

1TP0531

TP-P6

1TP0500

TP-P61

TP0510TP-P6

1TP0501

TP-P6

1TP0511

TP-P61

TP0520TP-P61

TP0521TP-P6

1TP0530

TP-P6

2

1R0530

1/20W

201MF

1%24.9

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

18 25 65

18 25 65

18 25 65

18 25 65

18 25 65

18 25 65

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

CPU GFX/NCTF/RSVD

MCP_DC_A3_B3TRUE

MCP_DC_A60

MCP_DC_A4

MCP_DC_A62TRUE MCP_DC_A61_B61

MCP_DC_AV1

MCP_DC_AW1

TRUE MCP_DC_AW2_AY2

MCP_DC_AW61_AY61TRUE

MCP_DC_AW3_AY3TRUE

TRUE MCP_DC_AW62_AY62

MCP_DC_AW63

MCP_DC_B2

MCP_DC_AW62_AY62 TRUE

TRUEMCP_DC_A61_B61

MCP_DC_A3_B3 TRUE

MCP_DC_B62_B63 TRUE

MCP_DC_C1_C2 TRUE

MCP_DC_AW61_AY61 TRUE

MCP_DC_AY60TRUEMCP_DC_AW3_AY3TRUEMCP_DC_AW2_AY2

DP_INT_ML_C_N<0>

NC_INT_ML_CP<1>

NC_INT_ML_CN<1>

DP_INT_ML_C_P<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>















MCP_EDP_RCOMP

TP_EDP_DISP_UTIL

DP_INT_AUXCH_C_N

DP_INT_AUXCH_C_P

NC_INT_ML_CP<3>

NC_INT_ML_CN<3>

NC_INT_ML_CP<2>

NC_INT_ML_CN<2>

PPVCOMP_S0_CPU

5 OF 73

<BRANCH>

<SCH_NUM>

<E4LABEL>

5 OF 120

5

5

5

5

5

5

5

5

5

5

5

5

8

w w w

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f i x

. c o

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BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNC

NC

SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1

SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*PROC_DETECT*

RESERVED

SYM 19 OF 19

VSS

VSS

RSVD

RSVD

CFG_RCOMP

RSVD

RSVD

RSVD

TD_IREF

CFG0

CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17

CFG19

RSVD

RSVD

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD

RSVD

RSVD

PROC_OPI_COMP

RSVD

RSVD

RSVD_B43

BI

BI

OUT

NC

BI

BI

BI

BI

BI

BI

BI

BI

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

NC

NCNCNCNC

NCNC

NCNC

NC

Apple Inc.


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6 3



(IPU)

(IPU)

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPD)

(IPU)

These can be placed close to J1800

and are only for debug access

issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

2

1R0640

MF1/20W

201

5%1K

NOSTUFF

2

1R0639

MF1/20W

201

5%1K

HSW_PRE_ES2

2

1R0638

NOSTUFF

1K5%

201

1/20WMF

2

1R0631

NOSTUFF

1K5%

201

1/20WMF

2

1R0630

MF1/20W

201

5%1K

NOSTUFF

6 16 65

6 16 65

16 62 65

16 65

16 65

6 16 65

16 65

16 65

6 16 65

6 16 65

16 65

6 16 65

16 65

16 65

16 65

16 65

16

16

16

16

AU61

AV60

AU60

AV61

AV15

C61

K63

E59

E61

F62

F63

E60

D61

K62

J62

N62

K61

J61

K60

H63

K59

H62

H61

H60

J60

U0500

CRITICAL

OMIT_TABLE

BGA2C+GT2

BROADWELL-ULT

P22

N21

B12

Y22

W23

L60

C63

C62

B51

AV63

AU63

A51

R20

P20

N60

J20

H18

E1

D58

D1

B43

AV62

A5

AY15

V63

V61

V62

Y60

Y61

Y62

AA60

AA63

AC63

U62

U63

AA61

AA62

T60

T61

T62

T63

U60

V60

AC62

AC60

U0500

BGA2C+GT2

BROADWELL-ULT

OMIT_TABLE

CRITICAL

35 36 49 65

2

1R061062

201MF

1/20W5%

2 1

R0611

1/20W

56

MF

5%

201

36 65

35 65

2

1R062010K

5%1/20W

MF201

PLACE_NEAR=U0500.C61:12.7mm

16 65

16 65

16 65

16 65

16 65

16 65

16 65

16 65

16 62 65

16 62 65

12 16 62 65

16 62 65

16 62 65

16 62 65

16 62 65

2

1R0652

PLACE_NEAR=U0500.AU61:12.7mm

1%100

201

1/20WMF

2

1R0651121

PLACE_NEAR=U0500.AV60:12.7mm

1%

201

1/20WMF

2

1R0650


MF1/20W

201

2001%

18

17

2

1R068049.9

MF201

1/20W1%

2

1R069049.91%1/20WMF201

2

1R06858.25K1%

201MF1/20W

2

1R0634EDP

MF1/20W

201

5%1K

CPU Misc/JTAG/CFG/RSVD


CPU_CFG_RCOMP

PCH_TD_IREF

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<6>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<11>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<12>

CPU_CFG<18>

CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<19>

TP_MCP_RSVD_AV63

TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63

TP_MCP_RSVD_C62

TP_MCP_RSVD_A51

TP_MCP_RSVD_B51

TP_MCP_RSVD_L60

CPU_OPI_RCOMP

CPU_MEMVTT_PWR_EN_LSVDDQ

TP_CPU_MEM_RESET_L

CPU_SM_RCOMP<1>

CPU_SM_RCOMP<2>

CPU_SM_RCOMP<0>

CPU_PROCHOT_R_L

CPU_PWRGD

CPU_PECI

CPU_CATERR_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPUPCH_TRST_L

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

CPU_CFG<1>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<0>

CPU_PROCHOT_L

CPU_CFG<4>

PP1V05_S0

6 OF 73

6 OF 120

<E4LABEL>

<SCH_NUM>

<BRANCH>

65

65

65

65

6 16 65

6 16 65

6 16 65

6 16 65

6 16 65

6 16 65

8 11 15 16 17 36 40 49 53 56 57 60 62

w w w

. c h

i n a

f i x

. c o

m

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

SYM 3 OF 19

MEMORY CHANNEL A

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55

SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45

SA_DQ46

SA_DQ42

SA_DQ43

SA_DQ44

SA_DQ40

SA_DQ41

SA_DQ39

SA_DQ37

SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32

SA_DQ33

SA_DQ29

SA_DQ30

SA_DQ31

SA_DQ27

SA_DQ28

SA_DQ24

SA_DQ25

SA_DQ22

SA_DQ23

SA_DQ21

SA_DQ19

SA_DQ20

SA_DQ17

SA_DQ18

SA_DQ16

SA_DQ14

SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7

SA_DQ8

SA_DQ6

SA_DQ4

SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0*

SA_CS1*

SA_CKE0

SA_CKE1

SA_CKE2

SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3

SA_MA4

SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13

SA_MA14

SA_MA15

SA_BA2

SA_BA0

SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3

SA_DQSP4

SA_DQSP5

SA_DQSP6

SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5

SA_DQSN6

SA_DQSN7

SYM 4 OF 19

MEMORY CHANNEL B

SB_DQ0

SB_DQ1

SB_DQ2

SB_DQ3

SB_DQ4

SB_DQ5 SB_CKE0

SB_DQ6 SB_CKE1

SB_DQ7 SB_CKE2

SB_DQ8 SB_CKE3

SB_DQ9

SB_DQ10 SB_CS0*

SB_DQ11 SB_CS1*

SB_DQ12

SB_DQ13 SB_ODT0

SB_DQ14

SB_DQ15 SB_RAS*

SB_DQ16 SB_WE*

SB_DQ17 SB_CAS*

SB_DQ18

SB_DQ19 SB_BA0

SB_DQ20 SB_BA1

SB_DQ21 SB_BA2

SB_DQ22

SB_DQ23 SB_MA0

SB_DQ24 SB_MA1

SB_DQ25 SB_MA2

SB_DQ26 SB_MA3

SB_DQ27 SB_MA4

SB_DQ28 SB_MA5

SB_DQ29 SB_MA6

SB_DQ30 SB_MA7

SB_DQ31 SB_MA8

SB_DQ32 SB_MA9

SB_DQ33 SB_MA10

SB_DQ34 SB_MA11

SB_DQ35 SB_MA12

SB_MA13

SB_DQ37 SB_MA14

SB_DQ38 SB_MA15

SB_DQ39

SB_DQ40 SB_DQSN0

SB_DQ41 SB_DQSN1

SB_DQ42 SB_DQSN2

SB_DQ43 SB_DQSN3

SB_DQ44 SB_DQSN4

SB_DQ45 SB_DQSN5

SB_DQ46 SB_DQSN6

SB_DQ47 SB_DQSN7

SB_DQ48

SB_DQ49 SB_DQSP0

SB_DQ50 SB_DQSP1

SB_DQ51 SB_DQSP2

SB_DQ52 SB_DQSP3

SB_DQ53 SB_DQSP4

SB_DQ54 SB_DQSP5

SB_DQ55 SB_DQSP6

SB_DQ56 SB_DQSP7

SB_DQ57

SB_DQ58

SB_DQ59

SB_DQ60

SB_DQ61

SB_DQ62

SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

Apple Inc.


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RSVD4

RSVD3

CAA4

CAA2

CAA0

CAA8

CAA9

CAB0

CAA6

CAA7

CAB7

CAA1

CAA3

LPDDR3

CAB6

CAB4

CAB1

CAB2

CAB3

CAB5

CAB8

CAB9

CAA5

LPDDR3

CAB6

CAB4

CAB1

CAB2

CAB3

CAA4

CAA2

CAA0

RSVD2

RSVD1

CAB5

CAB8

CAB9

CAA5

CAA8

CAA9

CAB0

CAA6

CAA7

CAB7

CAA1

CAA3

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

21 61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

21 61 68

61 68

61 68

61 68

61 68

61 68

61

61

20 21 24 61 68

20 21 24 68

20 21 24 68

20 24 68

21 24 68

21 24 68

20 24 68

20 24 68

20 24 68

61

21 24 61 68

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

20 24 61 68

61

61 68

61 68

61 68

61 68

61 68

21 61 68

61 68

61 68

21 24 68

21 24 68

19

19

19

22 24 68

22 24 68

23 24 68

23 24 68

22 24 68

22 24 68

23 24 68

23 24 68

22 23 24 68

22 23 24 68

22 23 24 61 68

61

61

61

61

23 24 61 68

61

61

61

61

61

61

61

61

61

61

61

61

61

22 24 61 68

61

61

61

61 68

61 68

61 68

61 68

61 68

61 68

23 61 68

61 68

61 68

61 68

61 68

61 68

61 68

23 61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

23 61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68

61 68 AP51

AR51

AP49

AW34

AY34

AP32

AU40

AY39

AW39

AV40

AR36

AU39

AP36

AR38

AU42

AV42

AR35

AU41

AW41

AP35

AY37

AU36

AL49

AL42

AW53

AW57

AN55

AN58

AN61

AJ62

AL48

AL43

AV53

AV57

AM55

AM58

AN62

AJ61

AM62

AM63

AK60

AK51

AM51

AK48

AM48

AK61

AK49

AM49

AK46

AM46

AM42

AM40

AK43

AK45

AM45

AM43

AH60

AK42

AK40

AU52

AV52

AU54

AV54

AW52

AY52

AW54

AY54

AH61

AU56

AV56

AU58

AV58

AW56

AY56

AW58

AY58

AN54

AR54

AK62

AK55

AL55

AK54

AM54

AR55

AP55

AN57

AR57

AK58

AL58

AK63

AK57

AM57

AR58

AP58

AP60

AP61

AM60

AM61

AP62

AP63

AH62

AH63

AR32

AP33

AW36

AY36

AU37

AV37

AY43

AY42

AW43

AU43

AU34

AY41

AV35

AU35

U0500

CRITICAL

OMIT_TABLE

BROADWELL-ULT2C+GT2

BGA

AK35

AM35

AL32

AU46

AY47

AY46

AW46

AP45

AR45

AR42

AP42

AP46

AR46

AK33

AU47

AV47

AK36

AR40

AP40

AM18

AM21

AW18

AV22

AM25

AM28

AW26

AV30

AN18

AN21

AV18

AW22

AN25

AN28

AV26

AW30

AW27

AY27

AU29

AP18

AR18

AM20

AK20

AV29

AL18

AK18

AR20

AN20

AK22

AK21

AP21

AN22

AM22

AL21

AU31

AR22

AR21

AU17

AV17

AU19

AV19

AW17

AY17

AW19

AY19

AV31

AU21

AV21

AU23

AV23

AW21

AY21

AW23

AY23

AL25

AK25

AW29

AM26

AK26

AP25

AR25

AR26

AN26

AP28

AR28

AN29

AR29

AY29

AK28

AL28

AK29

AM29

AU25

AV25

AU27

AV27

AW25

AY25

AW31

AY31

AK32

AM32

AV50

AW49

AU50

AY49

AK38

AL38

AM38

AN38

AM33

AU49

AM36

AL35

U0500

2C+GT2BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

CPU DDR3/LPDDR3 Interfaces

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5> MEM_B_CKE<0>




MEM_B_DQ<9>

MEM_B_DQ<10> MEM_B_CS_L<0>

MEM_B_DQ<11> MEM_B_CS_L<1>

MEM_B_DQ<12>

MEM_B_DQ<13> MEM_B_ODT<0>

MEM_B_DQ<14>

MEM_B_DQ<15> =MEM_B_RAS_L

MEM_B_DQ<16> =MEM_B_WE_L

MEM_B_DQ<17> =MEM_B_CAS_L

MEM_B_DQ<18>

MEM_B_DQ<19> =MEM_B_BA<0>

MEM_B_DQ<20> MEM_B_CAB<6>

MEM_B_DQ<21> =MEM_B_BA<2>

MEM_B_DQ<22>

MEM_B_DQ<23> =MEM_B_A<0>



MEM_B_DQ<26> TP_LPDDR3_RSVD3

MEM_B_DQ<27> TP_LPDDR3_RSVD4








MEM_B_DQ<35> MEM_B_CAA<6>

=MEM_B_A<13>



MEM_B_DQ<39>

MEM_B_DQ<40> MEM_B_DQS_N<0>








MEM_B_DQ<48>

MEM_B_DQ<49> MEM_B_DQS_P<0>








MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQ<36>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<2>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_CAB<6>

=MEM_A_BA<0>

=MEM_A_BA<2>

=MEM_A_A<15>

=MEM_A_A<14>

=MEM_A_A<13>

=MEM_A_A<11>

MEM_A_CAA<6>

=MEM_A_A<9>

=MEM_A_A<10>

=MEM_A_A<8>

=MEM_A_A<6>

=MEM_A_A<7>

=MEM_A_A<5>

TP_LPDDR3_RSVD2

TP_LPDDR3_RSVD1

=MEM_A_A<1>

=MEM_A_A<2>

=MEM_A_A<0>

=MEM_A_CAS_L

=MEM_A_WE_L

=MEM_A_RAS_L

MEM_A_ODT<0>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CLK_P<1>

MEM_A_DQ<2>

MEM_A_DQ<26>

MEM_A_DQ<35>

CPU_DIMMA_VREFDQ

CPU_DIMM_VREFCA

CPU_DIMMB_VREFDQ

MEM_A_DQ<12>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<16>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<21>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<34>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<39>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

7 OF 73

7 OF 120

<E4LABEL>

<SCH_NUM>

<BRANCH>

w w w

. c h

i n a

f i x

. c o

mOUT

IN

NCNC

NC

NCNC

NCNC

NCNC

NCNC

NC

BI

NCNC

IN

OUT

IN

NCNCNC

NC

NC

OUT

NC

NCNC

NCNCNCNC

IN

NC

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI

RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

VCCHSIO

VCCHSIO

VCCHSIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL

VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCDSW3_3

VCCCLK

VCCCLK

VCCCLK

VCCACLKPLL

DCPSUS4

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCCASW

VCC1P05

VCC1P05

VCC1P05

VCC1P05

VCC1P05

DCPSUSBYP

DCPSUSBYP

VCCASW

VCCASW

VCCASW

DCPSUS1

DCPSUS1

VCCTS1_5

VCCSDIO

VCCSDIO

RSVD

RSVD

RSVD

RSVD

VCCAPLL

VCC1_05

VCC1_05

VCC1_05

VCC1_05

VCC3_3

VCC3_3

VCC3_3

VCC3_3VCCCLK

VCCCLK

VCCSUS3_3

VCCSUS3_3

VCCSUS3_3

VCCSUS3_3

VCCSUS3_3

HSW ULT POWER

SYM 12 OF 19

VCC

VCC

VCC

VCC

VCC

VCC

VCCST

VCCST

VCCST

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC

RSVD

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

RSVD

RSVD

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VDDQ

VCCIOA_OUT

RSVD

RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

Apple Inc.


124578

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C

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



114mA Max

Max load: 300mA

42mA Max

17mA Max

3mA Max

31mA Max

Powered in DeepSx11mA Max

18mA Max

???mA Max

32A Max

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

213mA Max[1]3.3mA Max[1]

1mA Max[1]

40mA Max[1]

473mA Max[1]

185mA Max[1]

29mA Max[1]

0.3mA Max[1]

59mA Max[1]

41mA Max

WF: RSVD on Sawtooth Peak rev 1.0



1838mA Max

57mA Max

VCCCLK: 200mA Max

1499mA Max[1]

VCCCLK: 200mA Max

Max load: 300mA

R0802.2:

NOTE: Aliases not used on CPU supply outputs

to avoid any extraneous connections.

R0800.2:

R0810.2:

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0.

Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.

2

1R0802

201MF

1301%1/20W

PLACE_NEAR=U0500.L63:2.54mm

49 65

16

2

1R0860

5%

201MF

PLACE_NEAR=U0500.C50:50.8mm100

1/20W

49 65

16 17

17 49

17 49

49 65

2

1 C0899

6.3V10%1UF

CERM402

BYPASS=R0899:U0500:2.54mm

21

R0899

201

1/20W

PLACE_NEAR=U0500.AG19:2.54mm

5.11

MF-LF

1%

49 65

2

1 C0895

BYPASS=U0500.AE7:6.35mm

20%10V

402CERM

0.1UF2

1C0892

BYPASS=U0500.AG10:6.35mm

0.1UF20%10VCERM402

2

1C0891

20%10VCERM402

0.1UF


2

1 C0890

10%6.3VCERM402

1UF


B18

J15

AH11

AE21

AE20

AC9

AA9

Y8

U8

T9

B11

AG10M9

L10

K9

AH14

AH10

T21

R21

K19

J18

J17

AG8

AG14

AG13

AF9

AE9

W21

AA21

A20

W9

V8

K16

K14

P9

N8

J11

H15

H11

AG17

AG16

AF22

AE8

Y20

V21

M20

K18

AC20

AG20

AG19

AB8

J13

AH13

AD8

AD10

AE7

U0500

2C+GT2BROADWELL-ULT

OMIT_TABLE

CRITICAL

BGA

P62

D63

C59

F60

L63

N63

L62

AY50

AY44

AY40

AY35

AR48

AP43

AN33

AJ37

AJ33

AJ31

AH26

B59

AE23

AE22

AC22

E20

A59

W57

U57

E63

P57

M57

M23

L22

K57

K23

J23

H23

G57

G55

G53

G51

G49

G47

G45

G43

G41

G39

G37

G35

G33

G31

G29

G27

G25

G23

F56

F52

F48

F44

F40

F36

F32

F28

F24

E57

E55

E53

E51

E49

E47

E45

E43

E41

E39

E37

E35

E33

E31

E29

E27

E25

E23

C56

C52

C48

C44

C40

C36

C32

C28

C24

AG57

AD57

AB57

F59

V59

U59

P61

P60

N61

N59

T59

N58

L59

J58

AG58

AE60

AE59

AD60

AD59

AD23

AC59

AC58

AB23

AA59

AA23

H59

U0500BROADWELL-ULT

2C+GT2

OMIT_TABLE

CRITICAL

BGA

21

R0811

5%

0

0201

1/20WMF

21

R0812

5%

0

0201

1/20WMF

21

R0810

MF

5%

43

PLACE_NEAR=U0500.L62:38.1mm

1/20W

201

2

1R0800

201

1%

MF1/20W

75

PLACE_NEAR=R0810.1:2.54mm

CPU/PCH POWER


PPVCC_S0_CPU

PP1V05_S0

TP_CPU_RSVDN61

TP_CPU_RSVD_N59

TP_CPU_RSVDP61

TP_CPU_RSVD_P60

CPU_PWR_DEBUG

CPU_VCCSENSE_P

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

PPVCOMP_S0_CPU

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

VOLTAGE=1.05V

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VR_EN

CPU_VCCST_PWRGD

CPU_VR_READY

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

TP_PPVCCIO_S0_CPU

PP1V05_S0SW_PCH_HSIO

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0SW_PCH_VCCSATA3PLL

PP1V05_S0_PCH_VCCAPLL_OPI

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP1V05_S0

PP1V05_S0_PCH_VCCACLKPLL

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

PPVOUT_S0_PCH_DCPRTC

PP3V3_SUS

PP1V05_S0

PP1V05_S0

PPVOUT_S5_PCH_DCPSUSBYP_RMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0

PP1V05_S0

PP3V3_S0

PP3V3_S0PP1V05_S0_PCH_VCC_ICC

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

PP1V05_S0

CPU_VIDSCLK

CPU_VIDALERT_L

CPU_VIDSOUT

PPVOUT_S5_PCH_DCPSUSBYPMIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm

<BRANCH>

<SCH_NUM>

<E4LABEL>

8 OF 120

8 OF 73

8 10 40 50 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

18

18

8 10 40 50 60 62

10 40

5

11 56 60

11 14

11 12

11

11 17 56

11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

6 8 11 15 16 17 36 40 49 53 56 57 60 62

11 12

12 13 17 60 62

8 11 14 18 44 55 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

55 56 57 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43

54 57 59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

11

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

w w w

. c h

i n a

f i x

. c o

m

OUT

SYM 14 OF 19

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SYM 15 OF 19

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SYM 16 OF 19

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS_SENSE

VSS

VSS

VSS

Apple Inc.


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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



2

1R0960

PLACE_NEAR=U0500.E62:50.8mm5%100

1/20WMF201

49 65

AP20

AP17

AP10

AN7

AN63

AN60

AN52

AN51

AN49

AN48

AN46

AN45

AN43

AN42

AN40

AN39

AN36

AN35

AN32

AN31

AN23

AN17

AM52

AM31

AM23

AM17

AM1

AL61

AL60

AL57

AL54

AL52

AL51

AL46

AL45

AL40

AL39

AL36

AL33

AL31

AL29

AL26

AL23

AL22

AL20

AL17

AL13

AL10

AK52

AK3

AK23

AJ63

AJ60

AJ58

AJ56

AJ54

AJ52

AJ50

AJ47

AJ45

AJ43

AJ41

AJ39

AJ35

AJ29

AJ27

AJ25

AJ23

AJ14

AJ13

AH57

AH55

AH53

AH51

AH49

AH44

AH42

AH40

AH38

AH36

AH34

AH32

AH30

AH28

AH24

AH22

AH20

AH19

AH17

AG63

AG62

AG61

AG60

AG23

AG21

AG11

AG1

AF18

AF17

AF15

AF14

AF12

AF11

AE58

AE5

AE10

AD63

AD3

AD21

AC61

AB7

AB22

AB20

AB10

AA58

AA1

A56

A52

A48

A44

A40

A36

A32

A28

A24

A18

A14

A11

U0500BROADWELL-ULT

2C+GT2BGA

CRITICAL

OMIT_TABLE

D31

D30

D29

D27

D26

D25

D23

D21

D2

D18

D14

D12

C57

C39

C38

C27

C25

C20

C18

C14

C11

B60

B56

B52

B48

B44

B40

B4

B36

B32

B28

B26

B24

B20

AY6

AY59

AY57

AY53

AY51

AY4

AY33

AY30

AY26

AY24

AY22

AY18

AY16

AY11

AW60

AW59

AW51

AW50

AW47

AW44

AW42

AW40

AW4

AW37

AW35

AW33

AW24

AW16

AV8

AV59

AV55

AV51

AV49

AV46

AV43

AV41

AV39

AV36

AV34

AV33

AV28

AV24

AV20

AV16

AV14

AU59

AU57

AU55

AU53

AU51

AU33

AU30

AU28

AU26

AU24

AU22

AU20

AU18

AU16

AU1

AT63

AT62

AT61

AT49

AT46

AT43

AT42

AT40

AT37

AT35

AT13

AR52

AR5

AR49

AR43

AR39

AR33

AR31

AR23

AR17

AR15

AR11

AP57

AP54

AP52

AP48

AP39

AP38

AP31

AP3

AP29

AP26

AP23

AP22

U0500

BGA

OMIT_TABLE

CRITICAL

2C+GT2BROADWELL-ULT

Y63

Y59

Y10

W22

W20

V7

V58

V3

V23

V10

U9

U61

U22

U20

T58

T1

E62

R8

R22

R10

P63

P59

N3

N10

M22

L7

L61

L58

L20

L18

L17

L15

L13

K12

K1

J63

J59

J22

J10

H57

H17

H13

G8

G6

G5

G3

G22

G18

F61

F58

F54

F50

F46

F42

F38

F34

F30

F26

F20

E17

E11

D8

D62

D59

D57

D55

D54

D53

D51

D50

D5

D49

D47

D46

D45

D43

D42

D41

D39

D38

D37

D35

D34

D33

AH46

AH16

U0500BROADWELL-ULT

2C+GT2

OMIT_TABLE

CRITICAL

BGA


CPU/PCH GROUNDS

CPU_VCCSENSE_N

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CPU VDDQ DECOUPLING

CPU VCC Decoupling

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603

2x Bulk nostuff per Harris Beach v1.0 schematic

Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

2

1 C1000NO STUFF

4VX6S0402

20%10UF

2

1 C105010UF

0402-1CERM-X5R6.3V20%

2

1 C105110UF

CERM-X5R6.3V20%

0402-1

2

1 C1052

CERM-X5R0402-1

10UF

6.3V20%

2

1 C105310UF

0402-1CERM-X5R6.3V20%

2

1 C1054

CERM-X5R

20%

0402-1

10UF

6.3V2

1 C105510UF

0402-1CERM-X5R6.3V20%

2

1 C1040

6.3VCERM402-LF

2.2UF20%

2

1 C1041

402-LF

6.3VCERM

2.2UF20%

2

1 C1042

6.3VCERM402-LF

20%2.2UF

2

1 C1043

6.3V20%2.2UF

402-LFCERM

2

1 C1060

TANT2V20%270UF

CASE-B2-SM

2

1 C1061NO STUFF

CASE-B2-SMTANT2V20%270UF

2

1 C1001

20%4VX6S0402

NO STUFF

10UF

2

1 C1002

4VX6S

10UF20%

NO STUFF

0402

2

1 C1003

0402

4VX6S

10UF20%

NO STUFF

2

1 C1004

0402

4VX6S

10UF20%

NO STUFF

2

1 C1005NO STUFF

10UF

0402

4VX6S

20%

2

1 C1006

0402

4VX6S

10UF20%

NO STUFF

2

1 C100710UF

0402

4VX6S

20%

NO STUFF

2

1 C1008

0402

4VX6S

10UF20%

NO STUFF

2

1 C1009NO STUFF

20%

0402

4VX6S

10UF

2

1 C1010

0402

4VX6S

10UF20%

NO STUFF

2

1 C1011

0402

4VX6S

10UF20%

NO STUFF

2

1 C1012NO STUFF

0402

4VX6S

10UF20%

2

1 C101310UF

0402

4VX6S

20%

NO STUFF

2

1 C1014

0402

4VX6S

10UF20%

NO STUFF

2

1 C1015

4VX6S

20%10UF

0402

NO STUFF

2

1 C1016

4V20%

0402X6S

NO STUFF

10UF

2

1 C1017

20%10UF

X6S4V

0402

NO STUFF

2

1 C1018

4V20%

0402X6S

10UF

NO STUFF

2

1 C1019

20%4VX6S

10UF

0402

NO STUFF

2

1 C1020

20%

X6S4V

10UF

0402

NO STUFF

2

1 C1021

0402

4VX6S

10UF20%

NO STUFF

2

1 C1084

4VX6S

20%10UF

0402

CRITICAL

2

1 C1083

4VX6S

20%10UF

0402

CRITICAL

2

1 C1082

4VX6S

20%10UF

0402

NO STUFF

2

1 C1081

20%

0402X6S4V

10UF

NO STUFF

2

1 C1080NO STUFF

4VX6S

10UF20%

0402

2

1 C1079

4VX6S

20%10UF

0402

NO STUFF

2

1 C1078NO STUFF

10UF20%

X6S4V

0402

2

1 C1077

20%

X6S4V

10UF

0402

CRITICAL

2

1 C1076

4VX6S

10UF20%

0402

CRITICAL

2

1 C1075NO STUFF

4VX6S

10UF20%

0402

2

1 C107410UF20%4VX6S0402

NO STUFF

2

1 C1073NO STUFF

X6S4V20%

0402

10UF

2

1 C107210UF

X6S4V20%

0402

NO STUFF

2

1 C1071

4VX6S

10UF20%

0402

CRITICAL

2

1 C1070CRITICAL

0402

20%10UF

X6S4V

2

1 C1097

0402

20%10UF

X6S4V

CRITICAL

2

1 C1096

0402

4VX6S

20%10UF

NO STUFF

2

1 C1095

0402

20%10UF

X6S4V

NO STUFF

2

1 C1094

0402

20%10UF

X6S4V

NO STUFF

2

1 C109310UF

0402

20%

X6S4V

NO STUFF

2

1 C1092

0402

10UF20%

X6S4V

CRITICAL

2

1 C1091CRITICAL

0402

4V20%

X6S

10UF

2

1 C1090

0402

20%10UF

X6S4V

NO STUFF

2

1 C1089

0402

20%10UF

X6S4V

NO STUFF

2

1 C1088

0402

20%10UF

X6S4V

NO STUFF

2

1 C1087

0402

20%10UF

X6S4V

CRITICAL

2

1 C108610UF

0402

20%4V

CRITICAL

X6S2

1 C108510UF

0402

20%

X6S4V

CRITICAL

2

1 C1038NO STUFF

0402

10UF20%4VX6S2

1 C1037NO STUFF

0402

4VX6S

10UF20%

2

1 C1036NO STUFF

4V

0402X6S

20%10UF

2

1 C1035NO STUFF

0402

20%10UF

4VX6S2

1 C1034NO STUFF

X6S0402

20%4V

10UF

2

1 C1033NO STUFF

0402

20%4VX6S

10UF

2

1 C1032

0402

10UF20%

X6S4V

NO STUFF

2

1 C1029

0402

20%4VX6S

NO STUFF

10UF

2

1 C109A

0402

10UF20%4VX6S

NO STUFF

2

1 C1099NO STUFF

0402X6S

20%10UF

4V2

1 C1098NO STUFF

0402

4VX6S

20%10UF

2

1 C107BNO STUFF

20%

X6S4V

10UF

0402

2

1 C107A

4V20%10UF

X6S0402

NO STUFF

2

1 C1069NO STUFF

10UF

X6S4V20%

0402

2

1 C1068NO STUFF

0402X6S4V

10UF20%

2

1 C108FNO STUFF

20%4VX6S0402

10UF

2

1 C1067NO STUFF

0402

4VX6S

20%10UF

2

1 C108ENO STUFF

20%4VX6S

10UF

0402

2

1 C1066NO STUFF

0402

10UF20%4VX6S

2

1 C108DNO STUFF

X6S4V20%

0402

10UF

2

1 C108CNO STUFF

X6S4V20%10UF

0402

2

1 C1065NO STUFF

0402

10UF

4V20%

X6S

2

1 C1028NO STUFF

10UF

0402

4VX6S

20%

2

1 C102710UF

0402

4VX6S

20%

NO STUFF

2

1 C1049

0402

NO STUFF

4V20%

X6S

10UF

2

1 C1048

0402

4V20%

X6S

10UF

NO STUFF

2

1 C102610UF

4VX6S0402

20%

NO STUFF

2

1 C1047

0402X6S

10UF

4V20%

NO STUFF

2

1 C1025NO STUFF

10UF20%4VX6S0402

2

1 C1024NO STUFF

10UF

0402

4VX6S

20%

2

1 C1046NO STUFF

0402X6S

10UF

4V20%

2

1 C1045NO STUFF

0402

10UF

4V20%

X6S

2

1 C1023NO STUFF

0402

4VX6S

10UF20%

2

1 C102210UF

NO STUFF

0402

20%4VX6S

2

1 C1044NO STUFF

0402

20%

X6S4V

10UF

2

1 C1039NO STUFF

0402

10UF

X6S4V20%

2

1 C1064NO STUFF

X6S0402

10UF20%4V

2

1 C108B

X6S

20%4V

0402

10UF

NO STUFF

2

1 C1063

0402X6S4V

10UF20%

NO STUFF

2

1 C108ANO STUFF

20%

X6S4V

10UF

0402

2

1 C106210UF20%4VX6S

NO STUFF

0402

2

1 C109FNO STUFF

X6S

10UF

4V20%

0402

2

1 C109ENO STUFF

X6S4V20%10UF

0402

2

1 C1059NO STUFF

10UF

0402

20%4VX6S2

1 C1058NO STUFF

0402

10UF

4VX6S

20%

2

1 C109DNO STUFF

10UF20%4VX6S0402

2

1 C1057NO STUFF

4V

0402X6S

10UF20%

2

1 C109C

X6S

NO STUFF

10UF20%4V

0402

2

1 C1056NO STUFF

0402

10UF

4VX6S

20%

2

1 C109B

X6S4V

0402

10UF20%

NO STUFF

3 2

1 C1031470UF-0.0045OHM

SM

2.5VPOLY-TANT

20%

CRITICAL

2

1 C1030

0402

4VX6S

10UF20%

NO STUFF

2

1 C104C10UF

0402

4VX6S

20%

NO STUFF

2

1 C104D

20%

X6S4V

CRITICAL

10UF

0402

2

1 C104E

20%10UF

X6S4V

0402

NO STUFF

2

1 C104F

20%10UF

X6S4V

0402

CRITICAL

2

1 C106A

20%10UF

X6S4V

0402

CRITICAL

2

1 C106B

20%10UF

X6S4V

0402

NO STUFF

2

1 C106C

20%10UF

X6S4V

0402

NO STUFF

2

1 C106D

0402

4VX6S

10UF20%

NO STUFF

2

1 C106E

0402

4VX6S

10UF20%

NO STUFF

2

1 C105A

20%10UF

X6S4V

0402

NO STUFF

2

1 C105B

20%10UF

X6S4V

0402

CRITICAL

2

1 C105C

20%10UF

X6S4V

0402

CRITICAL

2

1 C105D

20%10UF

X6S4V

0402

NO STUFF

2

1 C105E

0402

4VX6S

10UF20%

NO STUFF

2

1 C105FCRITICAL

0402

4VX6S

10UF20%

2

1 C104ANO STUFF

10UF

0402

4VX6S

20%

2

1 C104BNO STUFF

0402

4VX6S

10UF20%

SYNC_DATE=01/11/2013SYNC_MASTER=LABEL_J41

CPU Decoupling

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

10 OF 73

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??mA Max

PCH OPI VCCAPLL FILTER/BYPASS

57mA Max

31mA Max

??mA Max

42mA Max83mA Max

41mA Max

PCH VCCDSW3_3 BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCHSIO BYPASS

PCH VCCASW BYPASS

(PCH 1.05V ME CORE PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V CLK PWR)

PCH VCCCLK BYPASS

PCH VCC3_3 BYPASS

(PCH 3.3V GPIO/LPC PWR)

PCH VCC3_3 BYPASS

(PCH 3.3V THERMAL PWR)

(PCH 1.05V USB2 PWR)

PCH VCCIO BYPASS

(PCH 1.05V VCCCLK PWR)

PCH VCCCLK FILTER/BYPASS

PCH VCCACLKPLL FILTER/BYPASS

(PCH 1.05V ACLK PLL PWR)

(PCH 3.3V DSW PWR)

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SUSPEND PWR)

PCH VCCSPI BYPASS

(PCH 3.3V SPI PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 3.3V/1.5V HDA PWR)

PCH VCCSDIO BYPASS

(PCH 3.3V/1.8V SDIO PWR)

PCH VCCSUSHDA BYPASS

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0

as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 1.05V USB3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS

(PCH 1.05V SATA3 PLL PWR)

PCH VCC BYPASS

(PCH 1.05V CORE PWR)

2

1C1202

BYPASS=U0500.Y8:6.35mm

CERM402

0.1UF20%10V

NO STUFF

21

L1280

0603

2.2UH-240MA-0.221OHM

CRITICAL

NO STUFF

21

R12800

MF-LF402

5%1/16W

2

1C1295

0805-1

47UF20%4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

2

1C1296

0805-1

47UF20%4V

CERM-X5R


NO STUFF

2

1C1290


CERM-X5R4V

20%47UF

0805-1

2

1C1291

0805-1

47UF20%4V

CERM-X5R


NO STUFF

2

1C1280

BYPASS=U0500.AA21:12.7mm

0805-1

47UF20%4V

CERM-X5R

NO STUFF

2

1C1281

CERM-X5R4V

20%47UF


0805-1

NO STUFF

2

1C1275

BYPASS=U0500.J18:12.7mm

4V20%

47UF

0805-1CERM-X5R 2

1C1276

0805-1

47UF20%4V

CERM-X5R


2

1C1270

CERM-X5R

BYPASS=U0500.A20:12.7mm

0805-1

47UF20%4V

2

1C1271

CERM-X5R4V

20%47UF

0805-1


2

1C1200

6.3V10%

402CERM

1UF

BYPASS=U0500.AH10:6.35mm

NO STUFF

2

1C1210


6.3V10%1UF

CERM402

2

1C1214

BYPASS=U0500.K14:6.35mm

CERM402

10V20%

0.1UF

2

1C1206


402CERM6.3V

1UF10%

2

1C1264

402CERM


1UF10%

6.3V

2

1C12611UF

CERM402

10%6.3V

BYPASS=U0500.L10:6.35mm

2

1 C1262

0402-1

20%10UF

CERM-X5R

BYPASS=U0500.M9:6.35mm

6.3V

2

1C1266

6.3VCERM402

1UF10%


2

1C1255


6.3V20%

603X5R

10UF

2

1C1250


X5R-CERM-16.3V20%

22UF

603

NO STUFF

2

1 C1256


6.3V

402

10%1UF

CERM 2

1 C12571UF


6.3V10%

402CERM

2

1 C1251


6.3V10%

402CERM

1UF

2

1C1267

6.3VCERM402

1UF10%

BYPASS=U0500.R21:6.35mm

2

1C1204

X5R-CERM-16.3V20%

22UF

603

BYPASS=U0500.AC9:12.7mm

2

1C121222UF

20%6.3V

X5R-CERM-1

BYPASS=U0500.V8:12.7mm

603

2

1C1208

BYPASS=U0500.U8:6.35mm

402CERM6.3V

1UF10%

2

1C1260

BYPASS=U0500.K9:6.35mm

1UF

402

10%6.3VCERM

2

1 C1277

10V10%

402X5R

1UF


21

L12752.2UH-240MA-0.221OHM

0603

CRITICAL

2

1 C1297

10V10%

402X5R

1UF


21

L1295CRITICAL

0603

2.2UH-240MA-0.221OHM

2

1 C1292

10V10%

402X5R

1UF


21

L12902.2UH-240MA-0.221OHM

CRITICAL

0603

21

R12750

1/16W5%

402MF-LF

2

1 C12721UF

X5R402

10%10V


21

L1270

0603

CRITICAL

2.2UH-240MA-0.221OHM

21

R1270

5%

402MF-LF1/16W

0

2

1 C12821UF

X5R402

10%10V



PCH Decoupling

PP1V05_S0

PP3V3_SUS

PP3V3_S0


PP3V3_S5

PP3V3_SUS

PP3V3_SUS

PP1V05_S0PP3V3_S0

PP3V3_S0

PP1V05_S0

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCCACLKPLL_R

PP1V05_S0


VOLTAGE=1.05VMIN_NECK_WIDTH=0.075 MMMIN_LINE_WIDTH=0.2 MMPP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0


VOLTAGE=1.05VMIN_NECK_WIDTH=0.075 MMMIN_LINE_WIDTH=0.2 MMPP1V05_S0SW_PCH_VCCSATA3PLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCC_ICC_R

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MMVOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCCACLKPLL


MIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05VMIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

11 OF 73

12 OF 120

<E4LABEL>

<SCH_NUM>

<BRANCH>

6 8 11 15 16 17 36 40 49 53 56 57 60 62

8 11 14 18 44 55 56 57 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8 17 56

8 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

8 11 56 60

8 14

6 8 11 15 16 17 36 40 49 53 56 57 60 62

8 11 56 60

8 12

8 12

8

8

w w w

. c h

i n a

f i x

. c o

mIN IN

IN

IN

IN

IN

IN

OUT

BI

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

RSVD

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1

RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD

HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34

SATA1GP/GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

SYM 6 OF 19

CLOCK SIGNALS

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

TESTLOW

TESTLOW

TESTLOW

DIFFCLK_BIASREF

RSVD

RSVD

OUT

OUT

IN

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

NC

NC

NC

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

NC

NC

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

NCNC

OUT

OUT

IN

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPD)

SSD Lane 0

SSD Lane 2

PCIe Port assignments:

SSD Lane 3

(IPD-PWROK)

(IPD-PLTRST#)

(IPU)

(IPD)

Secondary HDD/SSD

Unused

Primary HDD/SSD

Reserved: ODD

SATA Port assignments:

SSD Lane 1

(IPD-PLTRST#)

(IPU)

(IPU)

16 62 67

21R1345 100K1/20W5% 201MF

21R1375 100KMF5% 1/20W 201

16

12 16

12 16

15 16

21R1343 100K5% 201MF1/20W

16 62 67

16 62 67

16 62 67

16

AV6

U3

D17

C15

B17

A15

C17

B14

A17

B15

E5

H6

H8

H5

F5

J6

J8

J5

C12

A12

AC1

V6

U1

V1

AY5

AW5

AU7

L11

K10

AV2

AL11

AC4

AU62

AD62

AE61

AD61

AE62

AE63

AV7

AU6

AY8

AV11

AU11

AU12

AY10

AU8

AV10

AW10

AW8

U0500

2C+GT2BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

B25

A25

C35

C34

AL8

AK8

M21

K21

T2

U5

N1

AD1

Y5

U2

C26

A37

B39

C37

B42

A41

C42

B37

A39

B38

C41

B41

C43

AP15

AN15

A35

B35

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT2C+GT2

25 67

25 67

12 25

29 62 67

12 29

29 62 67

32 67

32 67

12 31

30 62 65

30 62 65

12 30

21R13762011/20W5% MF

100K

59 63 67

21R1377 100KMF5% 1/20W 201

59 63 67

59 63 67

21R1312201

33MF5% 1/20W


21R1311 331/20W5% MF

PLACE_NEAR=U0500.AV11:1.27mm201

59 63 67

21R1310 33MF 2015% 1/20W

PLACE_NEAR=U0500.AW8:1.27mm

17

2

1R1302330K

1/20W5%

201MF

2

1R1301

1/20W5%

201MF

1M

2

1C13001UF

X5R402

10%10V

2

1R130020K

MF201

5%1/20W

2

1 C1303

X5R402

1UF10%10V

2

1R1303

MF1/20W

20K

201

5%

6 16 62 65

2

1R1370

201MF

3.01K

1/20W1%


30 65

30 65

30 62 65

30 62 65

30 65

30 65

30 62 65

30 62 65

30 65

30 65

30 65

30 65

30 62 65

30 62 65

30 62 65

30 62 65

59 63 67

2

1R13803.01K

MF201

1%


1/20W

17 67

21R13902015% 1/20W MF

10K

21R13915%

10K1/20W 201MF

21R13925%

10K1/20W MF 201

21R1393201MF1/20W

10K5%

17

17

17

21R1313MF5% 1/20W

33

PLACE_NEAR=U0500.AU11:1.27mm201

21R1341 100KMF 2015% 1/20W

21R13441/20W5% 201MF

100K

21R1340 100KMF 2015% 1/20W

21R1342 100K1/20W 201MF5%


PCH Audio/JTAG/SATA/CLKXDP_PCH_UART_SSD_L_BT_H

XDP_PCH_GPIO35

XDP_PCH_UART_SSD_L_BT_H

PP3V3_S0

PCH_SATALED_L

XDP_PCH_GPIO35

XDP_FW_PME_L

SSD_CLKREQ_L

TBT_CLKREQ_L

AP_CLKREQ_L

FW_CLKREQ_L

CAMERA_CLKREQ_L

ENETSD_CLKREQ_L

PP1V05_S0_PCH_VCCACLKPLL

PPVRTC_G3H

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_RST_L

PCH_SATA_RCOMP

PCH_SATALED_L

PCH_JTAGX

XDP_PCH_TMS

XDP_PCH_TDO

XDP_PCH_TCK

XDP_PCH_TDI

XDP_CPUPCH_TRST_L

PP1V05_S0SW_PCH_VCCSATA3PLL

XDP_SSD_PCIE0_SEL_L

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

TP_PCH_I2S1_SCLK

TP_PCH_I2S1_SFRM

HDA_SDOUT_R

NC_HDA_SDIN1

HDA_SDIN0

HDA_SYNC_R

HDA_RST_R_L

PCH_SRTCRST_L

PCH_INTRUDER_L

PCH_INTVRMEN

RTC_RESET_L

NC_RTC_CLK32K_RTCX2

PCH_CLK32K_RTCX1

HDA_BIT_CLK_R

TP_PCH_I2S1_TXD

PCH_DIFFCLK_BIASREF

PCH_TESTLOW_AL8

PCH_TESTLOW_AK8

PCH_TESTLOW_C35

PCH_TESTLOW_C34

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT

TP_ITPXDP_CLK100MP

TP_ITPXDP_CLK100MN

LPC_CLK24M_SMC_R

TP_LPC_CLK24M_LPCPLUS_R

ENETSD_CLKREQ_L

TP_PCIE_CLK100M_ENETSDN

TP_PCIE_CLK100M_ENETSDP

CAMERA_CLKREQ_L

PCIE_CLK100M_CAMERA_P

PCIE_CLK100M_CAMERA_N

AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

FW_CLKREQ_L

NC_PCIE_CLK100M_FWP

NC_PCIE_CLK100M_FWN

TBT_CLKREQ_L

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

SSD_CLKREQ_L

13 OF 120

<E4LABEL>

<SCH_NUM>

<BRANCH>

12 OF 73

12 16

12 16

8 11 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 60

62 63 72

12

12 30

12 25

12 29

12

12 31

12

8 11

8 13 17 60 62

12

8 11

17 67

62

67

67

67

12

12

62

62

w w w

. c h

i n a

f i x

. c o

mIN

OUT

IN

OUT

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79

PIRQD*/GPIO80

PIRQA*/GPIO77

PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN

DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

NC

08

NC

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SLP_S0# Isolation

SLP_S0# can be driven high outside of S0

U1420 ensures signal will only be high in S0.

(IPD-PLTRST#)

(IPU)

(IPU)

(IPD-DeepSx)

(IPD-DeepSx)

(IPD-PLTRST#)

(IPU)

R1400 kept for debug purposes.

57 62

13 18 35

37

37

AJ5

AC3

AG2

AV4

AE6

AK2

AG4

AM5

AP4

AP5

AJ6

AT4

AF3 AJ7

AL5

AW6

AL7

AG7

AY7

AW7

AV5

V5

AN4

AB5

AJ8

U0500

2C+GT2BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

AD4

N2

N4

P4

U6

U7

L3

L4

L1

R5

C6

D6

A9

B8

A8

D11

D9

A6

B6

C8

C9

B9

B5

C5

U0500

2C+GT2BROADWELL-ULT

OMIT_TABLE

CRITICAL

BGA

13 30

15 16 18

21R14415% 2011/20W MF

100K

13 17

13 17

16 17 35

17 35 62

13 40 57

13 17 18 35 57

13 18 29 34 35 57

13 35 57

36 67

35 62

13 35 62

13 29 31 62

2

1R1451100K

MF1/20W

201

5%

35

2

1R1450330K

MF1/20W

201

5%

13 54

54

13 58

25 65

18 25 65

18 25 65

25 65

18 28

18

18

18 28

25

18 25

58

21R1446 100KMF1/20W 2015%

21R1445 100KMF1/20W 2015%

21R1442 100KMF1/20W 2015%

21R1443 100KMF1/20W 2015%

2

1R1400NO STUFF

MF1/20W

0201

05%

21R14405% 2011/20W MF

100K

13 26

13 35

13 62

13 62

13 62

13 62

13 62

13 27 35

21R1455 10KMF1/20W 2015%

21R1410 10KMF1/20W 2015%

21R1447 100KMF1/20W 2015%

21R1448 100KMF1/20W 2015%

21R1449 100KMF1/20W 2015%

21R1431 100KMF1/20W 2015%

21R1430 100KMF1/20W 2015%

35 36

13 57 59 63

21R1405 1KMF1/20W 2015%

21R1452 10KMF1/20W 2015%

21R1460 100KMF1/20W 2015%

21R1461 100KMF1/20W 2015%

21R1462 100KMF1/20W 2015%

21R1464 100KMF1/20W 2015%

21R1463 100KMF1/20W 2015%

13 16 35

4

6

53

1

2

U1420

SOT89174LVC1G08

CRITICAL

2

1 C14200.1UF

10V10%

X5R-CERM0201

SYNC_MASTER=J43_MLB SYNC_DATE=02/20/2013

PCH PM/PCI/GFX

HDMITBTMUX_FLAG

PPVRTC_G3H

PCIE_WAKE_L

PM_CLKRUN_L

PM_SLP_S5_L

TBT_PWR_REQ_L

SSD_BOOT

ODD_PWR_EN_L

HDMITBTMUX_LATCH

ENET_LOW_PWR

AP_PCIE_DEV_WAKE

AUD_PWR_EN

PP3V3_S5

PM_PWRBTN_L

PM_BATLOW_L

PP3V3_S0

PM_SLP_S0_L

PM_SLP_S4_L

PM_SLP_S3_L

PM_SLP_S0_L

HDMITBTMUX_FLAG

EDP_PANEL_PWR

EDP_BKLT_EN

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

PM_SLP_SUS_L

TP_PM_SLP_A_L

PM_SLP_S3_L

PM_SLP_S4_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PCIE_WAKE_L

PM_CLKRUN_L

PCH_DSWVRMEN

PM_DSW_PWRGD

PM_PCH_SYS_PWROK

PLT_RESET_L

PCH_SUSACK_L

PM_SYSRST_L

PM_PCH_PWROK

PM_PCH_PWROK

PM_RSMRST_L

PCH_SUSWARN_L

PM_PWRBTN_L

SMC_ADAPTER_EN

PM_BATLOW_L

PCH_PM_SLP_S0_L

TP_PCH_SLP_WLAN_L

EDP_PANEL_PWR

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_DDC_DATA

DP_TBTSNK1_DDC_CLK

DP_TBTSNK1_AUXCH_C_N


DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_C_P


DP_TBTSNK1_HPD

DP_INT_HPD

EDP_BKLT_PWM

EDP_BKLT_EN

SMC_RUNTIME_SCI_L

TBT_PWR_REQ_L

NC_PCI_PME_L

ODD_PWR_EN_L

HDMITBTMUX_LATCH

ENET_LOW_PWR

AUD_PWR_EN

SSD_BOOT

AP_PCIE_DEV_WAKE

SMC_RUNTIME_SCI_L

PP3V3_S0

14 OF 120

<E4LABEL>

<SCH_NUM>

<BRANCH>

13 OF 73

8 12 17 60 62

13 29 31 62

13 35 62

13 35 57

13 26

13 30

13 62

13 62

13 62

13 62

13 57 59 63

8 11 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

13 16 35

13 27 35

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

13 18 29 34 35 57

13 17 18 35 57

13 18 35

13 62

13 58

13 54

13 40 57

62

13 35

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

w w w

. c h

i n a

f i x

. c o

m

OUT

IN

IN

IN

OUT

IN

OUT

OUT

USB

PCI-E

SYM 11 OF 19

PCIE_RCOMP

PCIE_IREF

RSVD

RSVD

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42

OC3*/GPIO43

RSVD

RSVD

USBRBIAS*

USBRBIAS

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

PERN1/USB3RN3

PERN2/USB3RN4

PERP1/USB3RP3

PERP2/USB3RP4

PETN1/USB3TN3

PETN2/USB3TN4

PETP1/USB3TP3

PETP2/USB3TP4

USB3RN1

USB3RN2

USB3RP1

USB3RP2

USB3TN1

USB3TN2

USB3TP1

USB3TP2

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2

LAD3

LAD1

SPI_CLK

LAD0 SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

NCNC

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

NCNC

BI

BI

BI

IN

BI

BI

BI

BI

BIOUT

BI

BI

OUT

BI

BI

BI

BI

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

BI

OUT

BI

BI

IN

BI

BI

Apple Inc.


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6 3



page, may be wire-ORed into other signals.

SML1ALERT# pull-up not provided on this

Unused

(& Ethernet if combo)

Thunderbolt lane 3

Thunderbolt lane 2

Thunderbolt lane 1

PCIe Port Assignments:

USB3 Port Assignments:

Thunderbolt lane 0

Reserved: FireWire

AirPort

Camera

Ext B (SS)

USB Port Assignments:

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

Reserved: SD (HS)

(IPU/IPD)

(IPU)

(IPU/IPD)

(IPU/IPD)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

Trackpad

Reserved: Camera

(IPD)

SD Card Reader

Ext A (SS)

Otherwise, 100k pull-up to 3.3V SUS required.

(IPU)

25 67

21R1580 100K5% MF1/20W 201

21R1581 100K5% 1/20W MF 201

14 16 33

14 16 59 63

14 16

18 37

14 16

25 67

14 62

AJ10

AJ11

A33

B34

B33

C33

F18

H20

E18

G20

AP13

AN11

AN13

AL15

AT10

AP8

AT7

AM8

AR13

AP11

AM13

AM15

AR10

AR8

AR7

AN8

E15

E13

AN10

AM10

A21

C21

A23

C22

A29

B30

A31

C31

B22

B21

B23

C23

B29

C29

B31

C30

F6

G10

E8

E10

G13

F11

G15

F17

E6

H10

F8

F10

F13

G11

F15

G17

A27

B27 AV3

AH2

AT1

AL3

U0500

2C+GT2BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

AA2

AA4

AF1

Y6

AC2

Y4

Y7

AA3

AH3

AU3

AU4

AK1

AN1

AL2

AH1

AP2

AN2

AV12

AW11

AY12

AW12

AU14

AF4

AD2

AF2

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT2C+GT2

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

63 66

63 66

63 66

63 66

32 67

32 67

32 67

32 67

29 67

29 67

29 62 67

29 62 67

2

1R15003.01K

201MF

1%

PLACE_NEAR=U0500.A27:2.54mm

1/20W

59 63 66

59 63 66

59 63 66

59 63 66

33 66

25 67

33 66

33 66

33 66

2

1R157022.6

201

1%1/20WMF

PLACE_NEAR=U0500.AJ10:2.54mm

34 62 66

34 62 66

62

25 67

62

29 66

29 66

59 63 66

59 63 66 25 67

33 66

33 66

35 62 67

35 62 67

35 62 67

35 62 67

35 62 67

21R15431/20W5% 201MF

33

21R15422011/20W MF5%

33

25 67

21R1544 33MF 2015% 1/20W

21R15405% 1/20W 201MF

33

21R15411/20W5% 201MF

33

44 67

44 67

32 35 38 41 42 62 67 71

25 67

32 35 38 41 42 62 67 71

38 67

38 67

16 19 38 54 67

16 19 38 54 67

44 67

44 67

25 67

14 44 67

14 44 67

21R15912011/20W MF5%

100K

21R1549 1K5% MF1/20W 201

21R1590 100K5% 1/20W MF 201

21R1548 1K5% MF1/20W 201

21R1582 100K5% 1/20W MF 201

21R1583 100K201MF5% 1/20W


PCH PCIe/USB/LPC/SPI/SMBus

SPI_IO<3>

SPI_MISO

SPI_IO<2>

TP_SPI_CS2_L

SPI_MOSI_R

SPI_CS0_R_L

TP_SPI_CS1_L

LPC_FRAME_R_L

LPC_AD_R<2>

LPC_AD_R<3>

LPC_AD_R<1>

SPI_CLK_R

LPC_AD_R<0> PCH_SMBALERT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

WOL_EN

SML_PCH_0_CLK

SML_PCH_0_DATA

SMBUS_SMC_1_S0_SCL

PCH_SML1ALERT_L

SMBUS_SMC_1_S0_SDA

NC_CLINK_CLK

NC_CLINK_DATA

NC_CLINK_RESET_L

PCH_PCIE_RCOMPPP1V05_S0SW_PCH_VCCUSB3PLL

NC_PCIE_FW_R2D_CP

NC_PCIE_FW_R2D_CN

NC_PCIE_FW_D2RP

NC_PCIE_FW_D2RN

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<2>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

NC_USB_SDP

NC_USB_SDN

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<3>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

XDP_USB_EXTB_OC_L

XDP_USB_EXTA_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

PCH_USB_RBIAS

USB_EXTA_N

USB_EXTA_P

USB_EXTB_N

USB_EXTB_P

USB_BT_N

USB_BT_P

NC_USB_IRN

NC_USB_IRP

USB_TPAD_N

USB_TPAD_P

TP_USB_5N

TP_USB_5P

NC_USB_CAMERAN

NC_USB_CAMERAP

NC_USB3RPCIE_SD_D2RN

PCIE_CAMERA_D2R_N

NC_USB3RPCIE_SD_D2RP

PCIE_CAMERA_D2R_P

NC_USB3RPCIE_SD_R2D_CN

PCIE_CAMERA_R2D_C_N

NC_USB3RPCIE_SD_R2D_CP

PCIE_CAMERA_R2D_C_P

USB3_EXTA_D2R_N

USB3_EXTB_D2R_N

USB3_EXTA_D2R_P

USB3_EXTB_D2R_P

USB3_EXTA_R2D_C_N

USB3_EXTB_R2D_C_N

USB3_EXTA_R2D_C_P

USB3_EXTB_R2D_C_P

PP3V3_SUS

PP3V3_SUS

XDP_USB_EXTD_OC_L

SPI_IO<2>

PCH_SMBALERT_L

SPI_IO<3>

WOL_EN

XDP_USB_EXTC_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTA_OC_L

LPC_AD<2>

LPC_AD<0>

LPC_AD<1>

LPC_AD<3>

LPC_FRAME_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

15 OF 120

14 OF 73

14

62

62

62

8 11

62

62

62

62

62

62

66

62

62

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

14 16

14 44 67

14

14 44 67

14 62

14 16

14 16 59 63

14 16 33

w w w

. c h

i n a

f i x

. c o

mIN

OUT

BI

BI

LPIO

GPIO

CPU/MISC

SYM 10 OF 19

SPKR/GPIO81

GPIO10

GPIO9

GPIO46

GPIO45

GPIO14

GPIO25

GPIO13

HSIOPC/GPIO71

GPIO50

GPIO49

GPIO48

GPIO44

GPIO47

GPIO59

GPIO58

GPIO57

GPIO56

GPIO26

GPIO27

GPIO28

GPIO24

GPIO16

GPIO17

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

BMBUSY*/GPIO76

SDIO_D3/GPIO69

SDIO_D2/GPIO68

SDIO_D1/GPIO67

I2C0_SDA/GPIO4

UART1_TXD/GPIO1

UART1_CTS*/GPIO3

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

GSPI0_MOSI/GPIO86

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

GSPI0_CS*/GPIO83

RSVD

RSVD

PCH_OPI_COMP

RCIN*/GPIO82

SERIRQ

GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RST*/GPIO2

I2C1_SDA/GPIO6

I2C0_SCL/GPIO5

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66SDIO_POWER_EN/GPIO70

DEVSLP0/GPIO33

DEVSLP1/GPIO38

DEVSLP2/GPIO39

THERMTRIP*

IN

OUT

IN

OUT

ININ

IN

IN

OUT

OUT

OUT

IN

IN

IN

BI

BI

BI

OUT

NCOUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

OUT

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

BI

BI

BI

IN

OUT

BI

OUT

OUT

OUT

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




TABLE_BOMGROUP_ITEM

No-Stuffed R1634

R1616 should also be stuffed if

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

platform does not use SD card

(IPD-PLTRST#)

(IPD-PLTRST#)

GPIO12:

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Pull-up/down on chipset support page (depends on TBT controller)

(IPD-PLTRST#)Requires connection to SMC via 1K series R

(IPD-DeepSx)

(IPD-RSMRST#)

(IPD)

(IPD)

TBTLC for CR, S0 for RR

Pull-up on TBT page

Stuffed R1632

SSD_LPSR:S0 BOM option is on R1620

21R1652 10KMF 2015% 1/20W

21R1674 100K1/20W5% 201MF

21R1676 100K1/20W5% 201MF

2

1R1639

5%1/20W

MF201

100K

21R16411/20W 201

1KMF5%

21R1629201

100KMF1/20W5%

2

1R1621

1/20W

100K5%

MF201

13 15 16 18

18 25

25

15 35 62

G2

K4

J3

J4

K3

J1

J2

G1

D60

V2

T4

C4

E2

C3

E4

D3

F4

E3

AF20

AB21

V4

AW15

AM7

G4

F1

F2

F3

Y2

K2

N7

R7

L5

L8

N6

R6

L6

AM3

AU2

AT5

AL4

AP1

AG6

P3

Y3

U4

AB6

AG3

AG5

AK4

AD7

AN5

AN3

AM4

AD5

T3

Y1

AD6

AH4

AT3

AM2

N5

L2

P2

P1

U0500

BGA

OMIT_TABLE

CRITICAL

BROADWELL-ULT2C+GT2

2

1R1631100K

MF201

5%1/20W

RAMCFG3:H

15 29

29

2

1R1671

201

5%100K

1/20WMF

13 15 16 18

2

1R1680

5%1/20W

MF201

100K

18 31

2

1R168105%1/20WMF0201

2

1R1682

0201MF1/20W5%0

15 34

21R1668 47K1/20W5% 201MF

2

1R1636RAMCFG2:H

100K

MF201

5%1/20W

21R1669MF 2015% 1/20W

47K

21R1670 47K1/20W5% 201MF

21R1677MF 2015% 1/20W

47K

21R1672 47K1/20W5% 201MF

21R1673MF 2015% 1/20W

47K

21R1675 47K1/20W5% 201MF

15 18

15

21R1678MF

2.2K5% 1/20W 201

21R16792011/20W5%

2.2KMF

2

1R1635RAMCFG1:H

5%

201MF

1/20W

100K

15 18 19 34 38 39 56 60 62 63

2

1R1696SSD_LPSR:S3

1/20W

100K5%

MF201

2

1R1611RAMCFG0:H

100K

1/20WMF201

5%

26

15 62

15 62

15 62

15 62

37

15 16

15 16 18

15 16 62

15 34

18

15 30 56 57 62

15 62

15 63

15 25

15 16 18 25

15 16 18 25

15 18

15 56

15 44 62

15 18

15 30 62

15 29

30

15 35

15 63

15

36 65

15 16

15 16 18

15 16 18

15 16 18

18 25

15 34

15 16 63

15 34

15 34 66

15 34 66

2

1R1650

5%1K

1/20WMF

201

15 34 66

21R1610201MF5% 1/20W

100K

21R1614MF1/20W 2015%

100K

21R16155% MF 2011/20W

100K

21R1616 100K5% 201MF1/20W

SD_ON_MLB

21R1617 100K1/20W5% MF 201

21R1618 100K1/20W5% 201MF

21R1619201

100K1/20W MF5%

21R16201/20W 201

100K5% MF

SSD_LPSR:S021R1622 100K

5% 1/20W 201MF21R1623

2015% 1/20W

100KMF

21R1624MF 2011/20W5%

100K

21R1625MF5% 1/20W

100K201

21R1626MF 201

100K5% 1/20W

21R16275% 1/20W

100K201MF

21R16281/20W 201MF5%

100K

21R1630MF 2015% 1/20W

100K

21R1632 100K1/20W5% 201MF

21R1633 100KMF 2015% 1/20W

21R1634 100K1/20W5% 201MF

NOSTUFF

21R1640 100K1/20W5% 201MF

21R16371/20W MF 2015%

100K

21R1638 100K1/20W5% 201MF

21R16911/20W5% 201MF

100K

21R1694MF 2015% 1/20W

100K

21R1693MF 2015% 1/20W

100K

2

1R1655

MF1/20W1%

201

49.9

PLACE_NEAR=U0500.AW15:2.54mm

21R1695MF 2015% 1/20W

100K

21R1660 100K1/20W5% 201MF

21R16611/20W5% 201MF

100K

21R1662MF 2015% 1/20W

100K

21R1663 100K1/20W5% 201MF

21R1664 47K1/20W5% 201MF

21R1665 47K1/20W5% 201MF

21R1666 47KMF 2015% 1/20W

21R1667 47K1/20W5% 201MF

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAMCFG_SLOT


PCH GPIO/MISC/LPIOSSD_SR_EN_L

PP3V3_S0

AP_S0IX_WAKE_SEL

PP3V3_S3

SSD_PWR_EN

TPAD_SPI_INT_GPIO28_L

PCH_I2C1_SCL

PP3V3_S0

PCH_I2C1_SDA

CAM_PCIE_RESET_L

SSD_RESET_L

PLT_RESET_L

AP_RESET_L

PLT_RESET_L

AP_S0IX_WAKE_L

PCH_I2C1_SDA

PCH_I2C1_SCL

PCH_BT_UART_D2R

PCH_TCO_TIMER_DISABLE

XDP_MLB_RAMCFG2

XDP_MLB_RAMCFG1

CAMERA_PWR_EN_PCH

XDP_MLB_RAMCFG3

SPIROM_USE_MLB

TPAD_SPI_IF_EN

PCH_HSIO_PWR_EN

JTAG_TBT_TMS_PCH

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

SD_PWR_EN

TBT_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

HDD_PWR_EN

PCH_TBT_PCIE_RESET_L

TPAD_USB_IF_EN

SMC_WAKE_SCI_L


SD_RESET_L

XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

TP_MEM_VDD_SEL_1V5_L

HDMITBTMUX_SEL_TBT

XDP_MLB_RAMCFG0

XDP_PCH_GPIO76

LCD_PSR_EN

LCD_IRQ_L

ENET_MEDIA_SENSE

PCH_UART1_TXD

PCH_UART1_CTS_L

PCH_UART1_RXD

AUD_SPI_MOSI

TPAD_SPI_CS_L

TPAD_SPI_CLK

AUD_SPI_CLK

AUD_SPI_MISO

AUD_SPI_CS_L

PCH_OPI_COMP

TBT_CIO_PLUG_EVENT_L

LPC_SERIRQ

TPAD_SPI_MISO

TPAD_SPI_MOSI

PCH_BT_UART_R2D

TBT_POC_RESET_L

BT_PWRRST_L

PCH_STRP_TOPBLK_SWP_LAP_S0IX_WAKE_SEL

SSD_SR_EN_L

PM_THRMTRIP_L

XDP_PCH_GPIO17

SMC_WAKE_SCI_L

HDD_PWR_EN

SSD_PWR_EN

SD_PWR_EN

TBT_PWR_EN

PP3V3_S0


TPAD_USB_IF_EN

JTAG_TBT_TMS_PCH

SD_RESET_L

XDP_LPCPLUS_GPIO

TPAD_SPI_MOSI

TPAD_SPI_MISO

TPAD_SPI_CLK

TPAD_SPI_CS_L

AUD_SPI_MOSI

AUD_SPI_MISO

AUD_SPI_CLK

AUD_SPI_CS_L

AP_S0IX_WAKE_L

JTAG_ISP_TDO

PP3V3_S3

PP3V3_S3RS0_CAMERA

PP3V3_S3

XDP_PCH_GPIO76

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

LCD_PSR_EN

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG2

PP1V05_S0

ENET_MEDIA_SENSE

LCD_IRQ_L

CAMERA_PWR_EN_PCH

TPAD_SPI_IF_EN

PCH_HSIO_PWR_EN

XDP_FW_PME_L

LPC_SERIRQ

BT_PWRRST_L

PP3V3_S0

PP3V3_S3

PP3V3_S0

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG0

SPIROM_USE_MLB

PP3V3_S5

TPAD_SPI_INT_L

TPAD_SPI_INT_L


PCH_BT_UART_D2R

PCH_BT_UART_R2D

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_UART1_TXD

PCH_UART1_RXD

PCH_UART1_CTS_L

JTAG_ISP_TDO



15 OF 73

<BRANCH>

<SCH_NUM>

<E4LABEL>

16 OF 120

15 30 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

15 29

15

15

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

15

15

15

15 62

15

15

15

15 62

15 62

15 62

15 62

15 62

15 16

15 35

15 62

15 30 56 57 62

15 63

15 25

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60

62 63 72

15 16 63

15 34

15 18

15 63

15 16 62

15 34 66

15 34 66

15 34 66

15 34

15 62

15 62

15 62

15 62

15 29

15 18

15 18 19 34 38 39 56 60 62 63

31 39

15 18 19 34 38 39 56 60 62 63

15 16

15 16 18 25

15 16 18 25

15 62

15 16 18

15 16 18

6 8 11 16 17 36 40 49 53 56 57 60 62

15 62

15 62

15 18

15 34

15 56

12 16

15 35 62

15 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

15 18 19 34 38 39 56 60 62 63

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

15 16 18

15 16 18

15 44 62

8 11 13 16 17 18 28 29 40 52 55 56 57 58 60 62 72

15 34

15

15 62

15 62

15 62

15 62

15 62

15 62

15

15

15

15

w w w

. c h

i n a

f i x

. c o

m

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

NCNC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

TP

TP

TP

TP

TP

TP

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

IN

TP

OUT IN

BI

OUT

TP

TPBI

TPBI

TPBI

BI

IN OUT

OUT

OUT

OUT

BI

BI

IN

OUT

IN OUT

BI

TP

IN

OUT

Y

NC NC

VCC

GND

A

NC

IN

NC

IN

TP

IN

TP

IN

VER 3

D SG

VER 3

D SG

VER 3

D SG

VER 3

D SG

OUT TP

TP

TP

IN

BI

IN

OUT

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



VCC_OBS_AB

PWRGD/HOOK0

OBSDATA_B2

518S0847

CPU JTAG Isolation

TCK0

OBSDATA_D1

OBSDATA_B3

NOTE: Must not short XDP pins together!

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

via Top-Side Probe. Nets are listed here to show XDP associations and to make clear

These signals do not connect to XDP connector in this architecture, only accessible

Non-XDP Signals

PCH XDP Signals

RESET#/HOOK6

PCH/XDP Signals

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

Unused & MLB_RAMCFGx GPIOs have TPs.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

TDI and TMS are terminated in CPU.

HOOK2

TDO

TRSTn

Merged (CPU/PCH) Micro2-XDP

OBSFN_D0

SCL

OBSDATA_D2

OBSDATA_A1

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

TCK1

SDA

HOOK1

HOOK3

OBSDATA_B1

OBSDATA_B0

OBSFN_B0

OBSDATA_A2

OBSDATA_A3

OBSFN_B1

OBSDATA_A0

TDI

TMS

ITPCLK/HOOK4

XDP_PRESENT#

DBR#/HOOK7

OBSDATA_D3

ITPCLK#/HOOK5

OBSFN_D1

OBSDATA_D0

OBSDATA_C2

OBSDATA_C3

OBSDATA_C1

OBSFN_C1

OBSDATA_C0

OBSFN_C0

support chipset debug.

Extra BPM Testpoints

VCC_OBS_CD

OBSFN_A1

OBSFN_A0

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

6

13 15 18

6 65

6 62 65

6 65

6 65

6 65

6 65

13 35

13 17 35

12 16 62 67

17 65

6

12 16 62 67

12 16 62 67

21R18055% 2011/20W MFPLACE_NEAR=U0500.AG7:2.54mm

1KXDP

12R18135% 2011/20W MFPLACE_NEAR=U0500.E60:28mm

51XDP

21R18045%

0XDP

402MF-LF1/16W

21R18025%

002011/20W MFPLACE_NEAR=U5000.J3:2.54mm

XDP

21R18005% 2011/20W MFPLACE_NEAR=U0500.C61:2.54mm

XDP1K

6 65 9

8 7

64 63

62 61

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1800

XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

M-ST-SM1

6 65

6 65

6 65

6 65

6 65

6 65

6 65

6 65

6 65

6 65

1TP1806

TP-P61

TP1807TP-P6

1TP1805

TP-P6

1TP1804

TP-P6

1TP1803

TP-P6

1TP1802

TP-P6

8

2

1R1830

5%1/16WMF-LF402

150

21R18105% 2011/20W MFPLACE_NEAR=U0500.F62:28mm

XDP51

12 16 62 67

2

1R1831

5%

XDP

MF-LF402

1/16W

1K

12R18965% 2011/20W MF

NO STUFF

PLACE_NEAR=U0500.AE62:28mm

51

12R18925% 2011/20W MFPLACE_NEAR=U0500.AD62:28mm

XDP51

12R18915% 2011/20W MFPLACE_NEAR=U0500.AD61:28mm

XDP51

12R18905% 2011/20W MFPLACE_NEAR=U0500.AE61:28mm

51XDP

12R18995% 2011/20W MF

NO STUFF

PLACE_NEAR=U0500.AE63:28mm

1K

21R18355%

002011/20W MF

PLACE_NEAR=J1800.58:28mm

XDP

12 16

6 12 16 62 65

6 62 65

6 62 65

6 16 62 65

2

1 C1801XDP

6.3VCERM-X5R0201

0.1UF10%

15 16 63

14

14 16 59 63

6 65

14 16 59 63

1TP1870

TP-P6

14 16 33 14 16 33

15 18

14

1TP1874

TP-P6

2

1C1800XDP

6.3VCERM-X5R

0201

0.1UF10%

1TP1876

TP-P6

15 18

1TP1877

TP-P6

15 18

1TP1878

TP-P6

15 18

15

15 16 18 25 15 16 18 25

12

12

12

6 62 65

21R18845% 2011/20W MF

1K

15 16 62

6 62 65

15

15 16 18 25 15 16 18 25

15 16 62

1TP1887

TP-P6

2

1C1804XDP

6.3VCERM-X5R

0201

0.1UF10%

2

1 C1806XDP

6.3VCERM-X5R0201

0.1UF10%

6 65

6 12 16 62 65

12R18975% 2011/20W MF

51NO STUFF

PLACE_NEAR=U0500.AU62:28mm

4

6

51

3

2

U1845

SOT89174LVC1G07GF

2

1C1845

X5R-CERM0201

16V

0.1UF10%

6 65

2

1R1845

5%

201

1/20WMF

330K

17 35 57

1TP1873

TP-P6

15 16 63

1TP1886

TP-P6

6 65

45

3

Q1842


DMN5L06VK-7

CRITICAL

XDP

SOT563

12

6

Q1842

SOT563DMN5L06VK-7

CRITICAL

XDP

12

6

Q1840DMN5L06VK-7

XDPCRITICAL

SOT563

45

3

Q1840

PLACE_NEAR=J1800.51:28MM

SOT563DMN5L06VK-7

XDPCRITICAL

12 15 1TP1879

TP-P61

TP1880TP-P61

TP1881TP-P6

6 65

14 19 38 54 67

14 19 38 54 67

6 16 62 65

6

8 17

6

6 65

6 65

SYNC_DATE=12/17/2012

CPU/PCH Merged XDP

SYNC_MASTER=WILL_J43

XDP_CPUPCH_TRST_LMAKE_BASE=TRUE

MAKE_BASE=TRUEXDP_USB_EXTA_OC_L

MAKE_BASE=TRUEXDP_USB_EXTB_OC_L

XDP_SDCONN_STATE_CHANGE_LMAKE_BASE=TRUE

MAKE_BASE=TRUEXDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDIMAKE_BASE=TRUE

XDP_LPCPLUS_GPIOMAKE_BASE=TRUE

XDP_CPU_TDI

XDP_PCH_TDI

XDP_CPU_TMS

XDP_PCH_TMS

XDP_LPCPLUS_GPIO

XDP_JTAG_ISP_TDI

ALL_SYS_PWRGD

PP5V_S0

XDP_PCH_TMS

XDP_CPUPCH_TRST_L

CPU_CFG<1>

XDP_CPU_TCK

XDP_BPM_L<6>

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

PP1V05_SUS

PCH_JTAGX

XDP_PCH_TDI

XDP_CPU_TDO

XDP_PCH_TDO

PP1V05_S0

CPU_CFG<0>

CPU_CFG<2>

XDP_BPM_L<1>

CPU_CFG<4>

CPU_CFG<5>

SMBUS_PCH_CLK

XDP_PCH_TCK

CPU_VCCST_PWRGD

PM_PWRBTN_L

PM_PCH_SYS_PWROK

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<12>

CPU_CFG<14>

CPU_CFG<15>

PLT_RESET_L

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TRST_L

CPU_CFG<10>

CPU_CFG<11>

XDP_PCH_TCK

XDP_CPU_TCK

XDP_USB_EXTB_OC_L

XDP_MLB_RAMCFG0

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

XDP_MLB_RAMCFG1

XDP_PCH_GPIO76

SMBUS_PCH_DATA

XDP_SSD_PCIE0_SEL_L

XDP_PCH_GPIO17

XDP_MLB_RAMCFG2

CPU_CFG<13>

CPU_CFG<18>

CPU_CFG<19>

CPU_CFG<16>

CPU_CFG<17>XDP_CPU_PREQ_L

XDP_SYS_PWROK

PP3V3_S5

PCH_JTAGX

XDP_MLB_RAMCFG3


XDP_USB_EXTA_OC_L

XDP_JTAG_ISP_TCK

XDP_DBRESET_L

XDP_CPURST_L

XDP_CPU_VCCST_PWRGD

XDP_CPU_PRDY_L

CPU_CFG<3>

XDP_BPM_L<0>

XDP_CPU_PWRBTN_L

PP1V05_S0

CPU_PWR_DEBUG

CPU_CFG<7>

CPU_CFG<6>

XDP_CPU_PRESENT_L

XDP_TRST_L

XDP_PCH_TDO

XDP_JTAG_CPU_ISOL_L

XDP_CPU_TDO

XDP_FW_PME_L

XDP_PCH_GPIO35

XDP_PCH_UART_SSD_L_BT_H

18 OF 120

<E4LABEL>

<SCH_NUM>

<BRANCH>

16 OF 73

6 12 16 62 65

17 32 43 49 50 54 56 57 59 60 62

12 16 62 67

6 12 16 62 65

6 16 62 65

55 60

12 16

12 16 62 67

6 16 62 65

12 16 62 67

6 8 11 15 16 17 36 40 49 53 56 57 60 62

12 16 62 67

62

8 11 13 15 17 18 28 29 40 52 55 56 57 58 60 62 72

65

62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

w w w

. c h

i n a

f i x

. c o

mOUT

OUT

NCNC

OUTIN

BIIN

OUT

IN

OUT

NC

NCNC

OUT

IN

IN

NC

OUT

IN

NC

A Y

NC NC

VCC

GND

NC

IN

OUT

IN

IN

Y

A

B 08 Y

A

B 08

OUT

OUT

OUT

IN

OUT

IN

YA

B

NCGND

VCC

32.768K

GND THRM

VOUT

X2

X1

25M_A

25M_B

25M_C

VIOE_25M_A

VIOE_25M_B

VIOE_25M_C

VG3HOT

NC

VDD

PAD

NCNC

VER 3

D SG

VER 3

D

SG

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Must be powered if any VDDIO is powered.

available ~3.3V power

WF: Do we need this?

TPS51916 I(leak) = +/- 1uA,

Vih(min) = 1.8V

33uW when driven-low

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

Memory VTT Enable Level-Shifter

SMC controls strap enable to allow in-field control of strap setting.

VCCST (1.05V S0) PWRGD

IPD = 9-50k

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

PCH Reset Button

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

CAM XTAL Power

PCH PWROK Generation

PCH 24MHz Outputs

No bypass necessary

No Coin-Cell: 3.3V S5

Coin-Cell & No G3Hot: 3.3V S5

TBT XTAL Power

GreenCLK 25MHz Power

PCH 24MHz Crystal

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell: VBAT (300-ohm & 10uF RC)

System RTC Power Source & 32kHz / 25MHz Clock GeneratorChipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

VBAT and +V3.3A are

internally ORed to

create VDD_RTC_OUT.

+V3.3A should be first

to reduce VBAT draw.

For SB RTC Power

PCH ME Disable Strap

NOTE: 30 PPM or better required for RTC accuracy

pin 5 must receive S5 power (Stuff R2042)

new and old parts. With GreenCLK Rev C

This looks a little ugly to support

12

25 67

2

1 C1902

X5R

1UF

0201

20%6.3V

2

1 C1910

0201

6.3V20%1UF

X5R

31

42 Y1905

SM-3.2X2.5MM

CRITICAL

25.000MHZ-12PF-20PPM

2 1

C190512PF

25VNP0-C0G-CERM

0201

5%

21

C1906

25VNP0-C0G-CERM

0201

12PF

5%

17 35 67 21

R1927

PLACE_NEAR=U0500.AN15:5.1mm

22

MF1/20W

201

5%

12 67

13 35 62 16 65

2

1C1924

0201X5R-CERM

16V10%

0.1UF

21

R1905

MF1/20W

0201

0

5%

2

1R1906

NO STUFF

1M

MF1/20W

201

5%

21

R1996

XDP

MF

1/20W0201

0

5%

2

1R1997

402

1/16WMF-LF

SILK_PART=SYS RESET

NO STUFF

05%

2

1R199510K

MF1/20W

201

5%

2

1R1920100K

MF1/20W

201

5%

2

1R19211K

MF1/20W

201

5%

12 67

35

2

1C19220.1UF

10%16V

0201X5R-CERM

32 67

2

1R19161M

MF1/20W

201

5%

21

R1915

MF1/20W

0201

0

5%

21

C1915

C0G

6.8PF

0201

+/-0.1PF25V

21

C19166.8PF

0201C0G25V

+/-0.1PF

12

12

12 17

8 16

2

1R193110K

MF1/20W

201

5%

2

1C1930

0201

16VX5R-CERM

10%0.1UF

13 18 35 57

2

1R1970330K

MF1/20W

201

5%

4

6

51

3

2

U1970

SOT89174AUP1G07GF

2

1C19700.1UF

10%16V

0201X5R-CERM

6

17 51

26 27 35 36

16 17 35 57

7

8

4

2

1

U1950

74LVC2G08GTSOT833

2

1 C1950

X5R-CERM

10%

0201

16V

0.1UF

BYPASS=U1950:5MM

3

8

4

6

5

U1950

CKPLUS_WAIVE=UNCONNECTED_PINS

SOT83374LVC2G08GT


1

2R1963

MF1/20W

0201

05%

1

2R1960NO STUFF

MF1/20W

0201

05%

21

R19621K

MF1/20W

201

5%

13 16 35

13 17

13 17

21

R1951

NO STUFF

MF1/20W

0201

0

5%

2

1R195010K

MF1/20W

201

5%

2

1R195510K

MF1/20W

201

5%

8 49

8 17 49

8 17 49

2

1R1961NO STUFF

100K

MF1/20W

201

5%

4

6

5

3

1

2

U193074AUP1G09SOT891

CRITICAL

3

4

1

14

6

11

13

5

17

2

16

10

7

12

15

8

9

U1900SLG3NB148CV

CRITICALTQFN

CKPLUS_WAIVE=PwrTerm2Gnd

31

42

Y1915CRITICAL

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

45

3

Q1920DMN5L06VK-7

SOT563

12

6Q1920

SOT563

DMN5L06VK-7

Chipset Support

SYNC_DATE=01/09/2013SYNC_MASTER=J43_MLB1

LPC_CLK24M_SMCMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_RTC_CLK32K_RTCX2

MEMVTT_PWR_ENMAKE_BASE=TRUE

MAKE_BASE=TRUECPU_VR_READY

PM_PCH_PWROKMAKE_BASE=TRUE

SPI_DESCRIPTOR_OVERRIDE_L

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE


PP3V3_S5

PP3V3_S5RS3RS0_SYSCLKGEN

NC_RTC_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PP3V3_TBTLC

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

SYSCLK_CLK25M_X1

PCH_CLK24M_XTALOUT_R

PCH_CLK24M_XTALIN

PM_SLP_S3_L

ALL_SYS_PWRGD

PP3V3_S5

CPU_VCCST_PWRGD

PP1V05_S0

SMC_DELAYED_PWRGD

ALL_SYS_PWRGD

CPU_VR_EN

CPU_VR_READY

PP3V42_G3H

XDP_DBRESET_L PM_SYSRST_L

PP3V3_S0

HDA_SDOUT_R

PCH_CLK24M_XTALOUT

LPC_CLK24M_SMC_R

SYS_PWROK_R

PP5V_S0

CPU_MEMVTT_PWR_EN_LSVDDQ

PP1V2_S3

PP3V3_S0

MEMVTT_PWR_EN

PM_PCH_SYS_PWROK

PM_S0_PGOOD

PM_PCH_PWROK

CPUVR_PGOOD_R

PP3V3_S0

SYSCLK_CLK25M_X2

LPC_CLK24M_SMC

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_CAMERA

SYSCLK_CLK25M_TBT

<BRANCH>

<SCH_NUM>

<E4LABEL>

19 OF 120

17 OF 73

17 35 67

12 17

17 51

8 11 56

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

18

18 25 26 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

31

67

16 17 35 57

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72 6 8 11 15 16 36 40 49 53 56 57

60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

16 32 43 49 50 54 56 57 59 60 62

19 20 21 22 23 40 51 60 68

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

67

8 12 13 60 62

67

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

BI

BI

OUT

BI

BI

BI

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT IN

OUT

OUTIN

IN

BI

NC

08

NC

OUT

IN

IN

OUT

OUT

IN

IN

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

OUT

OUT

VCC

1A 1Y

2A 2Y

GND

IN

IN

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



MAKE_BASE

No MAKE_BASE on TCK/TDI as these are provided on XDP page.

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC (on TBT page)

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

Falcon Ridge PLUG_EVENT is active-low, always driven (pull-up)

NOTE: Only DDC_DATA is sensed by PCH, so

Unbuffered to indicate active display interface.

DDC_CLK pull-ups are unstuffed.

LPDDR3 Alias Support

DDC Pull-UpsGreenCLK 25MHz Power

R2041/2 should be stuffed for

DP++ spec violation, should remove!

TBTSNK1_DDC is pulled-up just to indicate that

DP port is used. No DDC on this port, AUX-only.

2.2k pull-ups are required by PCH

Required for unused second TBT port

R2042 should be stuffed for GreenCLK C

GreekCLK A or B depending on S2 rail

Buffered

TBT AliasesMAKE_BASE

Scrub for Layout Optimization

Platform Reset Connections

Pull-downs for chip-down RAM systems

RAM Configuration Straps

Single-port TBT implementation does not require DDC Crossbar

MAKE_BASE

Thunderbolt Pull-up/downs

(For development only)

Power State Debug LEDs

To RR

To PCH

S0 pull-up on PCH page

Redwood Ridge JTAG IsolationTBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

S0 pull-up on PCH page

From PCH

From RR

and TDI as well for PCH glitch-prevention.

different isolation techniques will likely be necessary.

Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK

Pin N61 needs a TP for Power to perform iFDIM test

Renaming the pins N61 and P61 to remove automatic diffpari property

2

1R2022

5%

201

1/20WMF

NO STUFF

2.2K

2

1R2023

5%

201

1/20WMF

2.2K

2

1R2020NO STUFF

2.2K

MF1/20W

201

5%

2

1R20212.2K

MF1/20W

201

5%

2

1R2050

5%

201

1/20WMF

RAMCFG3:L

10K

2

1R2051

5%

201

1/20WMF

RAMCFG2:L

10K

2

1R2052

5%

201

1/20WMF

RAMCFG1:L

10K

2

1R2053

5%

201

1/20WMF

RAMCFG0:L

10K

2

1R2016

5%

201

1/20WMF

10K

2

1R2017

5%

201

1/20WMF

10K

2

1R2018

5%

201

1/20WMF

10K

2

1R2019

5%

201

1/20WMF

10K

2

1R2014

5%

201

1/20WMF

10K

K

A

D2090GREEN-56MCD-2MA-2.65VLTQH9G-SM

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S5_ONK

A

D2091

LTQH9G-SMGREEN-56MCD-2MA-2.65V

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=STBY_ON

2

1R2090

5%

201

1/20WMF

DBGLED

20K

2 1

R2094

5%

0

402MF-LF1/16W

PLACE_SIDE=BOTTOM

DBGLED

2

1R2091

5%

201

1/20WMF

DBGLED

20K

K

A

D2092

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65VLTQH9G-SM

2

1R2092

5%

201

1/20WMF

DBGLED

20K

K

A


PLACE_SIDE=BOTTOMSILK_PART=S0I3_ON

DBGLED

2

1R2093

5%

201

1/20WMF

DBGLED

20K

15 16

15 16

15 16

15 16

25

25

25

25

6 18

15 18

28 56 57

13 18 29 34 35 57

13 17 35 57

2

1R2095

5%

201

1/20WMF

20K

DBGLED

K

A


PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S0_ON

13 35

13 18 25

5 25 65

5 25 65

13 18 28

13 18 25 65

13 18 25 65

13 18 28

13 18

13 18 25 65

13 18 25 65

13 18 25

13 18

2

1 C2071

10%16V

0.1UF

X5R-CERM0201

5

4

1

2

3

U2071

SC70-HF

CRITICAL

MC74VHC1G08

2

1R2070

5%

201

1/20WMF

100K21

R2088

5%

0

0201

1/20WMF

21

R2072

5%

0

0201

1/20WMF

13 15 16

21

R2071

5%

0

0201

1/20WMF

54

35

19

15 18 25 15 18 25

21

R2089

5%

0

0201

1/20WMF

NOSTUFF

15 31

15 18 25 15 18 25

21

R2040

5%

0

0201

1/20WMF

NO STUFF

21

R2041

5%

0

0201

1/20WMF

NO STUFF

13 18 28

13 18 28

4

6

5 3

1

2

U2030

CRITICAL

74LVC1G08SOT891

NOSTUFF

2

1C2030

NOSTUFF

0.1UF

BYPASS=U2030:3mm

0201X5R-CERM

10%10V

21

R2030

5%

0

0201

1/20WMF

31

15

13 18 29 34 35 57

21

R2042

5%

0

0201

1/20WMF

15 16 18 25

15 16 18 25

15 16 18 25

15 16 18 25

12

6Q2090DBGLED

DMN5L06VK-7SOT563

45

3Q2090DBGLED

DMN5L06VK-7SOT563

12

6Q2091

SOT563

DMN5L06VK-7

DBGLED

45

3Q2091

SOT563

DMN5L06VK-7

DBGLED

2

1R2015100K

MF1/20W

201

5%

15

25

2

1R2062100K

1/20W

201

5%

MF

52

43

61

U2060

SOT89174LVC2G07

2

1 C2060

10V20%

402CERM

0.1UF

2

1R2061

1/20W

100K5%

201MF

25

15

2

1R2010100K

1/20W

201

5%

MF

14 37

SYNC_MASTER=J43_MLB

Project Chipset Support


PCH_SML1ALERT_L

PP3V3_SUS

TP_CPU_RSVDN61MAKE_BASE=TRUE

TP_CPU_RSVDN61

MAKE_BASE=TRUETP_CPU_RSVDP61TP_CPU_RSVDP61

JTAG_TBT_TMS_PCH

PP3V3_TBTLC

JTAG_TBT_TDO JTAG_ISP_TDO

JTAG_TBT_TMS

PM_SLP_S4_L

CAMERA_PWR_EN_PCH

CAMERA_PWR_EN

PP3V3_S5

PM_SLP_S0_L

DBGLED_S0_D

PM_SLP_S3_L

DBGLED_S0I3_D

PM_SLP_S4_L

DBGLED_S3_D

S4_PWR_EN

DBGLED_S4_D

PP3V3_S5

TRUE DP_TBTSNK1_HPD

DP_TBTSNK1_ML_C_P<3..0>TRUE=DP_TBTSNK1_ML_C_P<3..0>

=DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_DATA

PP3V3_S5_DBGLEDMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=3.3V

PP3V3_S0


VOLTAGE=3.3VMAKE_BASE=TRUE



BKLT_PLT_RST_L

TRUE DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_HPD


DP_TBTSNK1_AUXCH_C_NTRUE


CAM_PCIE_RESET_L

SMC_LRESET_L

PCH_TBT_PCIE_RESET_LMAKE_BASE=TRUE

PLT_RST_BUF_L

PP3V3_S0

PLT_RESET_L

PCA9557D_RESET_L

DP_TBTSNK0_DDC_DATA

PP3V3_S3

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK

PP3V3_S0


XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG1



DP_TBTSNK0_DDC_DATA TRUE

DP_TBTSNK1_DDC_DATATRUE

DP_TBTSNK1_DDC_CLKTRUE

DP_TBTSNK1_AUXCH_C_PTRUE

DP_TBTSNK0_DDC_CLK

TBT_B_CONFIG1_BUF

TBT_B_CONFIG2_RC

DP_TBTPB_HPD

TBT_B_CIO_SEL

PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFCA_BVOLTAGE=0.6VMAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_B PP0V6_S3_MEM_VREFDQ_BVOLTAGE=0.6VMAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

TP_CPU_MEM_RESET_L

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_AVOLTAGE=0.6VMAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_AVOLTAGE=0.6VMAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_AMAKE_BASE=TRUETP_MEM_VDD_SEL_1V5_L

MAKE_BASE=TRUETP_CPU_MEM_RESET_L

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

DP_TBTSNK1_DDC_CLK

DBGLED_S0DBGLED_S0I3DBGLED_S5

DP_TBTSNK0_DDC_CLK TRUE

DP_TBTSNK1_DDC_CLK

XDP_JTAG_ISP_TCKXDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDI

PP3V3_S5

DBGLED_S3DBGLED_S4

TBT_CIO_PLUG_EVENT_LTRUE

PP3V3_S0

TBT_B_LSRX

<BRANCH>

<SCH_NUM>

<E4LABEL>

20 OF 120

18 OF 73

8 11 14 44 55 56 57 60 62

8 18 8 18

8 18 8 18

17 25 26 60 62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

17 18

8 11 12 13 15 17 18 26 30 34

36 37 38 39 40

41 42 43 54 57

59 60 62 63 72

13 18 28

15 19 34 38 39 56 60 62 63

13 18

13 18 28

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

17 18

13 18

13 18

18 19 22 23 68 18 19 22 23 68

18 19 22 23 68 18 19 22 23 68

18 19 20 21 68 18 19 20 21 68

18 19 20 21 68 18 19 20 21 68

15 18

6 18

13 18

8 11 13 15 16 17

18 28 29

40 52 55

56 57 58

60 62 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

25

w w w

. c h

i n a

f i x

. c o

m

OUT

V-

V+

V-

V+

IN

IN

IN

IN

VER 3

DSG

VER 3

DSG

VER 3

DSG

VER 3

DSG

VER 3

DSG

VER 3

DSG

VER 3

DSG

VER 3

DSG

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GNDPAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI

Apple Inc.


124578

B

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8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



6.36mV / step @ output

0.337V - 1.013V (+/- 337.5mV)

MEM B VREF DQ

NOTE: CPU has single output for

signals for independent DAC

DAC-Based Margining


LPDDR3 (1.2V)

DAC margining VREFCA ensure

LPDDR3 (1.2V) ?.??mV per step

May not be necessary due to C22x0

EN RC’s to avoid drain glitches

- DDRVREF_DAC - Stuffs DAC margining circuit.

BOM options provided by this page:

0.000V - 1.354V (0x00 - 0x69) 0.000V - 2.694V (0x00 - 0xD1)

- =I2C_VREFDACS_SDA

- =PPDDR_S3_MEMVREF

- =PP3V3_S3_VREFMRGN

DAC step size:

VRef current:

Nominal value

DAC range:

- =I2C_VREFDACS_SCL

VREFCA. Split into two

VREFMRGN_CPU_EN is low

DDR3L (1.35V) 6.99mV per step

Q2225 pin 6:

(OD)

both at the same time!

Pins B1 & B4:

Page NotesPower aliases required by this page:

Signal aliases required by this page:

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

margining support. When

CPU-Based Margining

0.000V - 1.199V (0x00 - 0x5D)

0.300V - 0.900V (+/- 300mV)Margined target:

0.675V (DAC: 0x34) 0.600V (DAC: 0x2E.5)

+73uA - -73uA (- = sourced)

(All 4 R’s)

NOTE: MEMVREG and SPARE share a

DAC output, cannot enable



4

C

DDR3L (1.35V)

MEM B VREF CA

3

C

MEM A VREF CA

2

BA

1

MEM A VREF DQ

PCA9557D Pin:

DAC Channel:

LPDDR3 (1.2V)

MEM VREG

D

5

1.200V (DAC: 0x5D)

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

DDR3L assumes TPS51916 supply with 19.6k/57.6k dividerDDR3L (1.35V)

0.972V - 1.714V (+/- 371mV)

1.343V (DAC: 0x68)



RST* on ’platform reset’ so that system

watchdog will disable margining.

soft-resets and sleep/wake cycles.

Addr=0x30(WR)/0x31(RD)

DAC sets voltage level, PCA9557 & FETs enable outputs

and disables margining after platform reset.

to remove short due to CPU.

Q2265 pin 6:

R22x6 pin 2:

FETs for CPU isolation during DAC margining

DDR3 (1.5V) 7.70mV per step

NOTE: CPU DAC output step sizes:

Addr=0x98(WR)/0x99(RD)

Always used, regardless

NOTE: Margining will be disabled across all

0.800V - 1.600V (+/- 400mV)

0.000V - 2.397V (0x00 - 0xBA)


of margining option.

VRef Dividers

51 2

1C2202

10%6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

21

R2214

201

PLACE_NEAR=R7415.2:1mm1%

DDRVREF_DAC

1/20WMF

38.3K

2

1R2213

201

5%100K

1/20WMF

DDRVREF_DAC

2

1R2212

201

5%100K

1/20WMF

DDRVREF_DAC

B4

B1

A4

A1

A2

A3

U2204

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

MAX4253UCSP

CRITICAL

DDRVREF_DAC

B4

B1

C4

C1

C2

C3

U2204UCSP

DDRVREF_DAC

MAX4253

CRITICAL

21

R2218SHORT

NONENONE

NONE

OMIT

402

18

7

7

2

1R2202

201

1/20W5%

MF

DDRVREF_DAC

100K

7

2

1R2201

201

100K

DDRVREF_DAC

5%1/20W

MF

21

R2225

201

1/20W5%

MF

DDRVREF_DAC

100K

2

1C2225

10%6.3V

DDRVREF_DAC

0.1UF

0201CERM-X5R

2

1C2245

10%6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

21

R2245

201MF

1/20W

DDRVREF_DAC

5%

100K

21

R2265

201MF

1/20W5%

DDRVREF_DAC

100K

2

1C2265

10%6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

2

1C2285

10%6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

2

1R2215

201

100K5%

1/20WMF

DDRVREF_DAC

21

R2285

201

DDRVREF_DAC

MF1/20W5%

100K

2

1R2207

201

DDRVREF_DAC

100K5%

1/20WMF

21R22262011% 1/20W MF

4.02KDDRVREF_DAC

PLACE_NEAR=Q2225.1:2.54mm21R2246

2011% 1/20W MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2265.1:2.54mm

21R22662011% 1/20W MF

4.02K

DDRVREF_DAC


21R22862011% 1/20W MF

4.02K

DDRVREF_DAC


2

1R2217

201MF1/20W5%

DDRVREF_DAC

1M

2

1R2200

201

100K5%

1/20WMF

2

1R2221

201PLACE_NEAR=Q2220.6:3mm

MF

1%8.2K

1/20W

21

R2280

201MF

1/20W1%

24.9

2

1 C2280

10%0.022UF

0201X5R-CERM6.3V

PLACE_NEAR=Q2260.3:2mm

21

R2283

201MF

1/20W

10

1%

2

1R2281


1%8.2K

1/20WMF

2

1R2282

201

1%8.2K

1/20WMF

PLACE_NEAR=R2281.2:1mm

2

1R2262

201


1%8.2K

1/20WMF

21

R2260

201MF

1/20W1%

24.9

21

R2263

201MF

1/20W

10

1%

2

1 C2260

10%0.022UF

0201X5R-CERM6.3V


2

1R2261


1%8.2K

1/20WMF

2

1R2242

201


1%8.2K

1/20WMF

21

R2240

201MF

1/20W1%

24.9

21

R2243

201

10

MF1/20W1%

2

1 C2240

6.3VX5R-CERM0201

0.022UF10%


2

1R2241

201

8.2K


1%1/20WMF

21

R2223

201

1/20WMF

10

1%

2

1R2222

201


1%8.2K

MF1/20W

21

R2220

201MF

1/20W1%

24.9

2

1 C2220

10%0.022UF

0201X5R-CERM6.3V


45

3

Q2220

SOT563

CRITICAL

DMN5L06VK-7

12

6

Q2220

SOT563

CRITICAL

DMN5L06VK-7

12

6

Q2260DMN5L06VK-7

CRITICAL

SOT563

45

3

Q2260DMN5L06VK-7

CRITICAL

SOT563

12

6

Q2265CRITICAL

DDRVREF_DAC

SOT563DMN5L06VK-7


12

6

Q2225


CRITICALDDRVREF_DAC

SOT563DMN5L06VK-7

45

3

Q2225DMN5L06VK-7

DDRVREF_DACCRITICAL

SOT563

45

3

Q2265

SOT563

CRITICALDDRVREF_DAC

DMN5L06VK-7

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2201

DDRVREF_DAC

CRITICAL

QFN

PCA9557

14 16 19 38 54 67

14 16 19 38 54 67

5

4

2

1

8

7

6

3

10

9

U2200MSOP

DDRVREF_DAC

CRITICAL

DAC5574

14 16 19 38 54 67

14 16 19 38 54 67

2

1 C2201

10%6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

2

1C2200

6.3V20%

CERM

2.2UF

DDRVREF_DAC

402-LF

2

1C2205

10%6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC


DDR3 VREF MARGINING


VREFMRGN_CA_B_RDIV

VREFMRGN_CA_B_EN_RC

CPU_MEM_VREFCA_B_ISOL

CPU_MEM_VREFCA_A_ISOL

VREFMRGN_CA_A_EN_RC

VREFMRGN_CA_A_RDIV

VREFMRGN_DQ_A_RDIV

VREFMRGN_DQ_A_EN_RC

CPU_MEM_VREFDQ_A_ISOL

VREFMRGN_DQ_B_RDIV

VREFMRGN_DQ_B_EN_RC

CPU_MEM_VREFDQ_B_ISOL

CPU_DIMMA_VREFDQ

VREFMRGN_CPU_EN

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

VREFMRGN_SPARE_EN

VREFMRGN_CA_B_EN

VREFMRGN_CA_A_EN

PP3V3_S3_VREFMRGN_DACMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

VREFMRGN_MEMVREG_EN

VREFMRGN_DQ_B_EN

VREFMRGN_DQ_A_EN

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PCA9557D_RESET_L

MEM_VREFDQ_A_RC

PP0V6_S3_MEM_VREFDQ_B


VREFMRGN_MEMVREG

VREFMRGN_DQ_B

PP0V6_S3_MEM_VREFCA_BMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

PP1V2_S3

PP0V6_S3_MEM_VREFCA_AMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

VREFMRGN_CA_AB

VREFMRGN_DQ_A

MEM_VREFCA_B_RC

DDRREG_FB

SMBUS_PCH_DATA

SMBUS_PCH_CLK

MEM_VREFDQ_B_RC

MEM_VREFCA_A_RC

VREFMRGN_MEMVREG_BUF

VREFMRGN_SPARE_BUF

PP3V3_S3

PP3V3_S3

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP0V6_S3_MEM_VREFDQ_A

<BRANCH>

<E4LABEL>

19 OF 73

22 OF 120

<SCH_NUM>

18 22 23 68

18 22 23 68

17 20 21 22 23 40 51 60 68

18 20 21 68

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

18 20 21 68

w w w

. c h

i n a

f i x

. c o

mBI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNCNC

NCNCNCNCNCNCNCNCNCNCNCNC

IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

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A


PAGE

12

D

A

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



10uF caps are shared between DRAM.

PLACEMENT_NOTE:

LPDDR3 CHANNEL A (0-31)

Distribute evenly.

61

61

2

1 C230610UF20%25VX5R-CERM0603

2

1 C2307

25V

0603

10UF20%

X5R-CERM2

1 C2302

402

10VX5R

1UF10%

61

2

1 C2300

10%0.1UF

X5R-CERM16V

0201

2

1 C2303

402

10VX5R

1UF10%

2

1 C2304

10VX5R402

1UF10%

2

1 C2301

10%0.1UF

0201X5R-CERM16V

2

1 C2305

10VX5R402

1UF10%

61

2

1 C2310

10VX5R402

1UF10%

2

1 C2311

10VX5R402

1UF10%

2

1 C2312

25V

0603

10UF20%

X5R-CERM

2

1 C2320

10%1UF

402X5R10V

2

1 C2321

10%1UF

402X5R10V

2

1 C2322

10%1UF

402X5R10V

61

2

1 C2324

X5R-CERM

20%10UF

0603

25V2

1 C2323

X5R-CERM

20%10UF

0603

25V

2

1 C233310UF20%

0603

25VX5R-CERM2

1 C2332

25V

0603

10UF20%

X5R-CERM2

1 C2331

10%1UF

402X5R10V

2

1 C2330

10%1UF

X5R10V

402

61

2

1 C23410.047UF

201

10%

X5R6.3V

2

1C2340

201

0.047UF

X5R6.3V10%

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

7 24 61 68

24 61 68

61

24 61 68

24 61 68

7 24 68

7 24 68

7 24 68

7 24 68

7 21 24 68

7 21 24 68

7 21 24 61 68

61

2

1R2300

201MF

1/20W1%

243

2

1R2301

1%243

1/20WMF

201

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2300

FBGALPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2300

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

61



PP1V2_S3

PP1V2_S3

MEM_A_CAA<1>

MEM_A_CAA<3>

MEM_A_CKE<0>

PP1V8_S3

MEM_A_ODT<0>

MEM_A_CS_L<1>

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>

=MEM_A_DQ<5>

=MEM_A_DQ<6>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<12>

=MEM_A_DQ<21>

=MEM_A_DQ<26>

=MEM_A_DQ<28>

=MEM_A_DQ<27>

=MEM_A_DQ<29>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<3>

=MEM_A_DQ<19>

=MEM_A_DQS_N<1>

=MEM_A_DQ<3>

PP1V2_S3

=MEM_A_DQS_P<0>

=MEM_A_DQ<25>

PP1V2_S3

=MEM_A_DQ<17>

=MEM_A_DQ<24>

MEM_A_CAA<0>

MEM_A_CAA<2>

=MEM_A_DQ<20>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

PP1V2_S3

=MEM_A_DQ<4>

MEM_A_CAA<6>

MEM_A_CAA<9>

PP1V8_S3

MEM_A_CAA<4>

MEM_A_CAA<8>

MEM_A_CKE<1>

MEM_A_CLK_P<0>

MEM_A_CAA<7>

MEM_A_CAA<5>

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_ZQ<1>

PP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_A

MEM_A_ZQ<0>

PP1V2_S3

23 OF 120

<SCH_NUM>

<E4LABEL>

<BRANCH>

20 OF 73

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

18 19 21 68

18 19 21 68

17 19 20 21 22 23 40 51 60 68

w w w

. c h

i n a

f i x

. c o

mBI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNCNC


IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Distribute evenly.

PLACEMENT_NOTE:


LPDDR3 CHANNEL A (32-63)

61

2

1 C2423

25V

0603

10UF20%

X5R-CERM

2

1 C2403

10%1UF

402X5R10V

2

1 C2404

10%1UF

402X5R10V

2

1 C2405

10%1UF

402X5R10V

2

1 C2406

0603X5R-CERM25V20%10UF

61

7 20 24 61 68

2

1R2400243

1%1/20W

MF201

2

1R2401

201MF

1/20W

2431%

2

1C2440

6.3VX5R

0.047UF

201

10%

61

2

1 C2441

6.3VX5R

10%0.047UF

201

61

61

61

61

7 61 68

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

7 61 68

7 61 68

61

61

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

7 24 61 68

24 61 68

61

24 61 68

24 61 68

7 24 68

7 24 68

7 24 68

7 24 68

7 20 24 68

7 20 24 68

61

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2400

OMIT_TABLE

FBGA

EDFA232A1MA-GD-F

CRITICAL

LPDDR3-16GB

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2400

FBGA

EDFA232A1MA-GD-F

LPDDR3-16GB

CRITICAL

OMIT_TABLE

2

1 C2430

10VX5R402

1UF10%

2

1 C2431

10VX5R402

1UF10%

2

1 C2410

10%1UF

402X5R10V

2

1 C2411

10%1UF

402X5R10V

61

2

1 C2432

X5R-CERM

20%10UF

0603

25V

2

1 C241210UF

X5R-CERM

20%

0603

25V

2

1 C2420

10VX5R402

1UF10%

2

1 C2400

10%0.1UF

X5R-CERM16V

0201

2

1 C2421

10VX5R402

1UF10%

2

1 C24010.1UF

16VX5R-CERM

10%

0201

2

1 C2422

10VX5R402

1UF10%

2

1 C2402

10V10%1UF

402X5R

SYNC_DATE=MASTERSYNC_MASTER=MASTER


PP0V6_S3_MEM_VREFCA_A

PP0V6_S3_MEM_VREFDQ_A

MEM_A_ZQ<3>

MEM_A_ZQ<2>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CAB<5>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CAB<4>

PP1V2_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

PP1V2_S3

PP1V2_S3

MEM_A_CS_L<1>

=MEM_A_DQ<32>

=MEM_A_DQ<33>

=MEM_A_DQ<35>

=MEM_A_DQ<34>

=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQ<50>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_A_DQ<53>

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<58>

=MEM_A_DQ<60>

=MEM_A_DQ<59>

=MEM_A_DQ<61>

=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<4>

MEM_A_DQS_P<6>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<7>

MEM_A_CLK_N<1>

MEM_A_DQ<32>

MEM_A_CAB<6>

MEM_A_CAB<7>

MEM_A_CAB<8>

MEM_A_CAB<9>

MEM_A_CLK_P<1>

<BRANCH>

<E4LABEL>

<SCH_NUM>

21 OF 73

24 OF 120

18 19 20 68

18 19 20 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

w w w

. c h

i n a

f i x

. c o

mBI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNCNC


IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.


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6 3



LPDDR3 CHANNEL B (0-31)

Distribute evenly.


PLACEMENT_NOTE:

61

2

1 C2523

X5R-CERM

20%10UF

0603

25V

2

1 C2503

10VX5R402

1UF10%

2

1 C2504

10VX5R402

1UF10%

2

1 C2505

10VX5R402

1UF10%

2

1 C250610UF20%25VX5R-CERM0603

61

7 23 24 61 68

2

1R2500243

1%1/20W

MF201

2

1R2501

201MF

1/20W

2431%

2

1C2540

10%6.3VX5R

0.047UF

201

2

1 C2541

6.3VX5R

10%0.047UF

201

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

7 24 61 68

24 61 68

61

24 61 68

24 61 68

7 24 68

7 24 68

7 24 68

7 24 68

7 23 24 68

7 23 24 68

61

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2500

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

LPDDR3-16GBFBGA

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2500

OMIT_TABLE

CRITICAL

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

2

1 C2530

10%1UF

402X5R10V

2

1 C2531

10%1UF

402X5R10V

2

1 C2510

10VX5R402

1UF10%

2

1 C2511

10VX5R402

1UF10%

61

2

1 C2532

25V

0603

10UF20%

X5R-CERM

2

1 C2512

25V

0603

10UF20%

X5R-CERM

2

1 C2520

10%1UF

402X5R10V

2

1 C2500

0201

16VX5R-CERM

0.1UF10%

2

1 C2521

10%1UF

402X5R10V

2

1 C2501

0201

10%0.1UF

X5R-CERM16V

2

1 C2522

10%1UF

402X5R10V

2

1 C2502

10VX5R402

1UF10%



PP0V6_S3_MEM_VREFCA_B


MEM_B_ZQ<1>

MEM_B_ZQ<0>

MEM_B_ODT<0>

=MEM_B_DQS_P<3>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<1>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQ<29>

=MEM_B_DQ<27>

=MEM_B_DQ<28>

=MEM_B_DQ<26>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<20>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQ<17>

=MEM_B_DQ<16>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

=MEM_B_DQ<13>

=MEM_B_DQ<12>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<1>

=MEM_B_DQ<0>

MEM_B_CS_L<1>

PP1V2_S3

PP1V2_S3

PP1V2_S3

PP1V8_S3

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CAA<9>

MEM_B_CAA<8>

MEM_B_CAA<7>

MEM_B_CAA<6>

MEM_B_CAA<5>

MEM_B_CAA<4>

MEM_B_CAA<3>

MEM_B_CAA<2>

MEM_B_CAA<1>

MEM_B_CAA<0>

PP1V2_S3

PP1V2_S3

PP1V2_S3

PP1V8_S3

<SCH_NUM>

<E4LABEL>

<BRANCH>

25 OF 120

22 OF 73

18 19 23 68

18 19 23 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

w w w

. c h

i n a

f i x

. c o

mBI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNCNC


IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.


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BRANCH

6 3



LPDDR3 CHANNEL B (32-63)

PLACEMENT_NOTE:

Distribute evenly.


61

2

1 C2623

X5R-CERM

20%10UF

0603

25V

2

1 C2603

10VX5R402

1UF10%

2

1 C2604

10VX5R402

1UF10%

2

1 C2605

10VX5R402

1UF10%

2

1 C260610UF20%25VX5R-CERM0603

7 22 24 61 68

61

2

1R2600

201MF

1/20W1%

243

2

1R2601

1%243

1/20WMF

201

2

1C2640

201

0.047UF

X5R6.3V10%

2

1 C2641

201

0.047UF10%

X5R6.3V

61

61

61

7 61 68

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

7 61 68

61

61

61

7 61 68

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

24 61 68

7 24 61 68

24 61 68

61

24 61 68

24 61 68

7 24 68

7 24 68

7 24 68

7 24 68

7 22 24 68

7 22 24 68

61

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2600

FBGALPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2600

OMIT_TABLE

CRITICAL

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

2

1 C2630

10%1UF

402X5R10V

2

1 C2631

10%1UF

402X5R10V

2

1 C2610

10VX5R402

1UF10%

2

1 C2611

X5R10V

402

1UF10%

61

2

1 C2632

25V

0603

10UF20%

X5R-CERM

2

1 C2620

10%1UF

402X5R10V

2

1 C2600

0201

16VX5R-CERM

0.1UF10%

2

1 C2621

10%1UF

402X5R10V

2

1 C2601

0201

10%0.1UF

X5R-CERM16V

2

1 C2622

10%1UF

402X5R10V

2

1 C2602

10VX5R402

1UF10%




PP0V6_S3_MEM_VREFCA_B

MEM_B_ZQ<2>

MEM_B_ZQ<3>

MEM_B_DQS_P<6>

=MEM_B_DQS_P<5>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<4>

MEM_B_DQS_N<6>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<4>

=MEM_B_DQS_N<5>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=MEM_B_DQ<61>

=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<51>

=MEM_B_DQ<50>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<47>

=MEM_B_DQ<46>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

MEM_B_DQ<33>

=MEM_B_DQ<40>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

PP1V2_S3

PP1V2_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

MEM_B_CAB<0>

MEM_B_CAB<1>

MEM_B_CAB<2>

MEM_B_CAB<3>

MEM_B_CAB<4>

MEM_B_CAB<5>

MEM_B_CAB<6>

MEM_B_CAB<7>

MEM_B_CAB<8>

MEM_B_CAB<9>

MEM_B_CKE<2>

MEM_B_CKE<3>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CS_L<1>

PP1V2_S3

PP1V2_S3

PP1V8_S3

MEM_B_CS_L<0>

MEM_B_ODT<0>

23 OF 73

<BRANCH>

<E4LABEL>

<SCH_NUM>

26 OF 120

18 19 22 68

18 19 22 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

20 21 22 23 55 60

w w w

. c h

i n a

f i x

. c o

mIN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

NC NC NCNC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

SpareSpare

2

1 C27020.47UF

4V20%

CERM-X5R-1201

2

1 C2704

201

0.47UF

CERM-X5R-1

20%4V

2

1 C2700

201

4V20%0.47UF

CERM-X5R-1

2

1 C2701

CERM-X5R-1

0.47UF

201

4V20%

2

1 C2703

CERM-X5R-14V20%

201

0.47UF

2

1 C2706

201CERM-X5R-14V20%0.47UF

2

1 C2705

CERM-X5R-1

0.47UF

4V20%

201

2

1 C2707

4V

201

0.47UF

CERM-X5R-1

20%

2

1 C2709

20%

CERM-X5R-1201

4V

0.47UF

20 61 68

7 20 61 68

20 61 68

7 20 68

7 20 68

7 20 68

7 21 68

21 61 68

21 61 68

21 61 68

20 61 68

7 20 68

20 61 68

20 61 68

21 61 68

20 61 68

7 21 61 68

21 61 68

21 61 68

21 61 68

63RP27014X0201-HF1/32W5%

5620 61 68

20 61 68

21 61 68

21 61 68

2

1 C2708

CERM-X5R-1201

20%4V

0.47UF

54RP27014X0201-HF5%

561/32W

72RP27014X0201-HF1/32W5%

56

81RP27014X0201-HF1/32W5%

56

22 61 68

2

1 C2712

201

20%4VCERM-X5R-1

0.47UF

2

1 C2714

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2716

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2718

4V

201

20%0.47UF

CERM-X5R-1

2

1 C2719

CERM-X5R-1201

4V20%0.47UF

2

1 C27170.47UF

201

20%4VCERM-X5R-1

2

1 C2715

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2713

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2711

201

20%4V

0.47UF

CERM-X5R-1

2

1 C2710

201

4VCERM-X5R-1

20%0.47UF

54RP27124X0201-HF5%

561/32W

22 61 68

22 61 68

7 22 61 68

22 61 68

7 22 68

7 22 68

7 22 68

7 22 68

22 61 68

22 61 68

22 61 68

22 61 68

22 61 68

23 61 68

23 61 68

23 61 68

7 23 61 68

23 61 68

7 23 68

7 23 68

7 23 68

7 23 68

23 61 68

23 61 68

23 61 68

23 61 68

7 21 68

7 21 68

7 21 68

23 61 68

7 22 23 68

7 22 23 68

7 22 23 61 68

20 61 68

7 20 21 68

7 20 21 68

7 20 21 61 68

21R2700 562015% 1/20W MF

21R27011/20W5% 201 MF

39

21R27025% 2011/20W MF

39

21R2703 825% 2011/20W MF

21R27045% MF1/20W 201

82

21R27055%

56MF1/20W 201

21R27065%

561/20W MF201

54RP27034X0201-HF5%

561/32W

63RP27034X0201-HF5%

561/32W

72RP27034X0201-HF

565% 1/32W

54RP27074X0201-HF5%

561/32W

63RP27074X0201-HF5%

561/32W

72RP27074X0201-HF5%

561/32W

81RP27074X0201-HF5%

561/32W

21R27075%

39MF1/20W 201

21R27085%

391/20W MF201

21R27095%

82MF1/20W 201

21R27205% 1/20W

82MF201

21R27215%

56201 MF1/20W

54RP27044X0201-HF5%

561/32W

63RP27044X0201-HF5%

561/32W

72RP27044X0201-HF5%

561/32W

81RP27044X0201-HF5%

561/32W

21R27225%

82MF1/20W 201

21R27235%

821/20W 201 MF

21R27245%

82201 MF1/20W

63RP27124X0201-HF5%

561/32W

72RP27124X0201-HF5%

561/32W

81RP27124X0201-HF5%

561/32W

21R27105%

56MF1/20W 201

21R27115%

39MF1/20W 201

21R27125% 1/20W MF

39201

21R27135%

82MF1/20W 201

21R27145%

82MF1/20W 201

21R27155%

56MF1/20W 201

21R27165%

561/20W MF201

54RP27134X0201-HF5%

561/32W

63RP27134X0201-HF5%

561/32W

72RP27134X0201-HF5%

561/32W

54RP27174X0201-HF5%

561/32W

63RP27174X0201-HF5%

561/32W

72RP27174X0201-HF5%

561/32W

81RP27174X0201-HF5%

561/32W

21R27175%

39MF1/20W 201

21R27185% 1/20W MF

39201

21R27195%

82MF1/20W 201

21R27305%

82MF1/20W 201

21R27315%

56201 MF1/20W

54RP27144X0201-HF5%

561/32W

63RP27144X0201-HF5%

561/32W

72RP27144X0201-HF5%

561/32W

81RP27144X0201-HF5%

561/32W

21R27325%

82MF1/20W 201

21R27335%

82MF1/20W 201

21R27345% 1/20W MF

82201

21R27255%

561/20W MF201

21R27355%

562011/20W MF

2

1 C2720CRITICAL

22UF

X5R-CERM-1603

20%6.3V

PLACE_NEAR=RP2701.5:4mm

2

1 C2740

6.3VX5R-CERM-1

22UF

603

20%

CRITICAL

PLACE_NEAR=RP2714.8:4mm

81

RP2703

1/32W4X0201-HF

56

5%

81

RP2713

1/32W4X0201-HF

56

5%


LPDDR3 DRAM Termination

MEM_A_CAA<8>

MEM_A_CAA<9>

MEM_A_CAA<6>

MEM_A_CAA<7>

MEM_A_CAA<5>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<1>

MEM_A_CKE<0>

PP0V6_S0_DDRVTT

MEM_A_CAA<4>

MEM_A_CAA<3>

MEM_A_CAA<2>

MEM_A_CAA<1>

MEM_A_CAA<0>

MEM_A_CAB<9>

MEM_A_CAB<6>

MEM_A_CAB<8>

MEM_A_CAB<7>

MEM_A_CAB<5>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CAB<4>

MEM_A_CAB<2>

MEM_A_CAB<3>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_B_CAA<9>

MEM_B_CAA<8>

MEM_B_CAA<7>

MEM_B_CAA<6>

MEM_B_CAA<5>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CKE<1>

PP0V6_S0_DDRVTT

MEM_B_CAA<4>

MEM_B_CAA<2>

MEM_B_CAA<3>

MEM_B_CAA<1>

MEM_B_CAA<0>

MEM_B_CAB<9>

MEM_B_CAB<8>

MEM_B_CAB<7>

MEM_B_CAB<6>

MEM_B_CAB<5>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<2>

MEM_B_CKE<3>

MEM_B_CAB<4>

MEM_B_CAB<2>

MEM_B_CAB<1>

MEM_B_CAB<3>

MEM_B_CAB<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

<BRANCH>

<SCH_NUM>

<E4LABEL>

27 OF 120

24 OF 73

24 51 60 24 51 60

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

BI

BI

IN

IN

IN

IN

OUT

OUT

OUT

BI

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

VCC

DO/IO1

GND THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

MISC

PCIE GEN2

SYM 1 OF 2

PORTS

DISPLAY PORT

DPSNK1_1_P

DPSNK1_1_N

DPSRC_AUX_N

DPSRC_AUX_P

XTAL_25_OUT

REFCLK_100_IN_N

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_RX_N

PB_AUX_N

PA_DPSRC_3_N

PA_DPSRC_1_N

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_N

PA_AUX_N

GPIO_8/EN_CIO_PWR_N_OD

DPSRC_3_N

DPSRC_2_N

DPSRC_1_N

DPSRC_0_N

DPSNK1_AUX_N

DPSNK1_3_N

DPSNK1_2_N

DPSNK1_0_N

DPSNK0_AUX_N

DPSNK0_3_N

DPSNK0_2_N

DPSNK0_1_N

DPSNK0_0_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

PETN_0

PETP_0

PETP_1

PETN_1

PETP_2

RSENSE

PETN_2

PETP_3

PETN_3

RBIAS

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P

GPIO_16/DEVICE_PCIE_RST_N

RSVD_GND

GPIO_19

GPIO_18

GPIO_17

XTAL_25_IN

TMU_CLK_OUT

GPIO_2/TMU_CLK_IN/AC_PRESENT

DPSRC_HPD_OD

DPSRC_2_P

DPSRC_3_P

DPSRC_1_P

DPSRC_0_P

GPIO_3/FORCE_PWR

GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD

GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO

PB_CONFIG2/CIO_2_LSOE

GPIO_15

GPIO_14

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_CIO3_RX_P

PB_DPSRC_1_P

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSTX/CIO_3_LSEO

PB_LSRX/CIO_3_LSOE

PB_AUX_P

PERP_0

PERP_1

PERN_1

PERP_2

PERN_2

PERN_3

PWR_ON_POC_RSTN

MONDC1

MONDC0

EE_DI

THERMDA

MONOBSN

MONOBSP

EE_DO

EE_CLK

TCK

TDO

TEST_EN

TEST_PWR_GOOD

EE_CS_N

DPSNK0_3_P

DPSNK0_2_P

DPSNK0_1_P

DPSNK0_0_P

DPSNK0_HPD

DPSNK0_AUX_P

DPSNK1_3_P

DPSNK1_2_P

DPSNK1_HPD

DPSNK1_AUX_P

DPSNK1_0_P

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_P/DPSRC_2_P

PA_CIO0_TX_P/DPSRC_0_P

PA_DPSRC_3_P

PA_DPSRC_1_P

PA_CIO1_RX_P

PA_DPSRC_HPD

PA_AUX_P

PA_LSTX/CIO_1_LSEO

PA_LSRX/CIO_1_LSOE

GPIO_12/PA_DP_PWRDN/BYP2

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

PERST_OD_N

TDI

TMS

PERN_0

PERP_3

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

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PAGE

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



DEBUG: For monitoring current/voltage

SNK0 AC Coupling

SNK1 AC Coupling

(TBT_SPI_MISO)(TBT_SPI_MOSI)

(TBT_SPI_CLK)

Used for straps in host mode

depends on the code in the flash.

bit in the flash, so the active-level

Security strap setting is XORed with

If strap != bit then security is enabled?

(TBT_SPI_CS_L)

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

Divides 3.3V to 1.8V

NOTE: The following pins require testpoints:

8 - GPIO_15

9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

10 - GPIO_14

11 - GPIO_0

5 - PCIE_RST_1_N

0 - GPIO_13

3 - GPIO_3

2 - GPIO_2

4 - GPIO_5

1 - GPIO_1

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

2

1R2890

5%3.3K

201

1/20WMF

13

13 18

2

1R2825

201

1/20WMF

5%100

28

28 69

28 69

28

28 69

28 69

28 69

28 69

28 69

28 69

18

62

62

18

62

62

62

62

62

62

2

1R2830

5%100K

201

1/20WMF

2

1R2831

5%100K

201

1/20WMF

28 69

28 69

2

1R2893

5%3.3K

201

1/20WMF

21C282910% 16VX5R-CERM0.1UF

020113 65

13 65

5 65

5 65

5 65

5 65

5 65

5 65

5 65

5 65

21C282816V10%

X5R-CERM0.1UF0201

21C282710% 16VX5R-CERM0.1UF

0201

21C282616V10%

X5R-CERM0.1UF0201

21C282510% 16VX5R-CERM0.1UF

0201

21C282416V10%

0.1UF X5R-CERM0201

21C282310% 16VX5R-CERM0.1UF

0201

21C282216V10%

X5R-CERM0.1UF0201

2

1R2855

MF1/20W

201

1K1%

21C282110% 16VX5R-CERM0.1UF

0201

21C282010% 16VX5R-CERM0.1UF

0201

21C283010% 16VX5R-CERM0.1UF

0201

21C283110% 16VX5R-CERM0.1UF

0201

21C283210% 16VX5R-CERM0.1UF

0201

21C283310% 16VX5R-CERM0.1UF

0201

21C283410% 16V

0.1UF X5R-CERM0201

21C283510% 16VX5R-CERM0.1UF

0201

21C283610% 16VX5R-CERM0.1UF

0201

21C283710% 16VX5R-CERM0.1UF

0201

21C283810% 16VX5R-CERM0.1UF

0201

21C283910% 16V

0.1UF X5R-CERM0201

5 18 65

5 18 65

5 18 65

5 18 65

5 18 65

5 18 65

5 18 65

5 18 65

2

1C2890

402CERM6.3V10%1UF

BYPASS=U2890::2mm

13 18 65

13 18 65

28

28

62

18

15 18

62 69

62 69

18

15 16 18

18

15 16 18

18

28 69

28 69

28 69

28 69

28

25 27 28

28

25 28

25

18

25

25 26

35 36

12

17 67 21

R2895806

1%1/20WMF201

2

1R2896

5%1K

201MF1/20W

2

1R2899

201

10K

NO STUFF

1/20W5%

MF

12 67

12 67

26

2

1R2815

0201

OMIT

NONENONE

NOSTUFFNONE

2

1R2888

MF1/20W

201

10K5%

2

1R2887

5%1/20WMF201

10K

2

1R288610K

MF1/20W

201

5%

NO STUFF

2

1R2885

MF1/20W

201

10K5%

NO STUFF

2

1R2880

5%

201

1/20WMF

100K

15

25

15 18

2

1R2883100K

MF1/20W

201

5%

3

8

9

7

4

25

1

6U2890

CRITICAL

OMIT_TABLE

W25X40CLXIG

USON

4MBIT

25 27

25 28

2

1R2861

MF1/20W

201

10K5%

2

1R2863

5%10K

201

1/20WMF

2

1R2867

NO STUFF

5%10K

201

1/20WMF

2

1R2862

5%10K

201

1/20WMF

2

1R2881100K

5%

201

1/20WMF

2

1R2829

5%

MF1/20W

201

10K

2

1R2884

5%

201

1/20WMF

100K

2

1R2882100K5%

201

1/20WMF

15 25

2

1R2878

5%

201

1/20WMF

100K

2

1R2879100K

MF1/20W

201

5%2

1R2832100K

MF1/20W

201

5%

AB23

AA24

AA4

AB1

AB7

W8

R6

U6

W2

AA6

L8

AD1

U20

AB21

AD21

W20R4

AD17

AD13

AD9

AD5

AD19

AD15

AD11

AD7

P5

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

V3

M5

P7

N6

A22

B23

A20

B21

M1

D3

W24

U24

W22

U22

R24

N24

R22

N22

K3

K1

N8

J6

M3

A18

B19

A16

B17

K5

P1

L24

J24

L22

J22

G24

E24

G22

E22

L4

L2

W18

W16

AC24

AD23

M7

V7

T7

Y1

Y7

H5

L6

U2

F1

V1

AD3

AB3

W6

T3

T1

F3P3

R2N2

R8

Y3

AA2

T5

U8

AC2

J4

J2

A14

B15

A12

B13

A10

B11

A8

B9

U4

H3

H1

E6

D5

E8

D7

E10

D9

E12

D11

AB5

G4

G2

E14

D13

E16

D15

E18

D17

E20

D19

U2800FALCON-RIDGE-FR2C

FCBGA

OMIT_TABLE

CRITICAL

21C2801X5R-CERM16V

10% 02010.1UF

21C2800X5R-CERM16V

0.1UF10% 0201

21C2802X5R-CERM16V

0.1UF10% 0201

21C28030.1UF

X5R-CERM16V

10% 0201

2

1R2892

5%3.3K

201

1/20WMF

21C2804 16V0201X5R-CERM10%

0.1UF21C2805

X5R-CERM16V

10%0.1UF

0201

21C2806X5R-CERM16V

0.1UF10% 0201

21C2807X5R-CERM16V

0.1UF10% 0201

21C28400201

0.1UFX5R-CERM10% 16V

21C28410201


21C28420201


2

1R2891

5%3.3K

201

1/20WMF

21C28430201


21C28450201


21C28440201X5R-CERM

0.1UF10% 16V

21C28460201X5R-CERM

0.1UF16V10%

21C28470201X5R-CERM

0.1UF16V10%

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67

14 67


SYNC_MASTER=T29_RR SYNC_DATE=01/19/2013

PP3V3_TBTLC

DP_TBTSRC_HPD

PP3V3_S4

TBT_EN_CIO_PWR_L

HDMITBTMUX_SEL_TBT

TBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

PP3V3_S4

TBT_BATLOW_L

TBT_B_HV_EN

TBT_A_DP_PWRDN

TBTROM_WP_L

TBTROM_HOLD_L

PCIE_TBT_D2R_P<2>


DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_C_N<3> DP_TBTSNK0_ML_N<3>


PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>












PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

DP_TBTSNK1_ML_N<1>


DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_ML_P<0>





DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<3>


PP3V3_TBTLC

SYSCLK_CLK25M_TBT

PCIE_TBT_R2D_C_N<0>

TBT_A_HV_EN

TBT_B_DP_PWRDN

PP3V3_TBTLC

PP3V3_TBTLC

PCIE_TBT_R2D_P<3>

PCIE_TBT_R2D_N<0>

JTAG_TBT_TMS

XDP_JTAG_ISP_TDI


TBT_A_HV_EN

TBT_A_CIO_SEL

TBT_A_DP_PWRDN

TBT_A_LSRX

TBT_A_LSTX

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

TBT_A_D2R_P<1>

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_P<3>

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG1_BUF

TBT_A_CONFIG2_RC

TBT_A_D2R_P<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<3>

TBT_SPI_CS_L

TBT_TEST_PWR_GOOD

TBT_TEST_EN

JTAG_TBT_TDO

XDP_JTAG_ISP_TCK

TBT_SPI_CLK

TBT_SPI_MISO

TBT_MONOBSP

TBT_MONOBSN

TP_TBT_THERM_DP

TBT_SPI_MOSI

TP_TBT_MONDC0

TP_TBT_MONDC1

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

NC_DP_TBTPB_AUXCH_CP

TBT_B_LSRX

NC_TBT_B_LSTX

DP_TBTPB_HPD

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_P<1>

NC_TBT_B_D2RP<1>

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

TBT_B_HV_EN

TBTDP_AUXIO_EN

TBT_DDC_XBAR_EN_L

TBT_B_CONFIG2_RC

TBT_B_CONFIG1_BUF

NC_TBT_B_R2D_CP<1>

NC_TBT_B_R2D_CP<0>

NC_TBT_B_D2RP<0>

TBT_BATLOW_L

TBT_GPIO7

HDMITBTMUX_SEL_TBT

SMC_PME_S4_DARK_L

TBT_PWR_EN

TP_DP_TBTSRC_ML_CP<0>

NC_DP_TBTSRC_ML_CP<1>



DP_TBTSRC_HPD

TBT_GPIO2

TBT_TMU_CLK_OUT

SYSCLK_CLK25M_TBT_R

TBT_DFT_STRAP_1

TBT_ROM_SECURITY_XOR

TBT_DFT_STRAP_3

TP_TBT_PCIE_RESET0_L

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

TBT_RBIAS

PCIE_TBT_D2R_C_N<3>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<2>

TBT_RSENSE

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<0>


DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_N

TP_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_ML_CN<1>



TBT_EN_CIO_PWR_L

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<1>

TBT_A_R2D_C_N<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_N<3>

NC_DP_TBTPB_AUXCH_CN

NC_TBT_B_D2RN<0>

NC_TBT_B_R2D_CN<0>

NC_TBT_B_D2RN<1>

NC_TBT_B_R2D_CN<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

PCIE_CLK100M_TBT_N

TP_TBT_XTAL25OUT

NC_DP_TBTSRC_AUXCH_CP

NC_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

<BRANCH>

<SCH_NUM>

<E4LABEL>

28 OF 120

25 OF 73

17 18 25 26 60 62

25

25 26 27 29 34 36 37 56 60 62

25 26

15 25

25

25 28

25 26 27 29 34 36 37 56 60 62

25 27

25

25 28

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

17 18 25 26 60 62

25 27 28

25

17 18 25 26 60 62

17 18 25 26 60 62

67

67

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

69

69

69

69

67

67

67

67

67

67

62

62

62

62

25

67

67

67

67

67

67

67

67

67

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

25 65

62

62

62

62

62

62

25 65

25 65

w w w

. c h

i n a

f i x

. c o

m

NC

VER 3

D

S G

VOUT

GNDON

VIN

IN

OUTIN

IN

D

SYM_VER_3

SG

G VER 5

S DOUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

VCC1P0_CIO

VSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

SVR_VCC1P0

VSS

SVR_AMON

SVR_IND

GND

VCC

SYM 2 OF 2

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

Vth = 2.508V nominal

TBT "POC" Power-up Reset

Delay = 4.04ms nominal

Internal switch not functional on RR.

100 mA EDP2.4 W (Single-Port)

POC input to RR - 150 mA EDP

SVR input to RR - 1100 mA EDP

1900 mA EDP

700 mA EDP 1200 mA EDP

25 mA EDP

EDP: 1.25 A

1.05V TBT "CIO" SwitchLoad Switch

11.5 mOhm Max

8 mOhm Typ

Max Current = 4A (85C)

@ 1.05V

R(on)

Type

Part

Isolated to reduce noise from SVR

Push-pull output

TPS22920

3.1 W (Dual-Port)

Pull-up (S0) on PCH page

U2940

2

1C2906

20%1.0UF

X5R

6.3V

0201-1

2

1C2911

20%1.0UF

X5R

6.3V

0201-1

2

1C2910

0201-1X5R

6.3V

1.0UF20%

2

1C2922

6.3VCERM-X5R0402-1

10UF20%

2

1C2923

6.3VCERM-X5R0402-1

10UF20% K

A

D2920

NSR1020MW2T1G

SOD-323

CRITICAL

12

6Q2945DMN5L06VK-7SOT563

2

1

R2945100K

201

MF

1/20W

5%

C1

B1

A1

C2

B2

A2

D2

D1

U2940

CSP

TPS22920

CRITICAL

2

1 C2940

X5R6.3V

0201-1

1.0UF20%

2

1 C2981

20%1.0UF

X5R

6.3V

0201-1

2

1 C2980

20%1.0UF

X5R

6.3V

0201-1

2

1C2970

0201-1

6.3VX5R

20%

1.0UF

25

2

1C2960

0201-1

6.3V

X5R

1.0UF20%

2

1C2961

20%1.0UF

X5R

6.3V

0201-1

2

1C2953

20%

10UF

0402-1CERM-X5R

6.3V2

1C2952

6.3VCERM-X5R0402-1

10UF20%

2

1C2951

6.3VCERM-X5R0402-1

10UF20%

2

1C2950

6.3VCERM-X5R0402-1

10UF20%

2

1

XW2960

PLACE_NEAR=C2953.1:1mm

SM

25

2

1C2995

X7R-CERM

0201

10%

330PF

16V

2

1

R2991

1/20W

MF

201

24.9K1%

2

1 C2990

X5R

10%0.1UF

25V

402

15

2

1

R2995

MF

201

100K

1/20W

5%

17 27 35 36

2

1

R2990100K

1/20W

MF

201

5%

21

3

Q2995

DFN1006H4-3

DMN32D2LFB4

2

1C2991

X7R-CERM

10%

50V

0.001UF

0402

4

5

3

Q2945

DMN5L06VK-7SOT563

13

6

4

3

2

1

5

U2990TPS3895ADRY

USON

CRITICAL

2

1

R2992

1/20W

100K

201

MF

5%

Y9

AC12

Y23

Y21

Y19

Y17

Y15

Y13

Y11

V9

V23

V21

AC10

V13

U16

U12

T9

T23

T21

T17

T13

R20

R16

AB17

R12

P9

P23

P21

P13

N20

N16

N12

M9

M23

AB11

M21

M13

L20

L12

K23

K21

K13

J20

J16

J14AA8

H23

H21

G8

G6

G20

F9

F7

F5

F23

F21

AA22

F19

F17

F15

F13

F11

E4

D23

D21

C8

C6

AA20

C4

C24

C22

C20

C2

C18

C16

C14

C12

C10

AA14

B7

B1

AC8

AC6

AC4

AC22

AC20

AC18

AC16

AC14

A24

A2

W10

R18

N18

L18

H7

H17

H15

H13

Y5

W4

V5

N4

H11

E2

D1

K17

K15

J18

H9

H19

G18

G16

W14

G14

W12

V17

V15

U18

T19

P19

M19

L16

K7

K19

G12

G10

R10

P15

P11

N14

N10

M11

L10

K11

V11

U14

U10

T15

T11

R14

J12

J10

V19

P17

M17

M15

L14

K9

J8

B3

A6

A4

B5

U2800

CRITICAL

OMIT_TABLE

FALCON-RIDGE-FR2CFCBGA

21

L2920CRITICAL

0.68UH-20%-4.2A-0.032OHM

PIMB041B-SM

2

1C2903

0201-1

6.3V

X5R

1.0UF20%

2

1C2920

20%

10UF

0402-1CERM-X5R

6.3V2

1C2921

6.3VCERM-X5R0402-1

10UF20%

2

1C2904

20%

6.3V

X5R

0201-1

1.0UF

2

1C2905

20%1.0UF

X5R

6.3V

0201-1

2

1C2900

0201-1

6.3V

X5R

1.0UF20%

2

1C29011.0UF

X5R

6.3V20%

0201-1

2

1C2902

0201-1

6.3V

X5R

1.0UF20%

2

1C2932

20%1.0UF

X5R

6.3V

0201-1

2

1C2931

20%1.0UF

X5R

6.3V

0201-1

2

1C2930

20%1.0UF

X5R

6.3V

0201-1



MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

PP1V05_TBTCIO

PP3V3_S4

PP3V3_S4_TBT_F

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMMIN_LINE_WIDTH=0.38 MM


PP3V3_TBTRDV

VOLTAGE=3.3V



PP3V3_TBTLC

PP1V05_TBTRDVMIN_LINE_WIDTH=0.38 MM


TBT_PWR_REQ_L

PP3V3_S0

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR

PP3V3_TBTLC

TBT_PWR_ON_POC_RST_L

TBTPOCRST_CT

PP1V05_TBT

TBTPOCRST_SENSE

PP3V3_S4

PP3V3_S0

SMC_DELAYED_PWRGD

TBTPOCRST_MR_LTBT_POC_RESET_L

PP1V05_TBT

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.50 MM

VOLTAGE=1.05V


SWITCH_NODE=TRUEDIDT=TRUE


P1V05TBT_SW

<BRANCH>

<SCH_NUM>

<E4LABEL>

29 OF 120

26 OF 73

60 62

25 26 27 29 34 36 37 56 60 62 17 18 25 26 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

17 18 25 26 60 62

26 62

25 26 27 29 34 36 37 56 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

26 62

w w w

. c h

i n a

f i x

. c o

mIN

IN

S

G

D

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND GND

NC

SNS1

SNS2

SYM_VER_2

G S

D

VER 3

D

S G

VER 3

D

S G

OUT

D

SYM_VER_3

SG

IN

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



BATLOW# Isolation

Pull-up on RR page

Changes required

8-13V Input

SGND shorted to

no XW necessary.

GND inside package,

Vout = 1.6V * (1 + Ra / Rb)

<Rb>

<Ra>

Freq = 300KHz

Max Current = 1.0A

Vout = 15.1V

<R2>

UVLO(rising) = UVLO(falling) + (2uA * R1)

UVLO = 4.55V (falling), 4.95 (rising)

<R1>

Vgs(th): -1.4V

Id(max): 3.7A @ 70C

Vgs(max): +/-12V

SI8409DB:

Vds(max): -30V

Rds(on): 46mOhm @ 4.5V Vgs

Voltage not specified here,add property on another page.

Max Vgs: 10V

TBT 15V Boost Regulator

UVLO(falling) = 1.22 * (R1 + R2) / R2

for 2S.

Page NotesPower aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

- =PP15V_TBT_REG (15V Boost Output)

(NONE)

(NONE)

- =PPVIN_SW_TBTBST (8-13V Boost Input)

25 28

2

1R3080

5%

201

1/20WMF

470K

2

1 C30800.1UF

402X5R25V10%

2

1R3092

201

1/20WMF

73.2K1%

2

1R3087

5%

201

1/20WMF

330K

2

1R3094

201

1/20WMF

41.2K1%

2

1 C30940.33UF

402CERM-X5R6.3V10%

2

1R3088

5%

201

1/20WMF

330K

17 26 35 36

2

1 C3089

5%

NO STUFF

100PF

402CERM50V

2

1R309615.8K

1%1/16WMF-LF402

2

1 C309510UF

25V20%

0603X5R-CERM

2

1 C3087

5%47PF

25VNP0-C0G-CERM0201

2

1C30922.2UF

402

10V20%

X5R-CERM

4

1

32

Q3080

CRITICAL

BGASI8409DB

2

1R3091

201

1/20WMF

200K1%

2

1C309010UF

0603

25V20%

X5R-CERM 2

1C309110UF

0603

25V20%

X5R-CERM

2

1 C3088

5%50VCERM0402

22PF

27

30

34

38

21

2098

32

37

24

23

4

3

6

33

36

35

10

2

1

28

17

16

15

14

13

12

31

25

U3090CRITICAL

LT3957QFN

2 1

XW3095SM

PLACE_NEAR=C3095.1:2 mm

21

R3089

5%

0

0201

1/20WMF

KA

D3095POWERDI-123

DFLS230L

CRITICAL

2

1 C30990.001UF

0402X7R-CERM50V10%

2

1 C3093

X7R-CERM10V

3300PF

0201

10%

2

1R3081

5%

201

1/20WMF

150K

2

1R3093

201

1/20WMF

10K1%

2

1R3095133K

1%1/16WMF-LF402

21

L3095

PIMB062D-SM

6.8UH-4.0A

CRITICAL

1

2R3090

MF-LF1/16W

1%49.9K

402

2

1 C30822.2UF

402

10V20%

X5R-CERM

2

1C3081

20%10V

402

2.2UF

X5R-CERM

2

1C309610UF

0603

25V20%

X5R-CERM

2

1 C309710UF

0603

25V20%

X5R-CERM

2

1C309810UF

0603

25V20%

X5R-CERM

2

1 C308410UF

0603

25V20%

X5R-CERM

2

1C3085

20%25V

0603

10UF

X5R-CERM 2

1C309B10UF

0603

25V20%

X5R-CERM

2

1 C309A

20%25V

0603

10UF

X5R-CERM

21

3Q3005

DFN1006H4-3

DMN32D2LFB4

12

6 Q3088

SOT563

DMN5L06VK-7

45

3 Q3088

SOT563

DMN5L06VK-7

25 27

21

3

Q3000

DFN1006H4-3

DMN32D2LFB4

13 35


TBT Power Support

GND_TBTBST_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

TBTBST_PWREN_L

PPBUS_G3H

TBTBST_PWREN_DIV_L

TBT_A_HV_EN

TBTBST_RT

PPVIN_S4SW_TBTBST_FET


TBTBST_SNS1MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmTBTBST_VSNS


TBTBST_BOOSTMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

TBTBST_SS

TBTBST_VCMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

TBTBST_VC_RC

TBTBST_SNS2


MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmTBTBST_INTVCC

PP15V_TBT

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmTBTBST_FBX

TBTBST_VSNS_RC

TBTBST_EN_UVLO

TBTBST_SHDN_DIV

SMC_DELAYED_PWRGD

MAKE_BASE=TRUE

TBT_BATLOW_L

PP3V3_S4

TBT_BATLOW_LPM_BATLOW_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

30 OF 120

27 OF 73

39 40 47 48 54 60 62

60 62

28 60 62

25 27

25 26 29 34 36 37 56 60 62

w w w

. c h

i n a

f i x

. c o

m

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

BI

IN

IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+

DPMLO-

HPD

THMPADGND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENATB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN

IN

IN

V3P3

ISET_V3P3

OUT

THRMGND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

ML_LANE2N

ML_LANE2P

ML_LANE1N

ML_LANE1P

GND

GND

GND

HOT_PLUG_DETECT

CONFIG2

ML_LANE0P

ML_LANE0N

GNDGND

RETURN

AUX_CHN

CONFIG1

ML_LANE3N

ML_LANE3P

AUX_CHP

DP_PWR

SHIELD PINS

Apple Inc.


124578

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




514-0818

TBT: Unused


470k R’s for ESD protection

(0-18.9V)

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

IV3P3 1100mA 1030mA 1200mA

V3P3 must be S4 to support

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

Nominal Min Max

ILIM = 40000 / RISET

(Both C’s)

DP DirTBT Dir(Both C’s)

on AC-coupled signals.

(Both C’s)

TBT Dir

TBT: TX_0

(0-18.9V)

DP Dir

(Both C’s)

TBT: LSX_R2P/P2R (P/N)

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

Low: 0 - 0.8V

High: 2.0 - 5.0V

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(IPU)

(IPD)

(IPD)

(IPU)

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

<RV3P3>

Nominal Min Max

Single-fault protection

below

requires two R’s per HV

Single R on ISET_V3P3 OK.

12V: See

<RHVS0><RHVS3>

For 12V systems:

TBT: TX_1

TBT: RX_0

TBT: RX_1

ISET_Sx with CD3210.

15.75V Max

Sink HPD range:

wake from Thunderbolt devices.

3.3V/HV Power MUX

2

1C32000.01UF

X7R-CERM

0402

10%50V

25 69

25 69

2

1 C32020.01UF

X5R-CERM

10%16V

0201

21

R3201

MF

1/20W

201

5%

12

2

1 C32010.01UF

X7R-CERM

0402

10%50V

2

1R3294

5%

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

1/20WMF

201

1K

2

1R3295

5%

1K

MF

201

1/20W

GND_VOID=TRUE


2

1R3241

5%

100K

MF201

1/20W

2

1 C328610UF

CERM-X5R

0402

20%6.3V

2

1C32850.1UF

0201

10%16V

X5R-CERM

2

1 C32810.1UF

16V10%

0201

X5R-CERM2

1C3280

X5R-CERM-1

603

6.3V20%

22UF

2

1C3287

CRITICAL

POLY-TANTCASE-B2-SM

20%6.3V

100UF

2

1R3252

5%

1M

MF201

1/20W

2

1R3251

5%

1M

MF201

1/20W2

1C3294330PF

X7R-CERM0201

10%16V

2

1 C3295330PF

X7R-CERM0201

10%16V

21

L3200FERR-120-OHM-3A

0603

CRITICAL

25

2

1 C3210

402

25V

X5R

10%0.1UF

2

1R3270

5%

GND_VOID=TRUE

1/20W

201MF

470K

2

1R3271

5%

GND_VOID=TRUE

1/20W

201MF

470K

21C3271

GND_VOID=TRUE

6.3V20%0201X5R0.22UF

21C3270

GND_VOID=TRUE

6.3V20%

0201X5R0.22UF

25 69

25 69

21C3272

GND_VOID=TRUE

6.3V20%

0201X5R0.22UF

21C3273

GND_VOID=TRUE

6.3V20%0201X5R0.22UF

2

1R3273

5%

GND_VOID=TRUE

1/20W

201

MF

470K

2

1R3272

5%

GND_VOID=TRUE

1/20W

201

MF

470K

25 27

18 56 57

55 57

2

1R321236.5K

MF

201

1%1/20W

2

1 C3211

402

25VX5R

10%0.1UF

2

1C3220

X5R-CERM16V10%

0201

0.1UF

25

13 18

13 18

25

25

25 69

25 69

25 69

25 69

21C3232

X5R 020120% 6.3V

0.22UF

21C3233

X5R 0201

20% 6.3V0.22UF

25 69

25 69

21C3230

0201

X5R-CERM16V10%

0.1UF

21C323116V10%

X5R-CERM0.1UF0201

25 69

25 69

21C3278

X5R 020120% 6.3V

0.22UF

21C3279

X5R 0201

20% 6.3V0.22UF

25 69

25 69

2

1R3211

TBTHV:P15V

22.6K

MF

201

1%1/20W

2

1R3210

TBTHV:P15V

22.6K

MF

201

1%1/20W

2

1R3214

1/20W

1%

201MF

22.6K

TBTHV:P15V

2

1R3213

1/20W

1%

201MF

22.6K

TBTHV:P15V

2

1C3215

25V

4.7UF

X5R-CERM0603

10%

2

1C3205

25V

GND_VOID=TRUE

10%

0201X5R-CERM

0.01UF

2

1C3206

25V

0.01UF

X5R-CERM0201

10%

GND_VOID=TRUE

25

21C327420%

0.47UF CERM-X5R-1201

GND_VOID=TRUE

4V

21C327520%

0.47UF CERM-X5R-1

GND_VOID=TRUE

4V 201

3

25

8

7 15

14

13

12 17

219

19

20

6

11

10

4

5

16 18

22

23

24

2

1

U3220CRITICAL

CBTL05024

SIGNAL_MODEL=TBT_MUX

HVQFN24-COMBO

25

25

25

2

1R3279

5%

470K

MF201

1/20W

2

1R3278

5%

470K

MF201

1/20W

21C3277

CERM-X5R-1

GND_VOID=TRUE

20%0.47UF

4V 201

21C3276

CERM-X5R-1

GND_VOID=TRUE

20%0.47UF

4V 2017

6

18

20

19

21

17

14

12

8

9

1011

15

13321

416

5

U3210CRITICAL

QFNCD3211A1RGP

19

10

12

15

17

9

11

3

5

28

27

26

25

24

23

22

21

2

14 8

13 7

1

20

6

4

16

18

J3200MDP-J11

CRITICAL

F-RT-TH



2 R3210,R3213 TBTHV:P12V118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3211,R3214118S0145 TBTHV:P12V2 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

PM_SLP_S3_BUF_L

PP3V3_S5

TBTAPWRSW_ISET_V3P3


PP3V3RHV_S4_TBTAPWR

VOLTAGE=15V

TBT_A_HV_EN

S4_PWR_EN

TBTAPWRSW_ISET_S0

VOLTAGE=3.3V



PP3V3_S4_TBTAPWR

TBTAPWRSW_ISET_S3

PP15V_TBT

TBT_A_D2R_P<1>TBT_A_D2R_C_P<1>

TBT_A_D2R_N<1>TBT_A_D2R_C_N<1>

DP_TBTPA_AUXCH_C_NDP_TBTPA_AUXCH_P

TBTAPWRSW_ISET_S3_R

TBTAPWRSW_ISET_S0_RDP_TBTPA_HPD

TBT_A_LSRX

TBT_A_LSTX

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_DDC_CLK

TBT_A_CONFIG1_BUF

TBT_A_D2R1_AUXDDC_N

DP_TBTPA_AUXCH_N

DP_TBTPA_ML_N<1>

DP_TBTPA_ML_P<1>

TBT_A_HPD

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

TBT_A_CONFIG1_RC

PP3V3_S4_TBTAPWR

TBT_A_CONFIG1_RC

TBT_A_CONFIG2_RC

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_P<0>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

TBT_A_D2R_N<0>

TBT_A_D2R_P<0>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_P<1>

TBT_A_D2R1_AUXDDC_P

TBT_A_DP_PWRDN

TBTDP_AUXIO_EN

TBT_A_CIO_SEL

VOLTAGE=18VMIN_NECK_WIDTH=0.20 MM


TBTACONN_20_RC


PP3V3RHV_S4_TBTAPWR_F

MIN_NECK_WIDTH=0.20 MMVOLTAGE=15V

TBT_A_D2R1_AUXDDC_P

DP_TBTPA_ML_P<3>

DP_TBTPA_ML_N<3>

TBT_A_D2R_C_P<0>

TBT_A_D2R1_AUXDDC_N

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM

TBTACONN_7_C

TBT_A_R2D_N<0>

TBT_A_R2D_P<0>

TBT_A_D2R_C_N<0>

TBT_A_HPD


TBTACONN_1_CMIN_LINE_WIDTH=0.38 MM

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

TBT_A_R2D_P<1>

TBT_A_R2D_N<1>

<BRANCH>

<SCH_NUM>

<E4LABEL>

32 OF 120

28 OF 73

8 11 13 15 16 17 18 29 40 52 55 56 57 58 60 62 72

28 60

27 60 62

69

69

69 28 69

69

69

69

28

28 69

28 69

28

28 60

28

28 69

28 69

69

69

69

28 69

69

69

69

28

28 69

28 69

69

69

w w w

. c h

i n a

f i x

. c o

mIN

IN

IN

IN

OUT

OUT

OUT

NC

BI

BI

BI

IN

GND

VOUT

ON

VIN

IN

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE

RESET*

+-

PAD

(OD)

DLY

VREF

IN

DP_2

DM_2

DM_1

DP_1

S

DP

GND

VDD

OE*

DM

OUT

SYM_VER_2

G S

D

IN

GND

VCC

A

B0

B1

S

VER-3 OUT

OUT

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

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B

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Supervisor & CLKREQ# Isolation

Delay = 130 ms +/- 20%

AIRPORT

Sense resistor on

sensor page

Type

R(on)

@ 2.5V

Part

18.5 mOhm Typ

Load Switch

25.8 mOhm Max

TPS22924C

3.3V WLAN Switch

514S0335

Max Current = 2A (85C)

SEL OUTPUT

H USB_BT (2)

L BT_WAKE (1)

BLUETOOTH

H AP_S0IX_WAKE_L (B1)

L PCIE_WAKE_L (B0)

SEL OUTPUT

PCIe Wake Muxing

14 67

14 67

12 62 67

12 62 67

2

1 C3521

10%0.1UF

0201CERM-X5R6.3V

BYPASS=J3501:5mm

14 62 67

14 62 67

2

1 C3532

10%0.1UF

0201CERM-X5R6.3V

BYPASS=J3501:1.5mm

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

21

20

19

J3501SSD-K99F-RT-SM1

CRITICAL

35 36 62

2

1 C3510

10%0.1UF

0201CERM-X5R6.3V

14 66

14 66

12

29 35 37

2

1R3553100K

APCLKRQ:ISOL

MF1/20W

201

5%

2

1R3554

1%232K

MF1/20W

201

2

1R3555

1%100K

MF1/20W

201

2

1 C3540

10%0.1UF

0201CERM-X5R6.3V

21C353110%

0.1UF X5R-CERM16V0201

21C353010%

0.1UF X5R-CERM 020116V

B1

A1

B2

A2

C2

C1

U3550

CRITICAL

CSPTPS22924

29 35 37

2

1 C3550

X5R6.3V

1.0UF20%

0201-1

2

1R3556APCLKRQ:ISOL

MF1/20W

0201

05%

2 1

R3557

APCLKRQ:BIDIR

MF1/20W

0201

0

5%

1

9

2

4

8

3

7

5

6

U3540SLG4AP041V

TDFNCRITICAL

21

R3558

MF1/20W

0201

0

5%

2 1

R3559

NOSTUFF

MF1/20W

0201

0

5%

15

5

4

3

8

6

2

107

1

9

U3510

SIGNAL_MODEL=BT_MUX

DFNUSB3740

CRITICAL

34 35 37

2

1R3512

1%15K

MF1/20W

201

21

3Q3510DMN32D2LFB4


DFN1006H4-3

13 18 34 35 57

5

6

2

1

3

4

U3560CRITICAL

SC70

NC7SB3157P6XG

13 31 62

2

1C3560

10%0.1UF

0201CERM-X5R

6.3V

15

15

21

R3560

NOSTUFF

MF1/20W

0201

0

5%

2

1R3561100K

MF1/20W

201

5%


Wireless Connector

SYNC_MASTER=J43_MLB

AP_S0IX_WAKE_SEL

AP_S0IX_WAKE_L

PCIE_WAKE_L

PP3V3_S5

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_WLANMIN_LINE_WIDTH=0.5 mm

AP_RESET_L

AP_CLKREQ_L

PCIE_AP_R2D_C_P

WIFI_EVENT_L

AP_CLKREQ_R_L

PCIE_AP_R2D_N

PCIE_AP_R2D_P

PP3V3_WLAN_R

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

SMC_WIFI_PWR_EN

PP3V3_S5

SMC_WIFI_PWR_EN

PCIE_AP_R2D_C_N

P3V3WLAN_VMON

AP_RESET_CONN_R_L

PM_SLP_S4_L

USB_BT_N

USB_BT_P

SMC_PME_S4_WAKE_L

BT_WAKE

PP3V3_S4

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_P

PP3V3_S4

PCIE_AP_D2R_N

PCIE_AP_D2R_P

AP_RESET_CONN_L

AP_CLKREQ_Q_L

PP3V3_S5

AP_PCIE_WAKE_L

USB_BT_CONN_N

USB_BT_CONN_P

<BRANCH>

<SCH_NUM>

<E4LABEL>

35 OF 120

29 OF 73

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

35 36 37 39 62

62 67

62 67

39

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

25 26 27 29 34 36 37 56 60 62

25 26 27 29 34 36 37 56 60 62

62

62

8 11 13 15 16 17

18 28 29

40 52 55

56 57 58

60 62 72

62 66

62 66

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

IN

NC

08

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

NC

08

IN

NC

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLY

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SMC_PWRFAIL_WARN_L Signal no connect on X31

Delay = ~55ms

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

GND_VOID

514S0449

OOB Isolation

GND_VOID

Gumstick3 Connector

PCIe polarity inversion and lane reversal

provided the device PHY supports it.are only permitted on the device side,Supervisor & CLKREQ# Isolation

35

2

1 C3702

10%0.1UF

10VX5R-CERM0201

PLACE_NEAR=L3700.1:1mm

21

L3700

0603


FERR-26-OHM-6A

CRITICAL

2

1 C3701

10%0.1UF


10VX5R-CERM0201

2

1R3742

201MF

1%100K

1/20W

2

1R3740

201

100K

1/20WMF

5%

2

1R3741

201

1%

MF1/20W

232K

12

2

1 C3740

10%

0201

6.3VCERM-X5R

0.1UF

15

15 30 56 57 62

4

6

5 3

1

2

U3711

74LVC1G08

CRITICAL

BYPASS=U3711:5 mm

SOT891

2

1C3719

10%0.1UF

0201X5R-CERM

10V

12 65

12 65

12 65

12 65

12 65

12 65

12 65

12 65

21C371610%

0.1UF

GND_VOID=TRUE16V 0201X5R-CERM

21C371710%

0.1UF16V 0201X5R-CERM

GND_VOID=TRUE

21C371310%

0.1UF

GND_VOID=TRUEX5R-CERM16V 0201

21C371210%

0.1UF


21C371510%

0.1UF

GND_VOID=TRUE16V 0201X5R-CERM

21C371410%

0.1UF


21C371110%

0.1UFX5R-CERM16V 0201

GND_VOID=TRUE

21C371010%

0.1UF020116V X5R-CERM

GND_VOID=TRUE

12 62 65

12 62 65

12 62 65

12 62 65

12 62 65

12 62 65

12 62 65

12 62 65

12 62 65

12 62 65

15 30 56 57 62

35 62

30 62

9

8

7

63

62

61

60

6

59

58

57

56

55

54

53

52

51

505

49

48

47

46

45

44

43

42

41

40

4

39

38

37

36

35

34

33

32

31

30

3

2928

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3700SSD-GS3

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE TRUE

TRUE

CRITICAL

TRUE

F-RT-SM

TRUE

2

1R3700NOSTUFF

201

100K

1/20WMF

1%

4

6

53

1

2

U3710

74LVC1G08

CRITICAL

SOT89135

2

1 C3718

10%0.1UF

10V

0201X5R-CERM

BYPASS=U3710:5 mm

2

1R3710NOSTUFF

201

100K

1/20WMF

5%

1

9

2

4

8

3

7

5

6

U3740SLG4AP016V

TDFN

CRITICAL

15 62

21R3701

NOSTUFF

0

MF 0201 5% 1/20W

13

2

1R3703

1%

MF1/20W

100K

201

21

R3702

0201

0

1/20WMF

5%


SSD Connector

SSD_PCIE_SEL_L

SSD_PCIE_SEL_L

SMC_OOB1_D2R_CONN_L

PCIE_SSD_R2D_C_P<1>

PP3V3_S0SW_SSD

SSD_RESET_CONN_L

SSD_CLKREQ_L

SSD_PWR_EN

SSD_RESET_L

SSD_CLKREQ_CONN_L

PP3V42_G3H

P3V3SSD_VMON

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<2>

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCIE_SSD_D2R_P<3>

SMC_PWRFAIL_WARN_L

TP_SSD_DEVSLP

SSD_PWR_EN

SMC_OOB1_R2D_CONN_L

SMC_OOB1_R2D_L

PP3V3_S0SW_SSD

PP3V3_S0

SMC_OOB1_D2R_L

PCIE_SSD_R2D_P<0>

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_N<3>

PCIE_SSD_R2D_P<3>

PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_P<2>

PP3V3_S0

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_N<1>

MIN_NECK_WIDTH=0.15mmMIN_LINE_WIDTH=0.6mmPP3V3_S0SW_SSD_FLT

VOLTAGE=3.3V

PP3V3_S0SW_SSD

SSD_SR_EN_L

SSD_BOOT_RSSD_BOOT

PCIE_SSD_D2R_N<3>

<BRANCH>

<SCH_NUM>

<E4LABEL>

37 OF 120

30 OF 73

30 62

62

30 39 60 62

62

62

17 33 34 35 36 38 44 46 47 48 57 59 60 62 63

62

30 39 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39

40 41 42 43 54 57 59

60 62 63 72

62 65

62 65

62 65

62 65

62 65

62 65

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

62 65

62 65

62 30 39 60 62

w w w

. c h

i n a

f i x

. c o

m

NCNC

NCNC

OUT

IN

OUT

BI

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

SYM 1 OF 3

DEBUG_15

DEBUG_14

PWR_MODE

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03

DEBUG_04

DEBUG_05

DEBUG_09PCIE_RDP0

DEBUG_06

DEBUG_00

DEBUG_01

DEBUG_02

DEBUG_07

DEBUG_08

DEBUG_10

DEBUG_11

DEBUG_12

DEBUG_13

DEBUG_16

GPIO_00

GPIO_01

GPIO_02

GPIO_03

GPIO_04

GPIO_05

GPIO_06

GPIO_07

I2C_CLK_DBG

I2C_CLK_SENSOR

I2C_DATA_DBG

I2C_DATA_SENSOR

JTAG_TCK

JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS

UARTRTS

UARTRXD

UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1

MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00

DDR_AD01

DDR_AD02

DDR_AD03

DDR_AD04

DDR_AD05

DDR_AD06

DDR_AD07

DDR_AD08

DDR_AD09

DDR_AD10

DDR_AD11

DDR_AD12

DDR_AD13

DDR_AD14

DDR_BA0

DDR_BA1

DDR_BA2

DDR_CS*

DDR_DM0

DDR_DM1

DDR_DQ00

DDR_DQ01

DDR_DQ02

DDR_DQ03

DDR_DQ04

DDR_DQ05

DDR_DQ06

DDR_DQ07

DDR_DQ08

DDR_DQ09

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

SYM 3 OF 3

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

NC

OUT

NCNCNC

NCNC

NCNCNC

NCNCNC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PU on PCH page

PD = 1.35V

PU = 25MHz

A1 SILICON BUG

L3902:1

L3901:1

(=PP3V3_S3RS0_CAMERA)

(=PP3V3_S3RS0_CAMERA)

12

32

32 62

32 62

2

1R3930

MF1/20W5%

NOSTUFF

100K

201 2

1R3932NOSTUFF

1/20W5%

201MF

100K

18

15 18

2

1 C3900

10%0.1UF

0201CERM-X5R6.3V

2

1 C3924

10%0.1UF

0201CERM-X5R6.3V

2

1 C3923

X5R6.3V20%

0201-1

1.0UF

2

1 C3922

10%0.1UF

0201CERM-X5R6.3V

2

1 C3921

X5R6.3V

1.0UF

0201-1

20%

2

1 C3910

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.D6:2.54MM

2

1 C3951

10%0.1UF

0201CERM-X5R6.3V


2

1R3901

5%

201

1/20WMF

100K

32 67

32 67

32 67

32 67

32 67

32 67

32 67

32 67

2

1R3906

5%

201

1/20WMF

CAM_XTAL:YES

100K

2

1R3907

5%

201

1/20WMF

CAM_XTAL:NO

100K

2

1R3904

5%

201

1/20WMF

100K

21

L3901

1008

PLACE_NEAR=U3900.M13:4MM

1.0UH-1.6A-55MOHM

21

L3902

PLACE_NEAR=U3900.K13:4MM

1008

1.0UH-1.6A-55MOHM

21

L390622NH

0402

2

1 C3916

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.L7:2.54MM

2

1 C3919

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.J1:2.54MM

2

1 C3937

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900:5mm

2

1 C3935

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900:5mm

2

1 C3940

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900:5mm

2

1 C3941

6.3V

BYPASS=U3900.F15:2.54MM

2.2UF20%

402-LFCERM

2

1 C3939

10%

X5R

BYPASS=U3900.G15:2.54MM

1UF

10V

402

2

1 C3960

10%0.1UF

0201CERM-X5R6.3V

A13

A12

E14

E13

D14

D13

J12

M10

C12

C13

H12

R13

E15

G12

N12

B9

C9

A8

B8

R14

B10

A10

B7

A7

P13

P6

P8

R6

R8

P7

R7

D11

D12

F12

E12

F13

C11

R9

C15

R10

D15

N9

N10

N11

P9

P10

P11

P12

R12

L10

L11

K10

K11

J10

H10

H11

G10

G11

F10

F11

E10

E11

A15

B14

C14

B11

U3900

CRITICAL

BCM15700FBGA

OMIT_TABLE

G3

J2

R3

H3

A2

E2

A3

D2

B3

B2

C5

A5

B4

B1

C3

B5

F2

F4

F1

F3

D3

E4

E3

C2

C4

C1

L4

J3

H2

G2

H4

K2

L2

K3

R4

P1

L1

R2

J4

P2

P3

N2

P4

M2

M1

M3

N3

M4

L3

U3900BCM15700

CRITICAL

FBGA

OMIT_TABLE

B12

B13

G8

G7

G6

G1

E5

D5

E9

R5

R1

P5

D1

N1

M9

A14

K9

K8

K7

K6

K5

K1

J9

B6

J8

J7

J6

J5

H9

H8

H7

H6

H5

G9

A6

A1

K12

M11

R11

B15

L9

L8

L5

L6

F9

F8

F7

F6

J11

F14

G15

F15

K14

K13

N14

M13

J15

J14

J13

H15

H14

N15

M15

M14

L15

L14

L13

L12

K15

R15

P15

P14

N13

M12

G14

D6

C8

D9

C7

C10

D7

L7

N6

N8

N7

N5

G5

N4

K4

G4

D4

A4

J1

U3900

CRITICAL

BCM15700FBGA

OMIT_TABLE

2

1 C3918

10%

BYPASS=U3900.J1:2.54MM

16VX7R-CERM0201

1000PF

2

1 C3934

10%1000PF

X7R-CERM0201

16V

BYPASS=U3900:3mm

2

1 C3917

10%


1000PF

16VX7R-CERM0201

2

1 C3936

10%

BYPASS=U3900:3mm

0201X7R-CERM

1000PF

16V

2

1 C3938

10%16V

1000PF


0201X7R-CERM

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32 70

32

2

1R3910

5%

201

1/20WMF

NO STUFF

100K

2

1R3911

5%

201

1/20WMF

100K

21

R3912

201

1/20WMF

1%

240

2

1R3913

5%

201

1/20WMF

1K

2

1R3914

5%

201

1/20WMF

1K

32 70

21

XW3900SM

21

XW3901SM

2

1R3990

5%

201

1/20WMF

100K

2

1 C3990

10%0.1UF

0201CERM-X5R6.3V

NOSTUFF

2

1 C3927

10%0.1UF

0201CERM-X5R6.3V

2

1 C3930

X5R6.3V

1.0UF20%

0201-1

32 70

2

1 C3932

X5R6.3V

0201-1

1.0UF20%

2

1 C3931

20%10UF

6.3VCERM-X5R0402-1

2

1 C3933

20%10UF

6.3VCERM-X5R0402-1

2

1R3915

5%

201

1/20WMF

CAM_A1

100K

21

L3903

0603

220-OHM-1.4A

21

L3904220-OHM-1.4A

0603

21

R3991

NOSTUFF

5%

0

0201

1/20WMF

13 29 62

2

1 C3975

6.3V10%0.1UF

0201CERM-X5R


2

1 C3974

10%0.1UF

0201CERM-X5R6.3V


2

1 C3973

10%1000PF


16VX7R-CERM0201

2

1 C3972

10%0.1UF

0201CERM-X5R6.3V


2

1 C3971


10%

0201

16V

1000PF

X7R-CERM2

1 C3970

10%0.1UF

0201CERM-X5R6.3V


2

1R3975

5%

201

1/20WMF

51K

2

1R3976

5%

201

1/20WMF

51K

2

1R3920

5%

201

1/20WMF

100K

2

1R3921

5%

201

1/20WMF

100K

2

1R3934NOSTUFF

1/20W5%

201MF

100K

2

1R3931

MF1/20W5%330K

2012

1R3933

MF1/20W5%330K

2012

1R3935

MF

5%330K

201

1/20W

2

1R3936

5%

201

1/20WMF

100K

NOSTUFF

2

1R3937

5%

201

1/20WMF

100K

NOSTUFF

2

1 C3912

X5R6.3V

BYPASS=U3900.K13:2.54MM

402

20%4.7UF

2

1 C3913

X5R6.3V

402

20%4.7UF

2

1 C3914

X5R6.3V20%4.7UF

402

2

1 C3915

X5R6.3V

4.7UF

402

20%

PLACE_NEAR=U3900.M13:2.54MM

2

1 C3926

X5R6.3V

PLACE_NEAR=U3900.M14:2.54MM

402

20%4.7UF

2

1 C3928

X5R6.3V

402

20%4.7UF

2

1 C3942

X5R6.3V

402

BYPASS=U3900:7mm

20%4.7UF

32 70

SYNC_MASTER=J43_MLB1

Camera 1 of 2SYNC_DATE=01/09/2013

PP1V8_CAM

CAM_RAMCFG0

CAM_RAMCFG1

CAM_RAMCFG2

PP1V2_CAM

PP1V2_CAM_PCIE_VDD_FLT

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

PP1V8_CAM

GND_CAM_PVSSD

MEM_CAM_A<14>

MEM_CAM_A<13>

PP1V8_CAM

MEM_CAM_A<3>

MEM_CAM_A<4>

MEM_CAM_A<5>

MEM_CAM_A<7>

MEM_CAM_A<10>

MIN_LINE_WIDTH=0.6MMP1V2_CAM_SRVLXC_PHASE

MIN_NECK_WIDTH=0.2MMDIDT=TRUE

PP3V3_S3RS0_CAMERA

PCIE_CAMERA_D2R_C_P

TP_CAM_PLL_BYPASS

CAM_GPIO3

CAM_UARTCTS

CAM_UARTRXD

TP_CAM_UARTTXD

CAM_RAMCFG1

CAM_RAMCFG2

CAM_RAMCFG0

TP_CAM_UARTRTS

CAM_XTAL_FREQ

CAM_TEST_MODE

CAM_TEST_OUT

CAM_XTAL_SEL

TP_CAM_LV_JTAG_TRSTN

TP_CAM_TEST_MODE0

TP_CAM_TEST_MODE1

TP_CAM_TEST_MODE2

TP_CAM_LV_JTAG_TCK

TP_CAM_LV_JTAG_TDI

TP_CAM_LV_JTAG_TDO

TP_CAM_LV_JTAG_TMS


GND_CAM_PVSSDMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

P1V35_CAM_SRVLXD_PHASE

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

GND_CAM_PVSSC

MIN_NECK_WIDTH=0.2MM

GND_CAM_PVSSC

PCIE_CLK100M_CAMERA_C_P

VOLTAGE=1.2V


PP1V2_CAM_PCIE_PVDD_FLT

I2C_CAM_SDA

I2C_CAM_SCK

CAM_PCIE_WAKE_L

CAM_PCIE_RESET_L

CAM_TEST_OUT

PCIE_WAKE_L

PP1V8_CAM

CAM_TEST_MODE

MEM_CAM_RESET_L

MEM_CAM_CAS_L

MEM_CAM_WE_L

MEM_CAM_RAS_L

MEM_CAM_DQS_N<1>

MEM_CAM_DQS_P<1>

MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<0>


CAMERA_CLKREQ_L

P1V35_CAM_SRVLXD_PHASE

CLK25M_CAM_CLKP

CAM_UARTRXD

CAM_UARTCTS

CAM_XTAL_FREQ

PP1V8_CAM

CAM_XTAL_SEL

CAM_PWR_SEL

CAM_DEBUG_RESET_L

PP1V8_CAM

PP1V8_CAM

PCIE_CAMERA_R2D_P

MIPI_DATA_P

I2C_CAM_SMBDBG_CLK

I2C_CAM_SMBDBG_DAT

TP_CAM_JTAG_TCK

CAM_JTAG_SRST_L

TP_CAM_JTAG_TRST_L

TP_CAM_JTAG_TDO

TP_CAM_JTAG_TDI

TP_CAM_JTAG_TMS

CAM_SENSOR_WAKE_L

CAMERA_PWR_EN

CAM_JTAG_SRST_L

MEM_CAM_DQ<0>

MEM_CAM_DQ<1>

MEM_CAM_DQ<2>

MEM_CAM_DQ<3>

MEM_CAM_DQ<4>

MEM_CAM_DQ<5>

MEM_CAM_DQ<7>

MEM_CAM_DQ<8>

MEM_CAM_DQ<9>

MEM_CAM_DQ<10>

MEM_CAM_DQ<11>

MEM_CAM_DQ<12>

MEM_CAM_DQ<13>

MEM_CAM_DQ<14>

MEM_CAM_DQ<15>

MEM_CAM_CS_L

MEM_CAM_CKE

MEM_CAM_DM<1>

MEM_CAM_DM<0>

MEM_CAM_CLK_N

MEM_CAM_CLK_P

MEM_CAM_BA<2>

MEM_CAM_BA<1>

MEM_CAM_BA<0>

MEM_CAM_A<12>

MEM_CAM_A<11>

MEM_CAM_A<9>

MEM_CAM_A<8>

MEM_CAM_A<6>

MEM_CAM_A<2>

MEM_CAM_A<1>

MEM_CAM_A<0>

MEM_CAM_ZQ_S2

VOLTAGE=1.35V


PP1V35_DDR_CLK

VOLTAGE=0.675VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP0V675_CAM_VREF

PP1V2_CAM

PP1V35_CAM

PP1V35_CAM

VOLTAGE=1.2V


MAKE_BASE=TRUE



PP1V2_CAM

VOLTAGE=1.2V


GND_CAM_PVSSC

I2C_CAM_SMBDBG_CLK

I2C_CAM_SMBDBG_DAT

PP1V8_CAM

P1V2_CAM_SRVLXC_PHASE

PP1V8_CAM

MEM_CAM_DQ<6>

PCIE_CAMERA_R2D_N


GND_CAM_PVSSD

VOLTAGE=1.35V

PP1V35_CAMMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

MIPI_CLK_P

MIPI_CLK_N

MIPI_DATA_N

PCIE_CAMERA_D2R_C_N

CLK25M_CAM_CLKN

PCIE_CLK100M_CAMERA_C_N

<BRANCH>

<SCH_NUM>

<E4LABEL>

39 OF 120

31 OF 73

31 32

31

31

31

31

31

31

15 39

31

31

31

31

31

31

31

31

31

31

31

31

31 32

31 17 31

31

31

31

31

31 32

31

31 32

31 32

31

31

31

31

32 70

31

31 32 70

31 32 70

17 31

31

31

31

31

31 32

31

31 32

17 31

31

31 32 70

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

OUT

OUT

IN

IN

IN

IN

BI

IN

IN

IN

BI

BIBI

IN

A4

A14

DQSL*

DQL1

VDD

A2

A3

A1

A0

NC

A6

ODT

RESET*

VSSQ VSS

CAS*

RAS*

BA2

BA0

BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML

DMU

DQL5

DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NCNCNCNCNC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

SYM_VER-1

SYM_VER-1

NCNC

OUT

IN

OUT

OUT

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



CAMERA SENSOR

518S0892

NOTE: TBD PPM crystal required

ALS

77.2 mA nominal max

96.2 mA peak

31 67

31 67

14 67

14 67

21C403310%


21C403210%


21C403110%

0.1UFX5R-CERM 020116V

21C403010%

0.1UFX5R-CERM 020116V

14 67

14 67

31 67

31 67

21

R4009

5%

0

0201

1/20WMF

CAM_XTAL:YES

21

R4010

5%

0

0201

1/20WMF

CAM_XTAL:YES

21

R4008

5%

0

02011/20W

MF

CAM_XTAL:NO

21

R4007

5%

0

02011/20WMF

CAM_XTAL:YES

21

R4000

5%

0

0201 MF1/20W

2

1 C4004

201

BYPASS=U4000.H9:4mm

0.47UF

CERM-X5R-14V20%

2

1 C4008

402

10V

2.2UF20%

X5R-CERM

BYPASS=U4000.K2:4mm

2

1 C4006

402

20%10VX5R-CERM

2.2UF

BYPASS=U4000.D2:4mm

2

1R4012

201

1/20WMF

1%1M

NOSTUFF

21

C4015

5%25V

0201

12PFCAM_XTAL:YES

NP0-C0G-CERM

21

C4014

5%25V

CAM_XTAL:YES

12PF

NP0-C0G-CERM0201

2

1 C4009

10%0.1UF

0201CERM-X5R6.3V

2

1 C4007

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U4000.R9:4mm

2

1C4013

402

0.1uF

10VCERM

20%

31 62

31 62

2

1 C4005

10%0.1UF

0201CERM-X5R6.3V

31 70

31 70

31 70

31 70

2 1

L4010

0402-LF

FERR-120-OHM-1.5A

2

1 C4003BYPASS=U4000.B2:4mm

20%10UF

6.3VCERM-X5R0402-1

2

1 C4002BYPASS=U4000.A1:4mm

20%10UF

6.3VCERM-X5R0402-1

14 35 38 41 42 62 67 71

14 35 38 41 42 62 67 71

2

1R4022

201

1/20WMF

1%1K

2

1R4023

201

1/20WMF

1%1K

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

P9

P1

M9

M1

J8

J2

G8

E1

T9

T1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

M7

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

T7

T3

N7

R7

L7

P7

N3 U4000

CRITICAL

FBGAH5TC4G63AFR

4GB-DDR3-256MX16

31 70

31 70

2

1 C4011

10%0.1UF

0201

6.3VCERM-X5R

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

2

1C4010

10%0.1UF

0201CERM-X5R

6.3V

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31

31 70

31 70

31 70

31 70

2

1R4020

201

1/20WMF

84.51%

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

31 70

2

1R4021

201

1/20WMF

821%

NO STUFF

31 70

2

1R4002

5%

201

1/20WMF

1K

2

1R4003

5%

201

1/20WMF

1K

NOSTUFF

2

1R4004

201

1/20WMF

2401%

21

R4030

5%

0

02011/20WMF

CAM_WAKE:YES

2

1 C4016

5%25V

0201NP0-CERM

CAM_XTAL:NO

100PF

2

1R4031

5%0

0201

1/20WMF

CAM_WAKE:NO

9

8

7

6

5

4

3

2

12

11

10

1

13

14

J4002CCR20-AK7100-1

CRITICAL

F-RT-SM

21C406110%


21C406210%


2 1

L4011FERR-120-OHM-1.5A

0402-LF

NOSTUFF

2

1 R4006

5%25V

NO STUFF

100PF

0201NP0-CERM

31 70

4

32

1

L400990-OHM-0.1ATCM0605

PLACE_NEAR=J4002.2:2.54MMCRITICAL

4

32

1

L4007

CRITICALPLACE_NEAR=J4002.2:2.54MM

TCM060590-OHM-0.1A

31

42

Y4000CRITICAL

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

CAM_XTAL:YES

31 67

31 67

31 67

31 67

12 67

12 67

2

1R4005

5%

201

1/20WMF

100K

17 67

Camera 2 of 2


MIPI_DATA_N

MIPI_DATA_P

MIPI_DATA_CONN_P

MIPI_DATA_CONN_N

MIPI_CLK_N

MIPI_CLK_P

MIPI_CLK_CONN_P

MIPI_CLK_CONN_N


VOLTAGE=5V

PP5V_S3RS0_ALSCAM_F


PP0V675_MEM_CAM_VREFCA

PP0V675_MEM_CAM_VREFDQ


PP1V35_CAM

MEM_CAM_A<4>

MEM_CAM_ODT

MEM_CAM_A<3>

MEM_CAM_A<10>

MEM_CAM_A<12>

MEM_CAM_A<13>

MEM_CAM_DQS_N<1>

CAM_SENSOR_WAKE_L_CONN

PP0V675_CAM_VREF

MEM_CAM_A<5>

I2C_CAM_SDA

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP5V_S0

MEM_CAM_DQ<8>

CAM_SENSOR_WAKE_L

CLK25M_CAM_CLKNCLK25M_CAM_XTALN

PCIE_CLK100M_CAMERA_P

MEM_CAM_ZQ_DDR

MEM_CAM_RESET_L

PP1V8_CAM

MEM_CAM_A<0>

MEM_CAM_A<6>

CLK25M_CAM_XTALP_R

PCIE_CAMERA_R2D_C_P

SYSCLK_CLK25M_CAMERA

PCIE_CAMERA_R2D_P

PCIE_CAMERA_D2R_P

PCIE_CAMERA_D2R_N

PCIE_CAMERA_R2D_N

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_C_N

CLK25M_CAM_XTALP

CLK25M_CAM_CLKP

MEM_CAM_DQS_N<0>

MEM_CAM_DQ<1>

MEM_CAM_DQ<7>

MEM_CAM_DQ<4>

MEM_CAM_DQ<3>

MEM_CAM_DQ<2>

MEM_CAM_DQ<0>

MEM_CAM_DQ<11>

MEM_CAM_DQ<10>

MEM_CAM_DQ<12>

MEM_CAM_DQ<15>

MEM_CAM_DQ<14>

MEM_CAM_DQS_P<0>

MEM_CAM_DQ<5>

MEM_CAM_DQ<6>

MEM_CAM_DQS_P<1>

MEM_CAM_DQ<9>

MEM_CAM_DQ<13>

MEM_CAM_A<2>

MEM_CAM_A<1>

MEM_CAM_A<7>

MEM_CAM_A<8>

MEM_CAM_A<9>

MEM_CAM_RAS_L

MEM_CAM_CAS_L

MEM_CAM_CS_L

PCIE_CAMERA_D2R_C_N

PCIE_CLK100M_CAMERA_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_C_N

MEM_CAM_CKE

MEM_CAM_CKE_R

MEM_CAM_DM<0>

MEM_CAM_WE_L

MEM_CAM_A<11>

MEM_CAM_BA<2>

MEM_CAM_BA<1>

MEM_CAM_BA<0>

PP5V_S4RS3

MEM_CAM_CLK_P

MEM_CAM_CLK_N

I2C_CAM_SCK

MEM_CAM_A<14>

MEM_CAM_DM<1>

CAM_SENSOR_WAKE_L_CONN

<BRANCH>

<SCH_NUM>

<E4LABEL>

40 OF 120

32 OF 73

62 70

62 70

62 70

62 70

62

70

70

31 70

70

32 62

31 70

16 17 43 49 50 54 56 57 59 60 62

31

67

31

67 67

33 45 47 52 53 56 60 62

32 62

w w w

. c h

i n a

f i x

. c o

mSYM_VER-1

OUT

OUT

IN

IN

GND

SSRX-

SXRX+

GND

D+

GND

SSTX+

SSTX-

D-

VBUS

FAULT*

IN_1

IN_0

ILIM

OUT1

OUT2

EN

GNDTHRMPAD

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

BI

BI

IN

OUT

IN

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Current limit per port (R4600+R4601): 2.19A min / 2.76A max

H USB (D)

Mojo SMC Debug Mux

SEL OUTPUT

APN: 514-0819

USB Port Power Switch

Right USB Port A

L SMC (M)

2

1C46050.01UF

16V

0201

X5R-CERM

10%

4 3

21

L4600

DLP0NS

90-OHM

CRITICAL

14 66

14 66

14 66

14 66

21

C4620GND_VOID=TRUE

6.3V

CERM-X5R 0201

0.1UF

10%

21

C4621

GND_VOID=TRUE

6.3V

CERM-X5R 0201

0.1UF

10%

1

8

2

3

9

18

17

16

15

14

13

12

11

10

7

4

6

5

J4600CRITICAL

F-RT-TH

USB3.0-J11-J13

2

1

D4610

GND_VOID=TRUE

ESD0P2RF-02LSTSSLP-2-1

CRITICAL

2

1

D4620ESD0P2RF-02LS

CRITICAL

GND_VOID=TRUE

TSSLP-2-1

2

1

D4611

GND_VOID=TRUE

CRITICAL

TSSLP-2-1ESD0P2RF-02LS

2

1

D4621CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

GND_VOID=TRUE

2

1R4601

1%22.1K

1/20WMF201

9

7

6

3

2

5

1

8

4

U4600TPS2557DRB

CRITICAL

SON

1

2

9

108

5

4

3

7

6

U4650

CRITICALTQFN

PI3USB102EZLE

SIGNAL_MODEL=MOJO_MUX_SMSC

2

1C4650BYPASS=U4650.9:3:5mm

0201X5R-CERM

10V

0.1UF10%

2

1R4650

201

100K

MF1/20W5%

14 66

14 66

35 36 66

35 36 66

35

2

1

D4600CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

2

1

D4601ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

2

1C4695

0402-1

6.3V

10UF

CERM-X5R

20%

2

1 C4691

16VX5R-CERM0201

0.1UF10%

14 16

2

1C4690

0402-1

6.3VCERM-X5R

20%

10UF 2

1R4600

MF1/20W

22.1K1%

201

2

1C4696

CRITICAL

POLY-TANT

20%

CASE-B2-SM1

220UF-35MOHM

6.3V

21

L4605

CRITICAL

FERR-120-OHM-3A

0603


External A USB3 Connector

XDP_USB_EXTA_OC_L

USB_PWR_EN

USB_ILIM_R

USB3_EXTA_R2D_C_N

USB3_EXTA_R2D_C_P

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5VMIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.5 mm

USB_ILIM

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_P

SMC_DEBUGPRT_RX_L

SMC_DEBUGPRT_TX_L

USB_EXTA_P

MIN_NECK_WIDTH=0.375 mm


VOLTAGE=5V

PP5V_S3_RTUSB_A_F

USB2_EXTA_MUXED_F_P

USB2_EXTA_MUXED_F_N

USB2_EXTA_MUXED_P

USB3_EXTA_R2D_N

PP5V_S4RS3

USB_EXTA_N

PP3V42_G3H

USB2_EXTA_MUXED_N

SMC_DEBUGPRT_EN_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

46 OF 120

33 OF 73

57 59 63

66

66

66

66

66

32 45 47 52 53 56 60 62

17 30 34 35 36 38 44 46 47 48 57 59 60 62 63

66

w w w

. c h

i n a

f i x

. c o

m

IN

IN

OUT

D

SYM_VER_3

SG

OUT

IN

OUT

OUT

BI

BI

BI

BI

OUT

IN

IN

Y

A

B 08

Y

A

B 08IN

IND

SYM_VER_3

SG

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



518S0884

(TPAD_SPI_INT_S4_WAKE_L_CONN)

(TPAD_WAKE_L)

(TPAD_USB_IF_EN_CONN)

(=PP3V42_G3H_IPD)

IPD Flex Connector

From PCH

From PCH

(TPAD_SPI_IF_EN_CONN)

To SMC

To PCH

2

1C4810

10%0.1UF

PLACE_NEAR=J4800.14:1.5MM

16VX5R-CERM

0201

13 18 29 34 35 57

15

15

21

3

Q4800

PLACE_NEAR=R4842.2:5MM

DFN1006H4-3DMN32D2LFB4

TPAD_INTWAKE:SHARED

2

1C4841

10%0.1UF

0201CERM-X5R

6.3VBYPASS=U4810:3mm

29 35 37

21

R4842

PLACE_NEAR=R4843.2:1.5MM

TPAD_INTWAKE:SPLIT

MF1/20W

0201

0

5%

21

R4843

PLACE_NEAR=R4841.1:1.5MM

TPAD_INTWAKE:SHARED

MF1/20W

0201

0

5%

21

R4841PLACE_NEAR=R4844.1:1.5MM

TPAD_INTWAKE:SPLIT

MF1/20W

0201

0

5%

2

1R4844TPAD_INTWAKE:SHARED


MF1/20W

0201

05%

34 35 36 46 62

34 36 62

34 35 36 62

34 35 38 42 62 71

34 35 38 42 62 71

14 62 66

14 62 66

9

8

7

6

5

4

3

20

2

19

18

17

16

15

14

13

12

11

10

1

21

22

J4800TF13BS-20S-0.4SH

CRITICAL

F-RT-SM-1

2

1R4810

NOSTUFF

100K

MF1/20W

201

5%

21

R485033

PLACE_NEAR=J4800.2:2.54mmMF1/20W 2015%

15 66

21 R485233


15 66

21 R485133


15 66

21 R4853PLACE_NEAR=J4800.12:2.54mm

33MF1/20W 2015%

7

8

4

2

1

U4810

CRITICAL

SOT83374LVC2G08GT

3

8

4

6

5

U4810

74LVC2G08GTSOT833



15

13 18 29 34 35 57

21

3

Q4860DMN32D2LFB4DFN1006H4-3

15

2

1R4860100K

MF1/20W

201

5%

2

1C4820

10%0.1UF

0201CERM-X5R

6.3V

BYPASS=J4800.19:1.5MM

2

1C4800

10%0.1UF

0201CERM-X5R

6.3VBYPASS=J4800.10:1.5MM

2

1 C4832

25V

NOSTUFF

100PF

0201NP0-CERM


5%

2

1 C4833

25VNP0-CERM0201

BYPASS=J4800.5:1.5mm

100PF

NOSTUFF

5%

2

1 C4834

25V

100PF

0201


NP0-CERM

5%

2

1 C4835

25VNP0-CERM0201


100PF5%

2

1 C4836

25VNP0-CERM0201

100PF


5%

21

L4820

0402-LF


FERR-120-OHM-1.5A

21

R4830


MF1/20W

0201

0

5%


IPD Connector

SMC_ONOFF_L

SMBUS_SMC_3_SDA

TPAD_SPI_IF_EN_CONN

TPAD_SPI_MISO



PP3V3_S4_IPD

PP3V3_S4

TPAD_SPI_INT_L

PP5V_S5

SMC_PME_S4_WAKE_L

TPAD_SPI_MOSI

TPAD_SPI_CLK

TPAD_USB_IF_EN

TPAD_SPI_IF_EN

PM_SLP_S4_L

PM_SLP_S4_L

SMC_LID

SMBUS_SMC_3_SCL

PP3V3_S4

SMC_ONOFF_L

TPAD_SPI_INT_S4_WAKE_L_CONN

TPAD_SPI_MOSI_R

TPAD_WAKE_L

TPAD_SPI_CLK_R

USB_TPAD_N

USB_TPAD_P

SMC_LID

TPAD_SPI_MISO_R

TPAD_SPI_CS_R_L

SMC_LSOC_RST_L

PP3V3_S3

TPAD_SPI_CS_CONN_L

PP3V3_S3

PP3V3_S0

TPAD_SPI_CS_L

PP3V42_G3H

SMC_LSOC_RST_L

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

TPAD_USB_IF_EN_CONN

VOLTAGE=5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

PP5V_S4_IPD

48 OF 120

<BRANCH>

<SCH_NUM>

<E4LABEL>

34 OF 73

34 35 36 62

34 35 38 42 62 71

62

62

25 26 27 29 34 36 37 56 60 62

51 52 60

34 35 36 46 62

34 35 38 42 62 71

25 26 27 29 34 36 37 56 60 62

62

62

62

62

62

62

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

8 11 12 13 15 17 18 26 30 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

17 30 33 35 36 38 44 46 47 48 57 59 60 62 63

34 36 62

62

62

w w w

. c h

i n a

f i x

. c o

mLPC0AD3

LPC0CLK

LPC0FRAME*

LPC0AD1

LPC0AD2

AIN08

AIN07

LPC0CLKRUN*

LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX

PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119

PP4/IRQ120

C0-

WT2CCP0/PH0

WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2

SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127

PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4

PF5

T1CCP0/PJ0

T2CCP0/PJ2

T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK

SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

IN

BI

BI

BI

BI

IN

IN

IN

BI

OUT

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

NC

OUT

NC

BI

OUT

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT

BI

OUT

OUT

BI

IN

OUT

IN

IN

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SMS Interrupt can be active high or low, rename net accordingly.

(OD)

those designated as inputs require pull-ups.

pins designed as outputs can be left floating,

(OD)

(OD)

NOTE:

If SMS interrupt is not used, pull up to SMC rail.

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

NOTE:

Unused pins have "SMC_Pxx" names. Unused

(OD)

(OD) (PL7)

(PL6) H10

G4

H3

H4

J3

K4

K3

L7

K7

E12

E13

E11

F11

M1

L3

C5

D5

C8

A9

B9

C9

F3

F4

N9

M9

K10

L10

N1

L4

M3

M2

L6

M6

K5

N6

N5

F5

E4

D4

K6

D8

L5

J13

J12

M5

L12

M13

M11

N11

N12

L11

D10

G3

L13

H11

A12

C11

B12

J2

J4

K9

L9

C6

C4

L1

H13

F12

C13

F13

D12

G11

H12

D11

C12

A13

B13

N3

N4

M7

N7

K8

L8

M8

N8

N2

M4

D13

E10

L2

K1

K2

A8

B8

A7

B7

H2

H1

G1

G2

B2

B1

C2

C1

A6

B6

A5

B5

A4

B4

A3

B3

F1

F2

E1

E2

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

N10

M10

N13

D2

D1

D6

K13

J6

J1

D3

J10

J9

J7

F10

E9

E8

E6

D7

K12

B10

A11

A10

C10G10

B11

G13

G12

A2

M12

E3

C3

J11

J8

J5

H9

H5

F9

E5

D9

K11

C7

A1

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

2 1

XW5000SM

PLACE_NEAR=U5000.A1:4MM

36 44 48 62

36 67

2

1R50021M

MF

5%1/20W

2012

1 C50060.1UF

X5R-CERM0201

10V10%

2

1 C50050.1UF

0201X5R-CERM10V10%

2

1 C5009

0201

10V

0.1UF

X5R-CERM

10%

2

1 C50080.1UF

0201X5R-CERM10V10%

2

1 C50040.1UF

0201X5R-CERM10V10%

2

1 C50030.1UF

X5R-CERM0201

10V10%

2

1 C50070.1UF

0201X5R-CERM10V10%

14 62 67

14 62 67

14 62 67

14 62 67

17 67

14 62 67

18

15 62

13 62

13 62

13

38 58 71

38 58 71

14 32 38 41 42 62 67 71

14 32 38 41 42 62 67 71

38 59 63 71

38 59 63 71

34 38 42 62 71

34 38 42 62 71

62

62

38 46 48 62 71

38 46 48 62 71

37 39

37 40

37 39

37 40

37 39

37 41

37 39

37 40

37 41

37 39

37 39

37 40

37 39

37 39

37 39

37 63

37 39

37 40

37 40

37 40

37 40

37 41

37 41

29 36 37 39 62

36 52 57

13

17 26 27 36

36

33 36 66

33 36 66

62

44 67

44 67

44 67

44 67

33

62

16 17 57

36

13 16

13 17 62

13 36

15

36

36

36 62

36 62

62

62

37

54

43

43

62

29 34 37

34 36 46 62

36

36 48 59 63

13 18

13 17 18 57

13 18 29 34 57

13 57

34 36 62

25 36

36 57

13 27

29 36 62

62

37

36

37

52 57

17

21

L5001

0402

30-OHM-1.7A

6 36 49 65

30

62

30

59 63

13 16 17

6 65

36

37 40 56

2

1 C5016


10V

0201X5R-CERM

0.1UF10%

2

1 C5015


10V10%0.1UF

0201X5R-CERM 2

1 C5013

PLACE_NEAR=U5000.J1:5MM

10%0.1UF

0201

10VX5R-CERM2

1 C5010

0201-1X5R6.3V20%1.0UF

PLACE_NEAR=U5000.D6:5MM

2

1 C5001

X5R-CERM

0.1UF

0201

10V10%

2

1 C5002

0201

6.3V

1UF20%

X5R

36

41

62

2

1 C5021

20%1UF

0201X5R6.3V

BYPASS=U5000.D2:D1:1MM

2

1 C5020

10VX5R-CERM0201

0.01UF10%

BYPASS=U5000.D2:D1:1MM

62

2

1 C5011


0.1UF10%

0201

10VX5R-CERM2

1 C5012

X5R-CERM10V

0201

0.1UF10%


2

1 C5014

0201-1X5R6.3V20%1.0UF


2

1 C5017

0201-1X5R6.3V

1.0UF20%

PLACE_NEAR=U5000.D6:5MM

36 37

29 37

36

36

30 62

37

SMC


SMC_BIL_BUTTON_L

LPC_PWRDWN_L

SMBUS_SMC_0_S0_SCL

SMC_SENSOR_ALERT_L

S5_PWRGD

PM_PWRBTN_L

PM_DSW_PWRGD

SYS_ONEWIRE

SMC_S5_PWRGD_VIN

SMC_VCCIO_CPU_DIV2

SMC_DEBUGPRT_TX_L

SMC_DEBUGPRT_RX_L

SMC_PROCHOT

SMC_DELAYED_PWRGD

SMC_PM_G2_EN

SMC_CPU_DBGPWR_RD_L

SMC_OOB1_D2R_L

SMC_ADAPTER_EN

NC_SMC_T25_EN_L

SMC_SYS_KBDLED

NC_SMC_FAN_1_CTL

SMC_FAN_0_TACH

SMC_FAN_0_CTL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

NC_SMBUS_SMC_4_ASF_SDA

PM_SLP_S4_L

PM_SLP_S3_L

SMC_CPU_VSENSE

NC_SMC_FAN_5_CTL

SMC_S4_WAKESRC_EN

SMC_PME_S4_DARK_L

SMC_OOB1_R2D_L

SMC_PCH_SUSACK_L

SPI_SMC_MOSI

SMC_CPUVR_ADJUST_ISENSE

PP3V3_WLAN

SMC_SENSOR_PWR_EN

ALL_SYS_PWRGD

SMC_THRMTRIP

SMC_OTHER_HI_ISENSE

SMC_DCIN_VSENSE

LPC_AD<3>

NC_SMC_GFX_OVERTEMP

MEM_EVENT_L

PM_SYSRST_L

NC_BDV_BKL_PWM

PM_BATLOW_L

CPU_THRMTRIP_3V3

NC_SMC_GFX_THROTTLE_L

CPU_CATERR_L

NC_SMC_SYS_LED

SPI_SMC_MISO

SPI_SMC_CLK

SPI_DESCRIPTOR_OVERRIDE_L

PM_SLP_S5_L

SMBUS_SMC_1_S0_SCL

PM_CLKRUN_L

LPC_AD<1>

LPC_CLK24M_SMC

LPC_FRAME_L

SMBUS_SMC_0_S0_SDA

SMC_CPU_ISENSE PP3V42_G3H

PP1V2_S5_SMC_VDDCMIN_LINE_WIDTH=0.25MMMIN_NECK_WIDTH=0.1MMVOLTAGE=1.2V

SMC_LCDBKLT_ISENSE

SMC_P1V05S0_VSENSE

SMC_P3V3S0_ISENSE

SMC_SSD_ISENSE

SMC_WLAN_ISENSE

SMC_1V2S3_ISENSE

SMC_PANEL_ISENSE

SMC_DCIN_ISENSE

SMC_BMON_ISENSE

SMC_TMS

SMC_TCK

SMC_DEBUGPRT_EN_L

SMC_RUNTIME_SCI_L

NC_SMC_XOSC1

SMBUS_SMC_3_SCL

SMBUS_SMC_1_S0_SDA

SMC_CPUDDR_ISENSE

SMC_PBUS_VSENSE

SMC_CPU_IMON_ISENSE

SMC_P3V3S5_ISENSE

SMC_XTAL

WIFI_EVENT_L

SMC_WAKE_L

LPC_AD<2>

SMC_BMON_DISCRETE_ISENSE

NC_SMC_HIB_L

SMC_RESET_L

SMC_TDI

SMC_TDO

SPI_SMC_CS_L

CPU_PROCHOT_L

LPC_AD<0>

LPC_SERIRQ

SMC_HS_COMPUTING_ISENSE

SMC_WAKE_SCI_L

SMC_CLK32K

SMC_P1V05S0_ISENSE

SMC_EXTAL

SMC_LRESET_L

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

PP3V3_S5_SMC_VDDAMIN_LINE_WIDTH=0.25MM

VOLTAGE=3.3VMIN_NECK_WIDTH=0.1MM

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_2_S3_SCL

SMC_CAMERA_ISENSE

NC_SMC_ADC16

NC_SMC_FAN_1_TACH

SMC_TOPBLK_SWP_L

SMBUS_SMC_3_SDA

NC_SMBUS_SMC_4_ASF_SCL

SMC_BC_ACOK

SMC_LID

CPU_PECI_R

SMC_PECI_L

SMC_PME_S4_WAKE_L

SMS_INT_L

SMC_TX_L

SMC_PWRFAIL_WARN_L

TP_SMC_5VSW_PWR_EN

NC_SMC_DP_HPD_L

PM_SLP_S0_L

SMC_ONOFF_L

SMC_RX_L

SMC_WIFI_PWR_EN

PM_PCH_SYS_PWROK

SMC_PCH_SUSWARN_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

50 OF 120

35 OF 73

17 30 33 34 36 38 44 46 47 48 57 59 60 62 63

36 44 62

36 44 62

36

36 62

36 62

36

36 39 40 41

36

w w w

. c h

i n a

f i x

. c o

mIN

OUT

BI

IN

IN

IN OUT

IN OUT

OUT

IN

BIOUT

IN

OUT

SYM_VER_2

G S

D

NCNC IN

SN0903049

PAD

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

VER 3

D

S G

VER 3

D

S G

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SMC Reset "Button", Supervisor & AVREF Supply

Mobiles: 3.42V

Desktops: 5V

Module has 3.3K PU

(IPU)

(IPU)

SMC Crystal Circuit

Debug Power "Buttons"

Used on mobiles to support SMC reset via keyboard.

MR1* and MR2* must both be low to cause manual reset.

values:5,6,8,10,12,16,18,20,24,25 MHz

To SMC

SMC12 PECI Support

From SMC

From/To CPU/PCH

SMC USB Clock require these crystal

NOTE: Internal pull-ups are to VIN, not V+.

21R51705% 2011/20W MF

10K

21R51715% 2011/20W MF

100K

21R51735% 2011/20W MF

10K

21R51745% 2011/20W MF

100K

21R51775% 2011/20W MF

10K

21R51785% 2011/20W MF

10K

21R51795% 2011/20W MF

10K

21R51805% 2011/20W MF

10K

35 36

15 36 65

2

1R5115

5%0

SILK_PART=PWR_BTN

OMIT

603

PLACE_SIDE=TOP

1/10WMF-LF

6 35 49 65

35

21R51895% 2011/20W MF

10KNO STUFF

21R51815% 2011/20W MF

10K

21

R5110

201

1/20WMF

1%

2.49K

2

1 C5111

5%

0201NP0-C0G-CERM25V

12PF

21R51875% 2011/20W MF

100K

21R51925% 2011/20W MF

100K

2

1R5116

5%0PLACE_SIDE=BOTTOM

OMIT

MF-LF603

1/10W

SILK_PART=PWR_BTN

2

1R5101

5%0

SILK_PART=SMC_RST

1/10W

PLACE_SIDE=BOTTOM

603MF-LF

OMIT

34 35 36 62

34 62

2

1C5101

0201

10%10V

0.01UF

X5R-CERM

2

1C5120

CERM-X5R6.3V10%

402

0.47UF

2

1 C5126

0201

10VX5R-CERM

0.01UF10%

2

1R5100

5%

201

1/20WMF

100K

35 44 48 62

13 67 21

R5112

5% 2011/20W MFPLACE_NEAR=U0500.AE6:5.1mm

2235 67

21R51905% 2011/20W MF

100K

21R51755% 2011/20W MF

20K

21R51765% 2011/20W MF

20K

21R51865% 2011/20W MF

10K

2

1 C5110

5%12PF

25VNP0-C0G-CERM0201

2

1R5197

201

1/20WMF

100K1%

2

1R5196

201

1/20WMF

1%100K

21R51935% 2011/20W MF

10K

34 35 36 62

35

2

1R5153

5%

201

1/20WMF

NOSTUFF

1.6K

21

R5152

5%

0

0201

1/20WMF

2

1R5151

5%

201

1/20WMF

330

21R51145% 2011/20W MF

10K NO STUFF

21R51175% 2011/20W MF

100K

21R51675% 2011/20W MF

100K

6 65

35 21

R5134

5%

201

1/20W

MF

43

15 36 65

2

3

1Q5158

DFN1006-3

CRITICAL

MMBT3904LP-7

35 36

2

1C512510UF

X5R-CERM

20%10V

0402-1

21

R5158

5%

201

1/20WMF

3.3K

21R51915% 2011/20W MF

100K

31

42

Y5110

CRITICAL

12.000MHZ-30PPM-10PF-85C3.2X2.5MM-SM

21

3Q5150DMN32D2LFB4

DFN1006H4-3

CRITICAL

2

1 C5127NOSTUFF

4.7UF

6.3V

402

20%

X5R

21

R5127

5%

0

MF-LF1/16W

402

21R51725% 2011/20W MF

10K

25 35 36

2

1 C5134

5%

PLACE_NEAR=Q5150.2:5MM

NOSTUFF

47PF

0201NP0-C0G-CERM25V

2

1C5131

5%

0201NP0-C0G-CERM

PLACE_NEAR=Q5159.6:5MM

25V

47PF

31

9

5

8

7

6

2

4

U5110VREF-3.3V-VDET-3.0V

DFN

CRITICAL

21R5198 100KMF1/20W 2015%

12

6 Q5159

SOT563

DMN5L06VK-7

45

3 Q5159DMN5L06VK-7

SOT563

21R51855% 2011/20W MF

100K


SMC Shared Support


SMC_PROCHOT

CPU_PROCHOT_L

SMC_THRMTRIP

PM_THRMTRIP_L

SMC_BC_ACOK

PM_THRMTRIP_L

SMC_PECI_L

CPU_PECI_R

PP1V05_S0

SMC_PME_S4_DARK_L

SMC_ONOFF_L

PP1V05_S0

SMC_PECI_L_R

SMC_CLK32K

CPU_THRMTRIP_3V3

CPU_PECI

PM_THRMTRIP_R_L

SMC_XTAL

MAKE_BASE=TRUESMC_PME_S4_DARK_L

PM_CLK32K_SUSCLK_R

MAKE_BASE=TRUESMC_BC_ACOK

SMC_EXTAL

GND_SMC_AVSS

PP3V42_G3H

VOLTAGE=3.42V

PP3V42_G3H_SMC_SPVSR


SMC_ONOFF_L

SMC_MANUAL_RST_L

SMC_RESET_L

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSS

MIN_NECK_WIDTH=0.1 mmVOLTAGE=0V

SMC_LSOC_RST_L

PP3V3_S5_AVREF_SMCMIN_LINE_WIDTH=0.4 mm


WIFI_EVENT_L

PP3V42_G3H

SMC_PME_S4_DARK_L

SMC_ONOFF_L

SMC_SENSOR_ALERT_L

SMC_LID

SMC_TX_L

SMC_RX_L

SMC_DEBUGPRT_TX_L

CPU_THRMTRIP_3V3

MEM_EVENT_L

PP3V3_S4

PP3V3_WLAN

SMC_BC_ACOK

SMS_INT_L

SMC_TCK

SMC_S5_PWRGD_VIN

SMC_BIL_BUTTON_L

SMC_TDO

SMC_VCCIO_CPU_DIV2

SMC_TMS

SMC_S4_WAKESRC_EN

SMC_DELAYED_PWRGD

SMC_PM_G2_EN

SMC_TDI

SMC_DEBUGPRT_RX_L

SMC_XTAL_R

PP3V42_G3H

PP3V3_S0

SMC_THRMTRIP

SMC_ADAPTER_EN

<BRANCH>

<SCH_NUM>

<E4LABEL>

51 OF 120

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6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53

56 57 60 62

35

25 35 36

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35

35 36 39 40 41

17 30 33 34 35 36

38 44 46

47 48 57

59 60 62

63

35 36 39 40 41

35

29 35 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

25 35 36

34 35 36 62

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34 35 46 62

35 62

35 62

33 35 66

35 36

35

25 26 27 29 34 37 56 60 62

29 35 37 39 62

35 36 48 59 63

35

35 44 62

35

35

35 62

35

35 44 62

35 57

17 26 27 35

35 52 57

35 62

33 35 66

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

8 11 12 13 15 17 18 26 30 34 37 38 39 40 41 42 43 54 57 59

60 62 63 72

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IN

IN

OUT

OUT

IN

IN

IN

OUTIN

IN

IN

IN

IN

OUT

IN OUT

INOUT

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SD alias on page 103

Top-Block Swap

29 34 35 37

29 34 35 37

2

1R5282100K

MF1/20W

201

5%

29 34 35 37

35 36

42

42 21

R5212100

MF1/20W

201

5%

21

R5211NOSTUFF

100

MF1/20W

201

5%

21

R5210100

MF1/20W

201

5%

59 63

21

R52831K

MF1/20W

201

5%

15 35

21R5294 10K NOSTUFFMF1/20W 2015%

21

R5213100

MF1/20W

201

5%

41

21

R5214100

MF1/20W

201

5%

42

21

R5215NOSTUFF

100

MF1/20W

201

5%

14 18

2

1R52961K

MF1/20W

201

5%

21R5295 NOSTUFF10KMF1/20W 2015%

21

R5216100

MF1/20W

201

5%

41

35 63

35 13

13 35

21

R5230

MF1/20W

0201

0

5%

21

R5231

MF1/20W

0201

0

5%


SMC Project Support

TBTMLBSNS_ALERT_L SMC_SENSOR_ALERT_L

CPUTHMSNS_ALERT_L

SMC_HS_COMP_ALERT_L

PCH_SML1ALERT_L

SMC_CPUVR_ADJUST_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_CPU_IMON_ISENSE

PP3V3_WLANMAKE_BASE=TRUE

SMC_P3V3S5_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_CPU_VSENSE

SMC_P1V05S0_VSENSEMAKE_BASE=TRUE

SMC_CAMERA_ISENSEMAKE_BASE=TRUE

SMC_1V2S3_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_PANEL_ISENSE

MAKE_BASE=TRUESMC_LCDBKLT_ISENSE

MAKE_BASE=TRUESMC_WLAN_ISENSE

MAKE_BASE=TRUESMC_SSD_ISENSE

SMC_DCIN_VSENSE


SMC_WIFI_PWR_EN

PP3V3_S4

SMC_SENSOR_PWR_EN

MAKE_BASE=TRUETP_SMC_5VSW_PWR_EN TP_SMC_5VSW_PWR_EN

SMC_P1V05S0_ISENSE

SMC_P1V05S0_VSENSE

PP3V3_S0

SMC_TOPBLK_SWP_L

SMC_PBUS_VSENSE

SMC_BMON_ISENSE

SMC_CPU_ISENSE

SMC_P3V3S0_ISENSE

SMC_1V2S3_ISENSE

SMC_CPUDDR_ISENSEMAKE_BASE=TRUE

SMC_BMON_DISCRETE_ISENSEMAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUESMC_P1V05S0_ISENSE

MAKE_BASE=TRUESMC_OTHER_HI_ISENSE

SMC_DCIN_ISENSE

CPUBMONSNS_ALERT_L

PP3V3_WLAN

SMC_PME_S4_WAKE_LMAKE_BASE=TRUE

SMC_HS_COMPUTING_ISENSE


SMC_CPU_IMON_ISENSE

SMC_DCIN_ISENSEMAKE_BASE=TRUE

SMC_CPU_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_BMON_ISENSE

SMC_PBUS_VSENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_HS_COMPUTING_ISENSE

PP3V3_S4

SMC_PME_S4_WAKE_L

SMC_PME_S4_WAKE_L

PCH_STRP_TOPBLK_SWP_L

SMC_SENSOR_PWR_EN

MAKE_BASE=TRUESMC_DCIN_VSENSE

SMC_PANEL_ISENSE

SMC_WLAN_ISENSE

FINSTACKSNS_ALERT_L

SMC_SENSOR_PWR_ENMAKE_BASE=TRUE

SMC_BMON_COMP_ALERT_L

SMC_P3V3S0_ISENSEMAKE_BASE=TRUE

SMC_CAMERA_ISENSE

NC_SMC_ADC16

SMC_WIFI_PWR_ENMAKE_BASE=TRUE

SMC_WIFI_PWR_EN

SMC_CPUDDR_ISENSE

SMC_SSD_ISENSE

SMC_P3V3S5_ISENSE

SMC_LCDBKLT_ISENSE

SMC_CPU_VSENSE

SMC_SENSOR_PWR_EN

SMC_PCH_SUSWARN_LMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_PCH_SUSACK_L

PCH_SUSWARN_L

PCH_SUSACK_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

52 OF 120

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35 37 40

35 37 40

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35 37 39

35 37 39

35 37 39

35 37 40

35 37 41

29 35 37

25 26 27 29 34 36 37 56 60 62

35 37 40 56

35 37 35 37

35 37 40

35 37 40

8 11 12 13 15 17 18 26 30 34 36 38 39 40 41 42 43 54 57 59 60

62 63 72

35 37 40

35 37 39

35 37 40

35 37 39

35 37 39

35 37 40

35 37 41

35 37 39

35 37 40

35 37 39

35 37 39

29 35 36 37 39 62

35 37 39

35 37 41

35 37 41

35 37 39

35 37 40

35 37 39

35 37 40

35 37 39

25 26 27 29 34 36 37 56 60 62

35 37 40 56

35 37 40

35 37 41

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35 37 40 56

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35 37 39

29 35 37 29 35 37

35 37 40

35 37 39

35 37 40

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(Write: 0x30 Read: 0x31)

ISL6259 - U7100

SMC "5" SMBus G3H Connections

SMC "3" SMBus S0 Connections

Battery Charger


SMC

XDP Connectors

(Write: 0x72 Read 0x73)

J4002

ALS

U5000

(MASTER)

SMC


PAC1921: U5620

EMC1704-02: U5800

CPU Temp, Inlet, DDR, BMON THR

J4800



VRef DACs

connector page and

gated by EDP_PANEL_PWR

J43 J41

(See Table)

Pullups are on eDP

J6950

(See Table)

TBT & MLBBOT, TBD Temp

EMC1414: U5810

LYNX POINT LP S0 "SMLink 0" Connections

LYNX POINT LP S0 "SMLink 1" Connections

U0500

U0500

LYNX POINT LP

LYNX POINT LP

J1800

U0500

LYNX POINT LP

(MASTER)


Battery Manager - (Write: 0x16 Read: 0x17)


U5000


Battery

J9500

U2800

U5000

(MASTER)

U5000

(MASTER)

(MASTER)

U5000

SMC

U2201

U2200

Trackpad

J8300

TBT

SMC

(MASTER)

Margin Control

(MASTER)

(Write: 0xFE Read: 0XFF)

LIO Finstack Temp


SMC

(MASTER)


access PCH

SMLink 1 is slave port to

U7701

(Write: 0x92 Read 0x93)

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

(Write: 0x58 Read: 0X59)

LCD BACKLIGHT

LYNX POINT LP S0 SMBus "0" Connections

Battery

Internal DP

Samsung LGD Samsung LGD AUO

(* = Multiple options)

Chipset current

Internal DP

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

SMC S0 "1" SMBus Connections

2

1R5361

201

2.0K5%

MF1/20W

2

1R5360

201

2.0K

MF

5%1/20W

2

1R5380

5%

201MF

1/20W

2.0K

2

1R5381

MF1/20W5%2.0K

201

2

1R53701K

1/20WMF

201

5%

2

1R53711K5%

201

1/20WMF

2

1R53108.2K

5%1/20W

MF201

2

1R5311

5%1/20W

8.2K

MF201

2

1R5301

5%1/20W

201MF

1K

2

1R5300

5%1K

MF1/20W

201

2

1R5391

1/20W

2.0K5%

MF201

2

1R53902.0K

1/20W

201MF

5%

SYNC_MASTER=J43_MLB

SMBus Connections


SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_DATA

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

SMBUS_PCH_CLK

SMBUS_PCH_DATA

PP3V3_S0

SMBUS_PCH_CLK

SMBUS_PCH_CLK

SMBUS_PCH_DATA

PP3V3_S0

MAKE_BASE=TRUE

SML_PCH_0_CLK

MAKE_BASE=TRUE

SML_PCH_0_DATA

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_3_SCL

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

PP3V3_S3

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCLSMBUS_PCH_CLK

MAKE_BASE=TRUE

PP3V3_S0

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_S0

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

PP3V42_G3H

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

<BRANCH>

<SCH_NUM>

<E4LABEL>

53 OF 120

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35 38 59 63 71

14 32 35 38 41 42

62 67 71

14 32 35 38 41 42

62 67 71

35 38 58 71

35 38 58 71

14 16 19 38 54 67

14 16 19 38 54 67

14 16 19 38 54 67

14 16 19 38 54 67

34 35 38 42 62 71

34 35 38 42 62 71

34 35 38 42 62 71

34 35 38 42 62 71

14 16 19 38 54 67

14 16 19 38 54 67

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

14 16 19 38 54 67

14 16 19 38 54 67

14 16 19 38 54 67

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

14 67

14 67

35 38 46 48 62 71

35 38 46 48 62 71

35 38 59 63 71

34 35 38 42 62 71

14 16 19 38 54 67

14 16 19 38 54 67

35 38 59 63 71

35 38 46 48 62 71

35 38 46 48 62 71

15 18 19 34 39 56 60 62 63

35 38 58 71

35 38 58 71

14 16 19 38 54 67

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

34 35 38 42 62 71

14 32 35 38 41 42 62 67 71

14 32 35 38 41 42 62 67 71

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

14 32 35 38 41 42

62 67 71

14 32 35 38 41 42 62 67

71

14 32 35 38 41 42 62

67 71

17 30 33 34 35 36 44 46 47 48 57 59 60 62 63

35 38 46 48 62 71

35 38 46 48 62 71

14 32 35 38 41 42 62 67

71

14 32 35 38 41 42

62 67 71

14 32 35 38 41 42 62 67

71

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OUT OUTIN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

V+

REFIN+

IN- OUT

GNDIN

OUT

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

OUT

V+

REFIN+

IN- OUT

GND

OUT

V+

REFIN+

IN- OUT

GND

OUTIN-

IN+ REF

V+

GND

OUTIN-

IN+ REF

V+

GND

V+

REFIN+

IN- OUT

GND

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EDP Current :12A

GAIN : 100X

IC0R : COMPUTING High Side Current Sense

MAX Vdiff : 0.06 mV

IBLC : LCD Backlight Driver Input Current Sense

(For R and C)

MAX Vdiff : 16.36 mV

GAIN : 200X

IS2C : 3.3V Camera Current Sense

IR0C : 3.3V S0 FET Current Sense

DC-IN (AMON) Current Sense

Max VOut: 1.4V at 8.25A

GAIN : 1000X

EDP Current :1.02A

MAX Vdiff : 3.06 mV

EDP Current : 0.82A

IO0R : OTHER High Side Current Sense

GAIN : 50X


(500V/V)

(200V/V)

(100V/V)

APN: 107S0137

(50V/V)

(1000V/V)

PLACEMENT_NOTEs:

(200V/V)

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

(For R and C)

Scale: 2.5A / V

CHARGER BMON High Side Current Sense

Replacing caps with 100K PD on ISENSE SMC inputs

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

(For R and C)

PLACEMENT_NOTEs:

(200V/V)

PLACEMENT_NOTEs:

(For R and C)

(100V/V)

APN: 104S0024

IAPC :AirPort Current Sense

MAX Vdiff : 24 mV

EDP Current :10.75A

IM3C :DDR 1V2 Current Sense (LPDDR + CPUDDR)

EDP Current : 7.57A


ISDC : SSD Current Sense

EDP Current : 1.00A

MAX Vdiff : 25 mV

GAIN : 100X

EDP Current : 3.00A

GAIN : 200X

MAX Vdiff : 15 mV

EDP Current : 0.67A

GAIN : 500X

GAIN : 200X

EDP Current: 3.5A

Sense R is R7120, 20mOhm

ISL6259 Gain: 20x

ISL6259 Gain: 36x

Scale: 2.78A / V


EDP Current: 310A

SENSE R : R7450 0.002R

35 37 35 37

2

1 C5431

10%

PLACE_NEAR=U5000.B3:11MM

2.2NF

10V

0201

X5R-CERM

21

R5431

201


45.3K

1%

MF

1/20W

48

35 37

35 37

35 37

35 37

2

1 C5465

Place close to SMC

X5R6.3V

PLACE_NEAR=U5000.A5:11mm

DRAM_ISNS:YES

20%0.22UF

0201

21

R5465

DRAM_ISNS:YES


Place close to SMC

201

4.53K

1%

MF1/20W

2

1 C5460

DRAM_ISNS:YES

10%0.1UF

0201

CERM-X5R6.3V

51 72

51 72

2

1 C5475

PLACE_NEAR=U5000.C1:11mm

AIRPORT_ISNS:YES

Place close to SMC

X5R

6.3V

0.22UF20%

0201

21

R5475


AIRPORT_ISNS:YES

Place close to SMC

201

4.53K

1%1/20W

MF

2

1 C5485

SSD_ISNS:YES

Place close to SMC0201

0.22UF20%


6.3V

X5R

21

R5485


SSD_ISNS:YES

Place close to SMC

201

1/20W1%

4.53K

MF

2

1 C5470

10%

0.1UF

0201CERM-X5R

6.3V

AIRPORT_ISNS:YES

2

1 C5495

PLACE_NEAR=U5000.B6:11mm

LCDBKLT_ISNS:YES

Place close to SMC

0.22UF20%

0201

6.3V

X5R

21

R5495


LCDBKLT_ISNS:YES

Place close to SMC

1%

4.53K

1/20W

MF201

2

1 C5490

LCDBKLT_ISNS:YES

6.3V

CERM-X5R0201

0.1UF10%

21

R5422

201


1/20W

MF

1%

300K

2

1 C5422

10%

0201

10V

X7R-CERM

3300PF


35 37

2

1 C5455

Place close to SMC

X5R

6.3V

PLACE_NEAR=U5000.E2:11mm

0201

CPU_HS_ISNS:YES0.22UF20%

21

R5455

201


1%

MF

4.53K

CPU_HS_ISNS:YES

1/20W

2

1 C5450

10%

0.1UF

0201CERM-X5R6.3V

CPU_HS_ISNS:YES

2

1 C5480SSD_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

35 37

2

1 C5433

OTHER_HS_ISNS:YES0201

20%0.22UF


6.3VX5R

Place close to SMC

21

R5433

201


4.53K

MF

1%

1/20W

Place close to SMC

OTHER_HS_ISNS:YES

2

1 C5430

CERM-X5R

10%

0.1UF

0201

6.3V

OTHER_HS_ISNS:YES

3

1

6

4

5

2

U5430

OTHER_HS_ISNS:YES

PLACE_NEAR=R5430:5mm

INA213

CRITICAL

SC70

27 39 40 47

48 54

60 62

52 60 62

48

3

1

6

4

5

2

U5460


DRAM_ISNS:YES

CRITICAL

SC70INA210

4

3

2

1R5450

0612

1%0.002

MF1W

CRITICAL

4

3

2

1R5480

0612MF1W1%

0.003

CRITICAL

OMIT_TABLE

3

1

6

4

5

2

U5480

SSD_ISNS:YES


SC70

INA210

CRITICAL

35 37

2

1 C5445

Place close to SMC

X5R6.3V


0.22UF20%

0201

3V3S0_ISNS:YES

21

R5445

Place close to SMC

201

1/20WMF

1%

4.53K

3V3S0_ISNS:YES


2

1 C5440

10%

0201CERM-X5R6.3V

0.1UF

3V3S0_ISNS:YES

3

1

6

4

5

2

U5440

SC70

INA212

CRITICAL


3V3S0_ISNS:YES

35 37 21

R5425

Place close to SMC

201

CAM_ISNS:YES


1/20W

4.53K

MF

1%

2

1 C5425

Place close to SMC

CAM_ISNS:YES

20%

0201

0.22UF PLACE_NEAR=U5000.B2:11mm

6.3V

X5R

2

1 C5420

6.3VCERM-X5R0201

10%

CAM_ISNS:YES

0.1UF

3

1

6

4

5

2

U5490


LCDBKLT_ISNS:YES

SC70

INA211

CRITICAL

21

R5421

402

5%

MF-LF

0

1/16W

21

R5423NOSTUFF

402

5%

MF-LF1/16W

0

4

3

2

1

R5470CRITICAL

0612

0.025

1WMTL

1%

3

1

6

4

5

2

U5450

SC70INA214

CPU_HS_ISNS:YES

CRITICAL

3

1

6

4

5

2

U5470


AIRPORT_ISNS:YES

CRITICAL

SC70INA214

3

1

6

4

5

2

U5420

CRITICAL

SC70

INA210


CAM_ISNS:YES

2

1R545120K

201MF

1/20W5%

2

1R5432

201

5%1/20W

MF

20K

2

1R5461

201

5%1/20W

MF

20K

2

1R5471

201

5%1/20W

MF

20K

2

1R548120K

MF1/20W

5%

201

2

1R549120K

5%1/20W

MF201

2

1R5441

201

5%1/20W

MF

20K

2

1R542420K

5%1/20W

MF201

4

3

2

1R5430

0612-SHORT

0.0031%1w

CYN

OMIT

4

3

2

1R5440

0612-SHORTCYN1w1%

0.003

OMIT

4

3

2

1R5420

0612-SHORT

0.0200.5%1wMF

OMIT

4

3

2

1R5490

0612-SHORT

OMIT

MF1w

0.5%0.020

1 C5475 AIRPORT_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD117S0008

117S0008 1 C5485 SSD_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD

1117S0008 C5495 LCDBKLT_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD

3V3S0_ISNS:NO117S0008 1 C5445RES,MF,1/20W,100K OHM,5,0201,SMD

C54251117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD CAM_ISNS:NO

C54331117S0008 OTHER_HS_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD

107S0248 CRITICALRES,SENSE,0.003OHM,1W,4-TERM,1%,0612,TFT R54801

117S0008 DRAM_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD1 C5465

CPU_HS_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD117S0008 1 C5455

SYNC_MASTER=SID_J41 SYNC_DATE=02/26/2013

High Side Current Sensing

ISNS_AIRPORT_N

ISNS_AIRPORT_P

ISNS_P5VWLAN_IOUT SMC_WLAN_ISENSE

PP3V3_S4SW_SNS

PP3V3_WLAN

PP3V3_WLAN_R

GND_SMC_AVSS

ISNS_1V2_S3_P

ISNS_1V2_S3_N ISNS_1V2_IOUT SMC_1V2S3_ISENSE

PP3V3_S4SW_SNS

GND_SMC_AVSS

PP3V3_S4SW_SNS

ISNS_LCDBKLT_IOUT

SMC_SSD_ISENSEISNS_P5VSSD_IOUT

PP3V3_S0SW_SSD

PP3V3_S0SW_SSD_FET_R

CHGR_BMON SMC_BMON_ISENSE CHGR_AMON SMC_DCIN_ISENSE

GND_SMC_AVSS

SMC_CAMERA_ISENSEISNS_CAMERA_IOUT

GND_SMC_AVSS

SMC_OTHER_HI_ISENSE

PP3V3_S3

PP3V3_S0

PP3V3_S3RS0_CAMERA

GND_SMC_AVSS

GND_SMC_AVSS

SMC_P3V3S0_ISENSE

PP3V3_S0

ISNS_HS_COMPUTING_N

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_IOUT SMC_HS_COMPUTING_ISENSE

PPBUS_S5_HS_COMPUTING_ISNS

GND_SMC_AVSS

ISNS_SSD_P

GND_SMC_AVSS

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

VOLTAGE=8.6V


PPVIN_S0SW_LCDBKLT_FET

ISNS_SSD_N


PPVIN_S0SW_LCDBKLT



ISNS_HS_OTHER_N

ISNS_HS_OTHER_P

PPBUS_G3H

PP3V3_S4SW_SNS

HS_OTHER_IOUT

ISNS_P3V3_S0_IOUT

PP3V3_S4SW_SNS

PPBUS_G3H

GND_SMC_AVSS

PPBUS_S5_HS_OTHER_ISNS

ISNS_P3V3_S0_N

PP3V3_S0

ISNS_P3V3_S0_P

PP3V3_S4SW_SNS



PP3V3_S3RS0_CAMERA


ISNS_CAMERA_N

ISNS_CAMERA_P

PP3V3_S3RS0_CAMERA



VOLTAGE=3.3V

PP3V3_S3RS0_CAMERA_R

PP3V3_S0_FET_R

PP3V3_S4SW_SNS


PPVIN_S0SW_LCDBKLT

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

<BRANCH>

<SCH_NUM>

<E4LABEL>

54 OF 120

39 OF 73

72

72

39 40 41 56 60

29 35 36 37 62

29

35 36 39 40 41

39 40 41 56 60

35 36 39 40 41

39 40 41 56 60

30 60 62

56

35 36 39 40 41

35 36 39 40 41

15 18 19 34

38 56

60 62

63

15 31

39

35 36 39 40 41

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

41 72

41 72

41

49 50 51 53

60 62

35 36 39 40 41

72

35 36 39 40 41

35 36 39 40 41

39 54

72

39 54

72

72

27 39 40 47

48 54

60 62

39 40 41 56 60

39 40 41 56 60

35 36 39 40 41

72

8 11 12 13 15 17 18 26 30 34 36 37

38 39 40 41 42 43

54 57 59 60 62 63

72

72

39 40 41 56 60

15 31

39

72

72

15 31

39

56

39 40 41 56 60

39 54

39 54

72

72

w w w

. c h

i n a

f i x

. c o

m

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUTIN

IN

V+

REFIN+

IN- OUT

GND

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

IN

V-

V++

-

OUT

IN

IN

OUT

V+

REFIN+

IN- OUT

GND

OUT

IN

OUTIN-

IN+ REF

V+

GND

OUT

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL Apple Inc.


124578

B

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C

B

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PAGE

12

D

A

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



IR5C :3.3 S5 REG Current Sense


(100V/V)


EDP Current : 3.00A

GAIN : 100X

1.05V Voltage Sense / Filter

CPU Vcore Voltage Sense / Filter

RTHEVENIN = 4573 Ohms

Max VOut: 3.3V at 19.77V Input

Enables DC-In VSense

divider when SUS present.

VD0R: DC-In Voltage Sense Enable & Filter

Max VOut: 3.3V at 19.77V Input

IC1C: 1.05V S0 CURRENT SENSE / FILTER

RTHEVENIN = 4573 Ohms

(200V/V)

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

Sense R is 0.75mOhm each, combined 0.375mOhm

EDP: 32A TDP :28.05A

Sense R is R7310, R7320

Gain:274.72x

EDP Current : 1A

MAX Vdiff : 5.65 mV

GAIN : 500X

(500V/V)

ICS0 : CPU VCore Load Side Current Sense

GAIN : 200X

VP0R: PBUS Voltage Sense Enable & Filter

IM0C : CPU DDR Current SenseEDP Current : 3.00A


35 37

56

2

1R5502

MF

1%100K

1/20W

201

2

1R5501

1/20W

100K1%

MF201

35 37

2

1 C5504

20%0.22UF

0201

6.3VX5R

PLACE_NEAR=U5000.E1:11MM

2

1R5503

1%

MF1/20W

27.4K

201PLACE_NEAR=U5000.E1:11MM

2

1R55045.49K

1/20W1%

MF201


4

1

5

2

3

6

Q5500

SOT-963NTUD3169CZ

35 37 21

R5561

PLACE_NEAR=U5000.H2:11MM

P1V05_ISNS:YES

201

1/20WMF

1%

4.53K

2

1 C5561P1V05_ISNS:YES

X5R6.3V20%0.22UF

0201

PLACE_NEAR=U5000.H2:11MM

2

1 C5560P1V05_ISNS:YES

10%0.1UF

0201CERM-X5R6.3V

53 72

53 72

3

1

6

4

5

2

U5560

SC70


P1V05_ISNS:YES



CRITICAL

INA211

21

R5548

201

1/20W

4.53K

MF

1%

CPUVR_ISNS:YESPLACE_NEAR=U5000.B4:11MM

35 37

2

1 C5541

X5R6.3V

CPUVR_ISNS:YES

0.22UF20%

0201


2

1 C5540

10%0.1UF

0201CERM-X5R6.3V

CPUVR_ISNS:YES

PLACE_NEAR=U5540.5:3MM

50 72

35 37

2

1R551327.4K

1/20WMF

1%

PLACE_NEAR=U5000.B3:11MM201

2

1 C55140.22UF

0201


6.3VX5R

20%

2

1R5514

1/20W

5.49K

MF

1%

201

PLACE_NEAR=U5000.F1:11MM

2

1R5512

MF

100K1%

201

1/20W

4

1

5

2

3

6

Q5510NTUD3169CZ

SOT-963

2

1R5511

100K

1/20W

1%

MF201

13 57

5

2

4

3

1

U5540

SC70-5

OPA333DCKG4

CRITICAL

CPUVR_ISNS:YES

35 37

2

1 C5595

0201

0.22UF20%

Place close to SMC

6.3VX5R


P3V3S5_ISNS:YES

21

R5595

Place close to SMC

1/20WMF

1%

4.53K

201

P3V3S5_ISNS:YES


2

1 C5590

P3V3S5_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

50 72

50 72

21

R5540

402

1%

4.42K

MF-LF

CPUVR_ISNS:YES

1/16W


21

R5541

402

1%

4.42K

MF-LF

CPUVR_ISNS:YES

1/16W


21

R5542

CPUVR_ISNS:YES

402MF-LF1/16W

4.42K

1%


21

R5543

CPUVR_ISNS:YES

402

1/16W

4.42K

1%

MF-LF


21

R5545

MF-LF402

1.43K

1%

CPUVR_ISNS:YES

1/16W

21

R5544

402

1.43K

MF-LF

1%1/16W

CPUVR_ISNS:YES

21

R5547

402

1M

CPUVR_ISNS:YES

MF-LF1/16W1%


2

1R5546CPUVR_ISNS:YES

MF-LF

1%1/16W

1M

402

35 37

2

1 C5575

Place close to SMC

CPUDDR_ISNS:YES

0.22UF20%

0201

6.3VX5R

PLACE_NEAR=U5000.H1:11mm

21

R5575

1/20W

Place close to SMC

MF

1%

4.53K

201

CPUDDR_ISNS:YES

PLACE_NEAR=U5000.H1:11mm

2

1 C5570

CPUDDR_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

3

1

6

4

5

2

U5570INA210

CPUDDR_ISNS:YES

SC70


35 37

2

1 C55300.22UF20%

0201

6.3VX5R

PLACE_NEAR=U5000.G1:11MM

21

R5530

1%

4.53K

MF1/20W

201

PLACE_NEAR=U5000.G1:11MM

21

XW5530SM

PLACE_NEAR=R7640.2:5 MM

50 72

3

1

6

4

5

2

U5590INA214

SC70

CRITICAL


P3V3S5_ISNS:YES

2

1R5571

MF1/20W

5%20K

201

2

1R5591

MF

5%20K

201

1/20W

2

1R5562

201

20K

MF1/20W

5%

4

3

2

1R5570OMIT

0612-SHORTCYN1w1%

0.003

4

3

2

1R5590

0612-SHORT

OMIT

CYN1w1%

0.003

35 37 21

R5520

1/20W1%

MF

4.53K

201


2

1 C5520

0201

0.22UF20%6.3VX5R


21

XW5520

PLACE_NEAR=R7310.2:5 MM

SM

RES,MF,1/20W,100K OHM,5,0201,SMD CPUVR_ISNS:NO117S0008 1 C5541

1117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD C5595 P3V3S5_ISNS:NO

SYNC_DATE=02/26/2013SYNC_MASTER=SID_J41

Voltage & Load Side Current Sensing

RES,MF,1/20W,100K OHM,5,0201,SMD P1V05_ISNS:NO117S0008 1 C5561

C5575RES,MF,1/20W,100K OHM,5,0201,SMD CPUDDR_ISNS:NO1117S0008

PPVMEMIO_S0_CPU

ISNS_P3V3S5_N

ISNS_P3V3S5_P

PBUS_S0_VSENSE

PBUSVSENS_EN_L


MAKE_BASE=TRUE


PPVMEMIO_S0_CPU

VOLTAGE=1.2V

PP3V3_S4SW_SNS

ISNS_1V05_S0_N

ISNS_1V05_S0_P

P1V05S0_IOUT SMC_P1V05S0_ISENSE

GND_SMC_AVSS

PP3V3_S4SW_SNS

MAKE_BASE=TRUE

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20MM

PP3V3_S5_REG_RMIN_LINE_WIDTH=0.5 MM

ISNS_P3V3S5_IOUT

ISNS_CPUDDR_IOUT

SMC_P3V3S5_ISENSE

SMC_CPUDDR_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

CPUVR_ISUM_R_NCPUVR_ISNS1_N_R

CPUVR_ISUM_R_P

CPUVR_ISNS1_P_R

CPUVR_ISNS2_N

CPUVR_ISNS1_N

CPUVR_ISNS2_P

CPUVR_ISNS1_P

PPDCIN_G3H_ISOL

SMC_SENSOR_PWR_EN

GND_SMC_AVSS

PBUSVSENS_EN_L_DIV

PPBUS_G3H

SMC_PBUS_VSENSE

PM_SLP_SUS_L

DCIN_S5_VSENSE

PDCINVSENS_EN_L_DIV

SMC_DCIN_VSENSE

P1V05VSENSE_INPP1V05_S0

CPUVSENSE_INPPVCC_S0_CPU

SMC_P1V05S0_VSENSE

SMC_CPU_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

PP3V3_S0

SMC_CPU_ISENSE

GND_SMC_AVSS

CPUVR_ISUM_IOUT

GND_SMC_AVSS

DCINVSENS_EN_L

PP3V3_S4SW_SNS

ISNS_CPUDDR_N

ISNS_CPUDDR_P

PP1V2_S3

PP3V3_S5

PP3V3_S5_REG_R

<BRANCH>

<SCH_NUM>

<E4LABEL>

55 OF 120

40 OF 73

8 10 40

72

72

8 10 40

39 40 41 56 60

35 36 39 40 41

39 40 41 56 60

40 52 35 36 39 40 41

35 36 39 40 41

72 41 72

72

41 72

47 48

60

62

35 36 39 40 41

27 39 47 48 54 60 62

6 8 11 15 16 17

36 49 53

56 57 60

62

8 10 50 60

62

35 36 39 40 41

35 36 39 40 41

8 11 12 13 15 17 18 26 30 34 36 37 38 39 41 42 43 54 57 59

60 62 63 72

35 36 39 40 41

35 36 39 40 41

39 40 41 56 60

72

72

17 19 20 21 22 23 51 60 68

8 11 13 15 16 17 18 28 29 52 55 56 57 58 60 62 72

40 52

w w w

. c h

i n a

f i x

. c o

m

SYM_VER_2

G S

D

IN

OUT

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

IN

IN

OUT

V+

REFIN+

IN- OUT

GND

OUT

SYM_VER_2

G S

D

IN

BI

IN

IN

BI

IN

IN

IN

OUT

OUT

OUT

VDD

SENSE-

ADDR_SEL/GAIN_SEL

SENSE+

EPADGND

SM_DATA/OUT_SEL

SM_CLK/INT_SEL

COMM_SEL

OUT

READ*/INT

OUT

OUTIN

Apple Inc.


124578

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




ICS3 : Adjustable Gain CPU VR Current

PU: SMBus mode

(500V/V)

GAIN: 500X

In battery discharge scenario negative voltage will be

Sense Pins gain stage for U5800 (EMC1704)

With 100mA battery current, Will have 10.2mV differencegoing into sense pins of U5800.This will set the minumum current threshold at 0.100mAfrom 3.3V with increasing discharge current.


CHGR_CSO_R_P/N are swapped on purpose


Gain: 50x

Scale: 0.25A / V

Vref = 0.406mV Vth = 0.442 = 1A from Battery

Vtl = 0.290mv = 0.687A from battery

(50V/V)

VR IMON Current Sense Filter

to measure power into the system

PLACEMENT_NOTEs:

(For R and C)

Hysteresis TBD based on RC value changes

R5821: ADDR - 0x56/0x57 (r/w)

present on IN+/- pins with INA output voltage decreasing

BMON : Discrete BMON Current Sense / Filter

Scale: 2A / V

MAX VOUT: 3V AT 0.825AEDP Current: 0.750 A

Max Vdiff: 15 mV

Gain: 200x

(200V/V)

ILDC :LCD Panel Current Sense / Filter

Discrete High side Current threshold

2

5

1

4

3

U5601

SC70-5MCP6541T

21

3U5602

DFN1006H4-3

DMN32D2LFB4

40 72

37

21

R5609200K

MF-LF1/16W1%

40221

R560610.2K

1%1/16WMF-LF402

2

1R5604

MF-LF1/16W1%100K

402

2

1R5605

MF-LF1/16W1%100K

402

21

C5601

20%

0201

0.22UF

NO STUFF

6.3VX5R

40 72

2

1 C5603BYPASS=U5601:3MM

0.1UF10%

0201CERM-X5R6.3V

2

1R56214.3K

MF1/20W

201

5%

3

1

6

4

5

2

U5600CKPLUS_WAIVE=NdifPr_badTerm

SC70INA213

CKPLUS_WAIVE=NdifPr_badTerm

CRITICAL

2

1R5600

MF1/20W

0201

05%

2

1 C5600

NOSTUFF

X5R

0.1UF10%25V

402

K

A

D5607SM-201

NOSTUFF

RB521ZS-30

2

1R5607

NOSTUFF

MF1/20W

0201

05%

3

1

6

4

5

2

U5660

PLACE_NEAR=R7150:5MM



INA211SC70

CRITICAL

48 71

48 71

2

1 C5670PANEL_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

21

R5675

201

1/20W

Place close to SMC

4.53K

PANEL_ISNS:YES

1%


MF

2

1 C5675

X5R


0201

Place close to SMC

20%0.22UF

PANEL_ISNS:YES

6.3V

35 37

3

1

6

4

5

2

U5670

CRITICAL


PANEL_ISNS:YES

INA210SC70

37

21

3U5612DMN32D2LFB4

DFN1006H4-3

21

C5611

20%

0201

0.22UF

NO STUFF

6.3VX5R

21

R5619

MF-LF1/16W1%

255K

402

2

5

1

4

3

U5611MCP6541TSC70-5

21

R5616

MF-LF1/16W1%

10.2K

402

2

1 C5610

X5R

0.1UF10%25V

402

NOSTUFF

2

1 C5613BYPASS=U5601:3MM

6.3VCERM-X5R0201

0.1UF10%

2

1R5610

MF1/20W

0201

05%

2

1R5617

NOSTUFF

MF1/20W

0201

05%

2

1R5614

MF-LF

1%1/16W

294K

402

2

1R5615

1%

MF-LF

49.9K

1/16W

402

K

A

D5617SM-201

RB521ZS-30

NOSTUFF

39

21

R5668

MF1/20W

0201

0

5%

21

R5669NO STUFF

MF1/20W

0201

0

5%

21

R5667NO STUFF

MF1/20W

0201

0

5%

21

R5666

MF1/20W

0201

0

5%

14 32 35 38 42 62 67 71

39 41

72

39 41

72

2

1R5671

201

20K

MF1/20W

5%

2

1R560120K

MF1/20W

201

5%

2

1R566320K

MF1/20W

201

5%

4

3

2

1R5670OMIT

MF1w

0.5%0.020

0612-SHORT

14 32 35 38 42 62 67 71

2

1 C5665

20%

0201

6.3VX5R

NO STUFF

0.22UF

2

1 C5660


6.3V

0.1UF10%

CERM-X5R

0201

35

39 41 72

39 41 72

21

R5665

MF1/20W

0201

0

5%

2

1R5662

1%1K

MF1/20W

201

2

1R5661

1%27K

MF1/20W

201

42 72

42 72 21

R5660

MF

1/20W

0201

0

5%

35 37

2

1C5606BYPASS=U5600:3MM

6.3V

0.1UF10%

CERM-X5R0201

2

1 C5602

0201

0.22UF


20%6.3VX5R

21

R56084.53K

1%


MF1/20W

201

1

11

9

10

2

3

8

4

5

7

6

U5620

DFN

PAC1921-1-AIA


35 37 21

R5625PLACE_NEAR=U5000.A7:5MM

MF1/20W

0201

0

5%

2

1 C5625

NO STUFF

0201

20%0.22UF


6.3VX5R

2

1 C5620

BYPASS=U5620.1:5:3MM

1.0UF20%6.3VX5R0201-1

21

R5620

MF-LF1/16W

100

1%

402

35 37

2

1 C5641

2.2NF

0201

X5R-CERM

10V


NO STUFF

10%

49 21

R5641


MF1/20W

0201

0

5%

RES,MF,1/20W,100K OHM,5,0201,SMD117S0008 1 PANEL_ISNS:NOC5675

Debug Sensors 1

SYNC_MASTER=SID_J41 SYNC_DATE=02/26/2013

PP3V3_S0SW_LCD_R

PP3V3_S0SW_LCD_R



ISNS_PANEL_P

PP3V3_S0

PP3V3_S4SW_SNS

PP3V3_S0SW_LCD

VOLTAGE=3.3V

MAKE_BASE=TRUE


PP3V3_S0SW_LCD

ISNS_PANEL_N

BMON_COMP_OUT

ISNS_HS_COMPUTING_IOUT

HS_IOUT_R

CPUVRSNS_ADDR_SEL

PP3V3_SNS_CPUVR_ADJUST_ISNS



PP3V3_S4SW_SNS

SMC_CPUVR_ADJUST_ISENSE_R

PP3V3_S0 ISNS_HS_GAIN_P

ISNS_HS_COMPUTING_P

GND_SMC_AVSS

SMBUS_SMC_1_S0_SCL

CPUVR_IMON

HS_COMP_OUT

HS_COMP_FB

HS_IOUT_D

HS_COMP_VREF

SMC_BMON_COMP_ALERT_L


GND_SMC_AVSS

SMC_PANEL_ISENSE

GND_SMC_AVSS

CHGR_CSO_R_N

CHGR_CSO_R_P

SMC_CPU_IMON_ISENSE

GND_SMC_AVSS

SMC_CPU_DBGPWR_RD_L

SMBUS_SMC_1_S0_SDA


CPUVR_ISNS1_P_R

ISNS_HS_GAIN_N_R

ISNS_PANEL_IOUT

ISNS_HS_GAIN_OUT

BMON_COMP_VREF

BMON_IOUT_R

BMON_IOUT

BMON_IOUT_D

BMON_COMP_FB

PP3V3_S0

CPUVR_ISNS1_N_R

ISNS_HS_GAIN_N

SMC_HS_COMP_ALERT_L

ISNS_HS_COMPUTING_N

ISNS_HS_GAIN_OUT_R

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

ISNS_HS_GAIN_P_R

<BRANCH>

<SCH_NUM>

<E4LABEL>

56 OF 120

41 OF 73

41 58

41 58

72

8 11 12 13

15 17

18 26

30 34

36 37

38 39

40 41

42 43

54 57

59 60

62 63

72

39 40 41 56 60

41 58

41 58

72

39 40 41 56 60

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

35 36 39 40 41

35 36

39

40

41

35 36 39 40 41

35 36 39 40 41

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

w w w

. c h

i n a

f i x

. c o

mDUR_SEL

DP1

VDD

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

GPIO

THRM_PADGND

TH_SEL

SENSE-

SENSE+

DN2/DP3

DP2/DN3

DN1

BI

BI

OUT

OUT

OUT

BI

BI

ALERT*

THERM*/ADDRDP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3GND

BI

BI

OUT

BI

BI

NC

OUT

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6 3



Detect DDR/5V/3.3V Proximity Temperature

Placement note:

Place Q5830 between near rear vent on bottom side

Place Q5810 next to DDR/5V/3.3V supply on TOP side

Read Address: 0x99

Placement note:

Place Q5840 on MLB bottom side opposite U5810

Place Q5820 close to TBT on TOP side

Placement note:

Placement note:

TBD

Write Address: 0x39

Read Address: 0x38

TBT,MLB Bottom Proximity Sensors

Placement note:

TBT, MLBBOT and TBD Temp Sensor

Write Address: 0x98

Place U5800 under CPU

Placement note:

CPU Proximity, Inlet ,DDR and BMON THR Sensor

21

R5840

MF1/20W

0201

0

5%

21

R5841

MF1/20W

0201

0

5%

2

3

1Q5810BC846BLPDFN1006H4-3

2

3

1Q5820

DFN1006H4-3BC846BLP

2

3


2

3

1Q5840

DFN1006H4-3BC846BLP

1

17

9

14

11

12

16

157

8

13

4

2

5

3 10

6

U5800EMC1704-2

QFN

CRITICAL

2

1 C58000.1UF10%6.3V

CERM-X5R0201

21

R580047

MF

1/20W

201

5%

14 32 35 38 41 62 67 71

14 32 35 38 41 62 67 71

2

1C5801

10%

PLACE_NEAR=U5800.2:5mm

PLACE_NEAR=U5800.3:5mm10V

X7R-CERM

0201

2200PF


2

1C5802

10%

X7R-CERMPLACE_NEAR=U5800.5:5mm

0201

10V

NO_XNET_CONNECTION=TRUEPLACE_NEAR=U5800.4:5mm

2200PF

2

1R5805

MF1/20W

0201

05%

37

41 72

41 72

34 35 38 62 71

34 35 38 62 71

2

1 C5810

10%0.1UF

0201

CERM-X5R6.3V

1

7

9

10

6

4

2

5

3 8

U5810

CRITICAL

EMC1414-1-AIZLMSOP

21

R581047

MF1/20W

201

5%

2

1C5812

10%PLACE_NEAR=U5810.4:5mm

PLACE_NEAR=U5810.5:5mm 0201X7R-CERM

10V


2200PF

42 72

42 72

37

2

1R5803

NOSTUFF

10K

MF1/20W

201

5%

2

1R5804

NOSTUFF

10K

MF1/20W

201

5%

2

3


2

1C5813

10%10V

2200PF


X7R-CERM

0201

42 72

42 72

2

1R5802100K

NOSTUFF

MF1/20W

201

5%

2

1R5811

22K

MF1/20W

201

5%

2

3

1Q5860

BC846BLP

DFN1006H4-3

2

1R5806100K

MF1/20W

201

5%

37

2

1 C5830

25V

PLACE_NEAR=Q5830:3MM

NP0-C0G-CERM

47PF

0201

5%

2

1 C5811

25V


NP0-C0G-CERM

47PF

0201

5%

2

1C5860

25V


NP0-C0G-CERM

47PF

0201

5%

2

1 C5820

25V


NP0-C0G-CERM

47PF

0201

5%

2

1 C5840

25V


NP0-C0G-CERM

47PF

0201

5%

2

1 C5850

25V


NP0-C0G-CERM

47PF

0201

5%SYNC_DATE=02/20/2013

Thermal Sensors

SYNC_MASTER=J43_MLB

CPUBMONSNS_ALERT_L

CPUTHMSNS_ALERT_L

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_S0_CPUTHMSNS_R

VOLTAGE=3.3V



CPUTHMSNS_ADDR_SEL

INLET_THMSNS_D1_P

CPUTHMSNS_DUR_SEL

ISNS_HS_GAIN_N

TBDTHMSNS_D2_N

CPUTHMSNS_D2_N

CPUTHMSNS_TH_SEL

PP3V3_S0

PP3V3_S0

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

TBTMLBSNS_ALERT_L

TBT_INLET_THM_L

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

PP3V3_S0_TBTMLB_ISNS_R

MIN_NECK_WIDTH=0.20 mmVOLTAGE=3.3V


TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_NMAKE_BASE=TRUE

MAKE_BASE=TRUE

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

ISNS_HS_GAIN_P

TBTTHMSNS_D2_R_P

TBTTHMSNS_D2_R_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBDTHMSNS_D2_N

TBDTHMSNS_D2_P

INLET_THMSNS_D1_N

CPUTHMSNS_D2_P

TBDTHMSNS_D2_P

<BRANCH>

<SCH_NUM>

<E4LABEL>

58 OF 120

42 OF 73

72

72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

42 72

42 72

42 72

42 72

42 72

42 72

42 72

42 72

72

72

42 72

42 72

42 72

42 72

72

72

w w w

. c h

i n a

f i x

. c o

m

D

SYM_VER_3

SG

NC

NC

OUT

IN

NC

08

NC

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6 3



MOTOR CONTROL

FAN CONNECTOR

TACH

5V DC

GND

518S0793

21

R606547K

MF1/20W

201

5%

2

1R6060

47K

MF1/20W

201

5%

2

1R6061

100K

MF1/20W

201

5%

4

3

2

1

6

5

J6000CRITICAL

FF14A-4C-R11DL-B-3HF-RT-SM

21

3

Q6060DFN1006H4-3DMN32D2LFB4

35

35

4

6

53

1

2

U6010

NOSTUFFCRITICAL

SOT89174LVC1G08

2

1 C6010

10%0.1UF

0201CERM-X5R6.3V

NOSTUFF

BYPASS=U6010:3mm

21

R6010

MF1/20W

0201

0

5%


Fan

PP3V3_S0

PP5V_S0

FAN_RT_PWM

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

PP3V3_S0_FAN

VOLTAGE=3.3VMIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.2 MM

<BRANCH>

<SCH_NUM>

<E4LABEL>

60 OF 120

43 OF 73

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 54 57 59 60

62 63 72

16 17 32 49 50 54 56 57 59 60 62

62

62

w w w

. c h

i n a

f i x

. c o

mBI

BI

OUTOUT

VCC

D

B

A Y

OE*C

GND

CS*

DI(IO0)

THRM_PAD

CLK

WP*(IO2)

HOLD*(IO3)

DO(IO1)

VCC

GND

OUT

OUT

BI

BI

OUT

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

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SAM Card ROM Slave

SPI Bus Series Termination

CPU Master

SMC12 Master

MLB ROM Slave

(SWDIO)

(SWCLK)

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

SPI ROMQuad-IO Mode (Mode 0 & 3) supported.

in normal and Dual-IO modes.

IO2

IO3

SPI+SWD SAM ConnectorSPI Frequency: 50MHz for CPU, 20MHz for SMC.

IO1

IO0

ROM will ignore SPI cycles

NOTE: If HOLD* is asserted

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

35 36 62

15 44 62

35 36 62

9

8 7

6 5

4 3

2

16 15

14 13

12 11

10

1

J6100

SAMCONN

CRITICAL

DF40PC-12DP-0.4V-51M-ST-SM

35 36 48 62

2

1C6100

0201

BYPASS=U6100::3mm

10%16V

X5R-CERM

0.1UF2

1 C6101

0201

16V10%

BYPASS=U6101::3mm

0.1UF

X5R-CERM

78

1

4

6

5

3

2

U610174LVC1G99

CRITICAL

SOT833PLACE_NEAR=U6100.1:12MM

3

8

9

7

4

2

5

1

6

U6100

CRITICAL

W25Q64FVZPIG64MBITWSON

OMIT_TABLE

44 67

44 67

44

44

21

R6120


1/20W

201MF

43

5%

2

1R6125


201MF

43

1/20W5%

SAMCONN

2

1R6126


1/20W5%

201MF

43

SAMCONN

2

1R6127435%1/20WMF201


SAMCONN

2

1R6128

201MF1/20W1%24.9


SAMCONN

21

R6110

5%

15

MF201

1/20W

PLACE_NEAR=U0500.Y7:5mm

21

R6121


1/20W5%

MF

43

201

21

R6116

1/20W5%

MF

15

201


21

R6122

1/20W5%


201

43

MF

21

R612324.9

1%PLACE_NEAR=U6100.2:5mm

MF201

1/20W

21

R6115

1/20W

15

MF

5%

201


21

R6114

1/20W

201

24.9

1%

MF


21

R6117


1/20W

15

5%

MF201

21

R611215

MF201

5%1/20W

PLACE_NEAR=U0500.AA2:5mm

21

R6111

201

15

MF

5%1/20W


21

R611315

MF

5%1/20W


201

35 67

35 67

35 67

35 67

14 67

14 67

14 67

14 67

21

R6118

PLACE_NEAR=U0500.Y6:5mm

15

MF201

5%1/20W

21

R6119

PLACE_NEAR=U0500.AF1:5mm

15

MF

5%1/20W

201

14 67

14 67

21

R6130

1/20W5%

201

43

MF

PLACE_NEAR=R6132.2:5mm44 67

44 67

2

1R6132


SAMCONN

201MF1/20W5%43

21

R6131

MF

43

201

5%1/20W


2

1R6133


435%1/20WMF201

SAMCONN

BOM_COST_GROUP=CPU SUPPORT

SPI Debug Connector

SYNC_DATE=01/09/2013SYNC_MASTER=YHARTANTO_J44

SPI_MLB_CS_L

PP3V3_SUS

SPI_MLB_CLK

SPI_MLBROM_CS_L

SPI_MLB_IO2_WP_L

SPI_MLB_IO3_HOLD_L

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISOSPIROM_USE_MLB

SPI_MLB_CS_LSPI_ALT_IO3_HOLD_L

SPI_ALT_IO1_MISO

SPI_ALT_IO0_MOSI

SPIROM_USE_MLB

SPI_ALT_CS_L

SPI_ALT_CLK

PP3V42_G3H

SMC_RESET_L

SPI_ALT_IO2_WP_L

SMC_TMS

SMC_TCK

SPI_ALT_CS_L

SPI_ALT_IO0_MOSI

SPI_ALT_CLK

SPI_ALT_IO1_MISO

SPI_MLB_CLK

SPI_SMC_MISO

SPI_SMC_MOSI

SPI_SMC_CLK

SPI_SMC_CS_L

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_L

SPI_CS0_L

SPI_CLK

SPI_CS0_R_L

SPI_CLK_R

SPI_MOSI_R

SPI_MISO

SPI_IO<2>

SPI_IO<3>

SPI_MOSI

SPI_MISO_R

SPI_IO2_R

SPI_ALT_IO2_WP_L

SPI_MLB_IO3_HOLD_LSPI_IO3_R

SPI_ALT_IO3_HOLD_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

61 OF 120

44 OF 73

8 11 14 18 55 56 57 60 62

44 67

44 67

44 67

44

44 15 44 62

44 67 44 62

44 62

44 62

44 62

44 62

17 30 33 34 35 36 38 46 47 48 57 59 60 62 63

44 62

44 62

44 62

44 62

44 62

67

67

67

67

67

44 62

67

44 62

w w w

. c h

i n a

f i x

. c o

mIN

IN

IN

IN-

IN+ OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

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6 3




ALIAS OF PP5VRT_S0, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.20MM

518S0519

SPEAKER AMPLIFIERS

80 HZ < FC < 132 HZ

APN:353S2888

GAIN 6DB

Right Speaker Connector

SPEAKER LOWPASS

21

C6410

0201

10%16V

0.1UF

OMIT_TABLE

CRITICAL

X5R-CERM

59 63 72

59 63

59 63 72

C2

A1

A2

B1

C1

B2

A3

B3

C3

U6410

CRITICAL

MAX98300WLP

2

1R6412

201

100K

1/20W

5%

MF

21

C6411

0201X5R-CERM

10%16V

CRITICALOMIT_TABLE

0.1UF

2

1R6411

1/20W

201

5%

MF

100K

2

1R6413

5%

100K

NOSTUFF

MF

201

1/20W

21

R6414

603

1/10W

0

MF-LF

5%

2

1 C6407

X5R-CERM16V

0201

10%0.1UF

2

1 C6401CRITICAL

POLY-TANT

20%47UF

6.3V

0805-LLP

2

1

4

3

J6404

CRITICAL

M-RT-SM78171-0002

132S0460 2 C6410,C6411 CRITICALCAP,CER,X5R,0.1UF,10%,16V,0201,MURATA

Audio: Speaker Amp




VOLTAGE=5V

PP5V_S3_U6210

SPKRAMP_INR_N

R_AMP_GAIN

MAX98300_R_P



SPKRAMP_ROUT_P

SPKRAMP_ROUT_N



SPKRAMP_SHDN_L

MAX98300_R_N

PP5V_S4RS3

SPKRAMP_INR_P

<BRANCH>

<SCH_NUM>

<E4LABEL>

64 OF 120

45 OF 73

72 62 72

62 72 72

32 33 47 52 53 56 60 62

w w w

. c h

i n a

f i x

. c o

m

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

NEG

POS

POS

NEG

NEG

SYS_DETECT

SDA

SCL

POS

BI

IN

NC

NC

NC

NC

OUT

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6 3



Hall Effect Sensor

Battery Connector

518-0369

11"-Specific

9

8

7

6

5

4

3

2

1

13

12

11

10

J6950

F-RT-THBAT-K99

CRITICAL

2

1C6951

16V10%

402X5R

1UF

2

1 C6950

X5R25V10%

402

0.1UF

2

1R6950

1/20W5%

201MF

10K

21

3

D6950

SC-75

RCLAMP2402B

NO STUFF

CRITICAL

35 38 48 62 71

35 38 48 62 71

2

1C6955

0402

10%

X7R-CERM50V

0.001UF

21

R6961

1/16W5%

402MF-LF

0

8

7

6

5 4

3

2

1

J6955

OMIT_TABLE

SMHALL-SENSOR-MLB-PADS-K99

34 35 36 62

Battery Connector & Hall Effect


SMC_LID_R

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SYS_DETECT_L

PPVBAT_G3H_CONN

SMC_LID

PP3V42_G3H

<BRANCH>

<SCH_NUM>

<E4LABEL>

69 OF 120

46 OF 73

63

62

48 62

17 30 33 34 35 36 38 44 47 48 57 59 60 62 63

w w w

. c h

i n a

f i x

. c o

m

NC

G

D

S

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

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6 3



3.425V "G3Hot" SupplySupply needs to guarantee 3.31V delivered to SMC VRef generator

6.8V Zener

300mA Max Output

for detection of B121 (16.5V)

Input impedance of 68K meets

sparkitecture requirements

(Switcher limit)

518S0508

Vout = 1.25V * (1 + Ra / Rb)

<Rb>

<Ra>

Vout = 3.425V

MLB to LIO Power Cable Connector

6

5

4

3

2

1

J7000CRITICAL

WTB-PWR-M82M-RT-SM

21

L7095CRITICAL

10UH-20%-0.85A-0.46OHM

2520

2

1C7094

10%

CERM

0.22UF

10V

402

3

2

1

D7005

CRITICAL

BAT30CWFILMSOT-32321

R70064.7

805MF-LF1/8W5%

21

R7005

1/8W

805

10

MF-LF

5%

2

1R7095

1%348K

MF1/20W

201

2

1R7096200K

1%

MF1/20W

201

2

1R7010100K

MF1/20W

201

5%

5A

5

4

1

Q7010SI5419DU

POWERPAK

CRITICAL

K

A

D7012GDZT2R6.8

CRITICAL

GDZ-0201

2

1C7005NO STUFF

0.1UF

603-1X7R50V10%

2

1 C70060.1UF

0201X5R-CERM16V10%

2

1C7091

X5R

1UF

CRITICAL

10%25V

402

2

1 C7090CRITICAL

X5R

1UF10%25V

402

2

1 C7092CRITICAL

20%5.6UF

POLY-TANTCASE-B2-SM

25V

2

1C7099

10V

0402-1X5R-CERM

20%10UF

CRITICAL

2

1 C7098

10V

0402-1X5R-CERM

20%10UF

CRITICAL

2

1 C7008

NO STUFFCRITICAL

1UF

603X5R35V10%

2

1C7007CRITICAL

NO STUFF

1UF

603X5R35V10%

2

1 C7095

50V

22PF

NP0-C0G-CERM0201

5%

21

R7011

1%

10K

MF1/20W

201

6

9

48

7

5

1

3

2

U7090

CRITICAL

DFNLT3470AED

2

1R701268K1%

MF1/20W

201

2

1R7080

MF1/20W

0201

05%

2

1R70811%

NO STUFF

49.9K

MF1/20W

201

2

1C7080NO STUFF

1000PF

0402CERM25V5%

2

1C7012CRITICAL

10%25VX7R0402

0.047UF

DC-In & G3H Supply


P3V42G3H_SHDN_L

PP3V42_G3H

PP5V_S4RS3

PPDCIN_G3H_ISOL

PPBUS_G3H

DCIN_ISOL_GATE

P3V42G3H_FBMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

VOLTAGE=18.5V

PP18V5_DCIN_ISOL_RMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM


PPBUS_G3H_RMIN_LINE_WIDTH=0.4 mm


P3V42G3H_SW


P3V42G3H_BOOSTDIDT=TRUEMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

VOLTAGE=18.5V


PPVIN_G3H_P3V42G3H

PPDCIN_G3H

DCIN_ISOL_GATE_R

<BRANCH>

<SCH_NUM>

<E4LABEL>

70 OF 120

47 OF 73

17 30 33 34 35 36 38 44 46 48 57 59 60 62 63

32 33 45 52 53 56

60 62

40 48 60 62

27 39 40 48 54 60 62

48 60 62

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

BI

OUT

IN

S

G

D

IN

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N

GG

SDS D

NCNCNCNC

Apple Inc.


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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(CHGR_CSO_P)

(GND)

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

Max Current = 8A

ACIN pin threshold is 3.2V, +/- 50mV

DIVIDER SETS ACIN THRESHOLD AT 13.55V

Float CELL for 1S

Reverse-Current Protection

(CHGR_AGATE)

Inrush Limiter

FROM ADAPTER

(AGND)

(OD)

36V/V

20V/V

Vout = 1.25V * (1 + Ra / Rb)

(Switcher limit)

.

(PPVBAT_G3H_CHGR_R)

<Ra>

<Rb>

Vout = 5.50V200MA MAX OUTPUT

For Erp Lot6 spec

5.5v "G3Hot" Supply

(CHGR_DCIN)

TO/FROM BATTERY

Need to stuff R7192 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!

TO SYSTEM

(CHGR_BGATE)

(CHGR_SGATE)

* R7151 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

f = 400 kHz

30mA max load

2

1R711146.4K1%

MF1/20W

201

2

1 C7142

6.3V

CERM-X5R

0201

0.1UF10%

2

1 C7116470PF

16V

0201

X5R-X7R-CERM

10%

2

1C7115470PF

X5R-X7R-CERM

16V

0201

10%

2

1 C71021UF

10V

X5R

10%

402

2

1 C71001UF

402-1

10V

X5R

10%

21

R7101

MF-LF

4.7

1/16W

402

5%

2

1R7110130K1%

MF1/20W

201

21

XW7100


SM

2

1C71011UF

10V

X5R

10%

402

2

1 C7121

X5R

0.1UF10%

25V

402

2

1C7122

X5R

0.1UF10%

25V

402

2

1 C71200.047UF

16V

X7R-CERM

0402

10%

2

1 C7125PLACE_NEAR=U7100.25:2mm

CERM

10V

0.22UF10%

402

21

R712210

MF

1/20W

201

5%

21

R712110

MF

1/20W

201

5%

2

1

C7130

CASE-D3L

POLY-TANT

CRITICAL

25V

20%

33UF-0.06OHM

2

1

C713133UF-0.06OHM

POLY-TANT

CRITICAL

CASE-D3L

25V

20%

21

F71408AMP-24V

1206

CRITICAL

2

1

R7186332K

1%

MF

1/20W

201

2

1

R718162K

MF

1/20W

201

5%

2

1C71050.22UF

X5R-CERM

50V

10%

0603-1

39

39

35 38 46 62 71

35 38 46 62 71

2

1C7111

10V

X5R-CERM

0201

0.01UF10%

2

1 C71500.47UF

10V

0402

X5R

10%

2

1C7126

X7R-CERM

0201

16V

10%

1000PF

35 36 59 63

2

1 C7137

BYPASS=Q7130:1.5mm

0.001UF

X7R-CERM

0402

50V

10%

2

1 C7145

BYPASS=L7130:Q7130:1.5mm

0201

16V

10%

1000PF

X7R-CERM

2

1

R7102100K

NO STUFF

MF

1/20W

201

5%

57

32

1

4

5

Q7155

SI7137DPSO-8

CRITICAL

2

1

R7113100

MF

1/20W

201

5%

3

2

1

D7105

SOT-323

CRITICAL

BAT30CWFILM

2

1C71850.1UF

10%

25V

402

X5R

2

1

R7180100K

MF

1/20W

201

5%

2

1

R7185470K1%

MF

1/20W

201

2

1 C71351UF

603-1

X5R

10%

25V2

1 C71361UF

603-1

X5R

10%

25V

21

R7100

MF

1/20W

0201

0

5%

35 36 44 62

2

1 C7114

603-1

1UF

X5R

10%

25V2

1 C7113

X5R

0.1UF10%

25V

402

2

1 C71120.01UF

X7R

10%

25V

402

2

1C7117

805

10UF

X5R

10%

25V

21R7151 2.2

MF1/20W201 5%

21R7152MF1/20W 0201

0

5%

2

1R7115

1%255K

MF1/20W

201

2

1R7116

1%10K

MF1/20W

201

2

1C7140

CASE-B2S

20%

TANT-POLY11V

62UF-0.023OHM

2

1C7143

62UF-0.023OHM

11V

20%

CASE-B2S

TANT-POLY2

1C7141

11VTANT-POLY

20%

62UF-0.023OHM

CASE-B2S

21

L7130CRITICAL

4.7UH-17A

PIMC104T4R7MN-SM

21

R7105

PP5V5_DCIN:NO

MF-LF603

20

5%1/10W

2

1 C7199

603

10UF

CRITICAL

10V

NO STUFF

X5R

20%

2

1 C7198

X5R

NO STUFF

603

10V

10UF

CRITICAL

20%

2

1

R7195

NO STUFF

1%

681K

MF

1/20W

201

2

1

R7196

1%

200K

NO STUFF

MF

1/20W

201

2

1C7194

0.22UF

CERM

10V

10%

402

NO STUFF

2

1 C7195

22PF

0201

50V

NP0-C0G-CERM

NO STUFF

5%

6

9

48

7

5

1

3

2

U7190

CRITICAL

NO STUFF

DFN

LT3470A

21

R7190

PP5V5_DCIN:YES

MF-LF

1/16W

402

0

5%

21

R7191

PP5V5_VDDP

1/16W

402MF-LF

0

5%

21

R7192

1/16W

MF-LF

NO STUFF

402

0

5%

2

1C7190

X5R-CERM

4.7UF

0603

NO STUFF

10%

25V

21

L7195NO STUFF

CRITICAL

10UH-20%-0.85A-0.46OHM

2520

2

1C7184

X5R-CERM

4.7UF

0603

10%

25V

8

12

4

20

19

7

24

29

1326

10

11

23

22

21

5

2

18

17

28

276

25

15

16

9

1

14

3

U7100TQFN

CRITICAL

ISL6259

2 51 4

3 6

10

97 8

Q7180

CRITICAL

DIRECTFET-MCIRF9395TRPBF

4

3

2

1

R71200.020

MF-LF0612

CRITICAL

1W0.5%

2

1R71421K

MF1/20W

201

5%

43

21

R7150

0612-4

0.5%

0.01

1W

MF

765

10

8

1

9432

Q7130CRITICAL

DFN

NTMFD4902NF

SYNC_MASTER=J43_MLB

PBus Supply & Battery Charger




VOLTAGE=8.6V

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_PHASE

PPDCIN_G3H_CHGR

VOLTAGE=18.5V



DIDT=TRUE

GATE_NODE=TRUE


MIN_NECK_WIDTH=0.2 mmCHGR_LGATE

DIDT=TRUE

CHGR_UGATEMIN_LINE_WIDTH=0.5 mm


GATE_NODE=TRUE



VOLTAGE=8.6V

PPVBAT_G3H_CHGR_REG



VOLTAGE=5.5V

PP5V5_CHGR_VDDP


SWITCH_NODE=TRUE


P5V1_SW

DIDT=TRUE

CHGR_CSO_P




VOLTAGE=18.5V

PPCHGR_DCIN_D_RMIN_LINE_WIDTH=0.5 mm

PPVBAT_G3H_CHGR_RMIN_LINE_WIDTH=0.6 mm


VOLTAGE=8.6V

CHGR_CSI_N



CHGR_CSI_P



CHGR_AGATE



CHGR_SGATE

CHGR_DCIN



PPDCIN_G3H_ISOL

P5V1_FB



CHGR_SGATE_DIV

PP3V42_G3H


CHGR_CSI_R_P


CHGR_BOOTDIDT=TRUEMIN_LINE_WIDTH=0.5 mm



VOLTAGE=0V

GND_CHGR_AGNDMIN_LINE_WIDTH=0.2 mm

CHGR_CELL

CHGR_ICOMP_R


CHGR_ICOMPMIN_LINE_WIDTH=0.2 mm

CHGR_BGATE



CHGR_ACIN

PPDCIN_G3H

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

CHGR_VFRQ

CHGR_VCOMP_R



VOLTAGE=5.1V

PP5V1_CHGR_VDDP

CHGR_CSO_R_N

CHGR_CSO_R_P


PPCHGR_DCIN_D_R


CHGR_DCIN

PPBUS_G3H

PP5V1_CHGR_VDDP

SMC_BC_ACOK

CHGR_BMON

CHGR_AMON



CHGR_DCIN_D

VOLTAGE=8.6V


PPVBAT_G3H_CONNMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P5V1_BOOST


CHGR_VNEG MIN_LINE_WIDTH=0.2 mm

CHGR_CSI_R_N

PPDCIN_G3H_INRUSHMIN_LINE_WIDTH=0.6 mm


VOLTAGE=18.5V

CHGR_AGATE_DIV

CHGR_RST_L


CHGR_VCOMPMIN_LINE_WIDTH=0.2 mm

SMC_RESET_L

CHGR_VNEG_R



CHGR_CSO_N

PP5V1_CHGR_VDD

VOLTAGE=5.1V



<BRANCH>

<SCH_NUM>

<E4LABEL>

71 OF 120

48 OF 73

71

48

71

71

48

40 47 60 62

17 30 33 34 35 36 38 44 46 47 57 59 60 62 63

71

47 60 62

48

41 71

41 71

48 48

27 39 40 47 54 60 62

48

46 62

71

71

w w w

. c h

i n a

f i x

. c o

m

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC

NC

NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

OUT

NCNC

OUT

OUT

IN

IN

IN

OUT

IN

IN

IN

NC

NCNC

Apple Inc.


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6 3



FCCM = 1: Forced CCM

(GND)

FCCM = FLOATING: PS4

FCCM = 0: DCM

(CPUVR_ISUMP)

8 65

8 65

8 65

8 17

6 35 36 65

2

1R7279

1%54.9


MF1/20W

201 2

1R7280


1%130

MF1/20W

201

1

4

17

16

33

29

30

32

13

23

22

2026

27

28

2

5

24

21

19

9

15

14

10

11

12

3

18

8

7

25

6

31

U7200

LLP

CRITICAL

ISL95826HRZ-_R6200

8 17

50

50

50

21

R7224

MF1/20W

0201

0

5%

21

R7202

402

1/16WMF-LF

10

5%

2

1C7202

25V10%

0402

PLACE_NEAR=U7200.17:2mm0.22UF

X7R

21

R7201

402

1/16WMF-LF

1

5%

2

1 C7201

10%

X5R402-1

1UF

10V


50

50

2

1 C7210

10%0.01UF

10V

0201X7R-CERM 2

1 C7211

10%10V

0201

0.01UF

X7R-CERM

50

2

1C7213

10%0.1UF

0201CERM-X5R

6.3V

2

1R72206.04K1%

MF1/20W

2012

1R722121K1%

MF1/20W

201

41

2

1R723095.3K1%

MF1/20W

2012

1C7230

10%10V

1800PF

X5R-CERM201

50

2

1C7214

25V10%

X7R-CERM


220PF

201

21

R7215

1%

845

MF1/20W201

21

C7215

25V10%

X7R-CERM

820PF

020121

C7216

25V0201

47PF

NP0-C0G-CERM5%

8 65

9 65

2

1 C7260

10%

0201X7R-CERM

330PF

16V2

1 C7261

10%

X7R-CERM

330PF

16V

0201

2

1C7240

0201-1

+/-10%1.2NF

CERM10V

2 1

C7242

25V


NP0-CERM0201

100PF

5%

2

1C7241

25VNP0-C0G-CERM

0201

56PF


5%

2

1R724075K


1%

MF1/20W

201

2 1

R7242

1%

1K

MF1/20W

201

21

R7243NO_XNET_CONNECTION=TRUE

MF1/20W

0201

0

5%

21

R72359.31K

1%

MF1/20W

201

2

1R723695.3K

1%

MF1/20W

201

2

1

R7237

0201

100KOHM

21

R7250

NOSTUFFNO_XNET_CONNECTION=TRUE

2K

1%

MF1/20W

201

2

1 C7250

10%330PF

16VX7R-CERM0201

NOSTUFF

21

R72411.37K

1%

MF1/20W

201

21

R7210

1%

255

MF1/20W

201

2

1R7223

1%16.9K

MF1/20W

2012

1R72229.31K1%

MF1/20W

201

21

XW7261


SM

2

1R7225

NOSTUFF

MF1/20W

0201

05%

2

1C7278

10%0.1UF

0201CERM-X5R

6.3VPLACE_NEAR=R7279.32:2mm


CPU VR12.6 VCC Regulator IC

CPUVR_ISUMN_R

CPUVR_PROG3

CPUVR_FB2



PP5V_S0_CPUVR_VDD

CPUVR_PWM1

CPUVR_IMON

CPU_VCCSENSE_P_RC

CPU_VCCSENSE_N

CPU_VCCSENSE_P

VOLTAGE=12.9VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPPVIN_S0_CPUVR_VIN

CPUVR_PWM2

PPBUS_S5_HS_COMPUTING_ISNSPP5V_S0

CPUVR_COMP_RC

CPUVR_ISUMN_RC

CPU_VCCSENSE_P_R

CPUVR_NTC_R

PP1V05_S0CPUVR_NTC

CPUVR_FCCM

CPUVR_FB_RC

CPU_PROCHOT_L

CPU_VIDSCLK

CPUVR_ISUMPCPUVR_COMP

CPUVR_ISEN2

CPUVR_ISEN1

CPU_VIDSOUT

CPUVR_FB

CPUVR_ISUMN

CPUVR_DRSEL

CPUVR_SLOPE

CPU_VR_EN

CPU_VR_READY

CPUVR_PROG1

CPU_VIDALERT_L

CPU_RTN

CPUVR_PROG2

49 OF 73

72 OF 120

<E4LABEL>

<SCH_NUM>

<BRANCH>

39 50 51 53 60 62 16 17 32 43 50 54 56 57 59 60 62

6 8 11 15 16 17 36 40 53 56 57 60 62

w w w

. c h

i n a

f i x

. c o

mIN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

D

S

G

D

S

G

D

S

G

D

S

G

OUTOUT

OUTOUT

THRMPAD

PHASE

VCC

LGATE

BOOT

UGATEFCCM

GND

PWM

THRMPAD

PHASE

VCC

LGATE

BOOT

UGATEFCCM

GND

PWM

Apple Inc.


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REVISION

BRANCH

6 3



Additonal Input Bulk Caps

PHASE 1

PHASE 2

353S3942

152S1757

152S1757

.

THESE TWO CAPS ARE FOR EMC

THESE TWO CAPS ARE FOR EMC

Vout = 1.85V max

f = 700kHz

353S3942

32A max output

2

1

C7372

CRITICAL

20%

11V

TANT-POLY

CASE-B2S

62UF-0.023OHM

2

1

C7371

CRITICAL

CASE-B2S

TANT-POLY

62UF-0.023OHM

11V

20%

2

1

C737062UF-0.023OHM

CRITICAL

20%

TANT-POLY

11V

CASE-B2S2

1 C7319

X7R-CERM0402

0.001UF10%50V

2

1 C73180.001UF10%50V

0402X7R-CERM

2

1 C7317

16V

0402

1UF10%

X6S-CERM2

1 C7316

CRITICAL

20%16V

NOSTUFF

10UF

0603X6S-CERM

2

1 C7315

CRITICAL

20%16V

10UF

0603X6S-CERM

NOSTUFF

2

1

R7314

0201

MF-LF1/20W1%

1.00

2

1C7314

CASE-B2S

CRITICAL

11V

TANT-POLY

20%

62UF-0.023OHM

2

1C7313

CASE-B2S

CRITICAL

11V

TANT-POLY

20%

62UF-0.023OHM

21

L7310

MPCG0730-SM

CRITICAL

0.40UH-20%-16A

2

1R7312

2.2

603

5%

1/10WMF-LF

NOSTUFF

2

1 C7312

0.001UF10%

X7R-CERM

0402

50V

NOSTUFF

49

49 50

2

1C7373

CRITICAL

20%

62UF-0.023OHM

11V

TANT-POLY

CASE-B2S

2

1R7316NO_XNET_CONNECTION=TRUE

201

200K1%

MF1/20W

2

1R7315

201MF

1%1K

1/20W

49

49 50

49 50

21

R7317

NONE0201

NONENONE

OMIT

NOSTUFF


2

1 C73290.001UF

50V10%

X7R-CERM0402

49 50

2

1 C7328

0402X7R-CERM

50V10%0.001UF

2

1 C7327

X6S-CERM

16V

0402

10%1UF

2

1

R7324

0201

1/20WMF-LF

1.001%

2

1 C7326

20%16V

X6S-CERM0603

CRITICALNOSTUFF

10UF

2

1 C7325

CRITICAL

16V

X6S-CERM0603

NOSTUFF

20%10UF

2

1

C7324

20%

11V

CRITICAL

CASE-B2S

TANT-POLY

62UF-0.023OHM

2

1

C732362UF-0.023OHM

CASE-B2S

20%

TANT-POLY

CRITICAL

11V

21

L73200.40UH-20%-16A

MPCG0730-SM

CRITICAL

2

1 C7322

50V

0.001UF

NOSTUFF

0402X7R-CERM

10%

2

1R7326NO_XNET_CONNECTION=TRUE

1%

201

200K

MF1/20W

2

1R7325

1%

MF1/20W

1K

201

2

1R7322

NOSTUFF

603

2.25%

1/10W

MF-LF

49

21

R7327


NONE

OMIT

NOSTUFF

NONENONE

0201

49

49 50

2 1

R7311

MF-LF402

5%1/16W

2.2

21

C7311

402CERM

10%16V

0.22UF

2

1C7310

X6S-CERM

1UF10%16V

0402

2

1C7320

0402X6S-CERM

10%1UF

16V

49 50

2

1

C7376

CRITICAL

20%

62UF-0.023OHM

11V

TANT-POLY

CASE-B2S

2

1

C7375

11V

TANT-POLY

20%

CASE-B2S

CRITICAL

62UF-0.023OHM

2

1C7377

CRITICAL

11V

TANT-POLY

20%

62UF-0.023OHM

CASE-B2S

2

1

C7374

CASE-B2S

TANT-POLY

11V

20%

62UF-0.023OHM

CRITICAL

2 1

R7321

402

2.2

5%1/16WMF-LF

21

C73210.22UF

CERM

10%16V

402

321

4

5

Q7310SISA18DNPWRPAK-SM

CRITICAL

OMIT_TABLE

321

4

5

Q7320

CRITICAL

OMIT_TABLE

SISA18DNPWRPAK-SM

4 3

2 1

R7310

1%

0.00075

1W

MF

0612

CRITICAL

43

21

R7320CRITICAL

0.00075

1W

1%

MF

0612

321

4

5


CRITICAL

OMIT_TABLE

321

4

5


CRITICAL

OMIT_TABLE

40 50 72 40 72

40 50 72 40 72

6

1

9

3

8

5

4

7

2

U7310

CRITICAL

DFN

ISL6208D6

1

9

3

8

5

4

7

2

U7320

CRITICAL

DFN

ISL6208D


CPU VR12.5 VCC Power Stage

SYNC_MASTER=J43_MLB

PP5V_S0

CPUVR_ISNS2_P

CPUVR_ISEN1

PPVCC_S0_CPU_PH1



SWITCH_NODE=TRUE


DIDT=TRUEMIN_NECK_WIDTH=0.2 MM

CPUVR_PHASE1

CPUVR_FCCM



CPUVR_BOOT1

DIDT=TRUE

DIDT=TRUE

CPUVR_PH1_SNUB

CPUVR_BOOT2_RCMIN_LINE_WIDTH=0.25 MM


DIDT=TRUE

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMCPUVR_LGATE2


DIDT=TRUESWITCH_NODE=TRUE


CPUVR_PHASE2


DIDT=TRUE


CPUVR_BOOT1_RC


DIDT=TRUE

CPUVR_LGATE1

CPUVR_ISEN2



DIDT=TRUE

CPUVR_BOOT2

CPUVR_ISUMP

CPUVR_ISNS2_N

CPUVR_ISUMN

CPUVR_ISUMN

CPUVR_ISNS1_N

CPUVR_ISNS2_N

CPUVR_ISUMP


PPVCC_S0_CPU_PH2

VOLTAGE=1.8V


CPUVR_ISNS1_N

DIDT=TRUE

CPUVR_PH2_SNUB

CPUVR_PWM1


CPUVR_UGATE1

DIDT=TRUE

CPUVR_FCCM

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

CPUVR_UGATE2

CPUVR_PWM2

CPUVR_ISNS1_P

PP5V_S0

PPVCC_S0_CPU


<BRANCH>

<SCH_NUM>

<E4LABEL>

73 OF 120

50 OF 73

16 17 32 43 49 50 54 56 57 59

60 62

40 50 72

40 50 72

16 17 32 43 49 50 54 56 57 59 60 62

8 10 40 60 62

39 49 51 53 60 62

w w w

. c h

i n a

f i x

. c o

m

BG

TGR

TG

PGND

VIN

VSWIN

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

IN

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(VDDQ/VTTREF Enable)

(DDRREG_DRVH)

(DDRREG_VDDQSNS)

(DDRREG_DRVL)

(DDRREG_LL)

(VTT Enable)

10mA max load

f = 400 kHz

(Q7435 limit)

14.1A max output

Vout = 1.35V

2

1 C7462

BYPASS=U7400.3:3mm

CRITICAL

10UF

6.3VX5R603

20%

8

7

6

1

4

3

9

5

Q7430CSD58873Q3D

Q3D

CRITICAL

2

1R7435

603MF-LF1/10W

NOSTUFF

5%2.2

2

1C7435

10%0.001UF

50V

0402X7R-CERM

NOSTUFF

21

R7460

MF1/20W

10

5%

201

2

1C7400

10VX5R

10UF

BYPASS=U7400.12:1mm

603

20%

2

1 C7432

10%1UF

603-1X5R25V

21

C7425

25V10%

X5R402

0.1UF

2

1 C74330.001UF

50V

0402X7R-CERM

10%

2

1 C7445

X5R603

10UF

6.3V

20%

2

1C74460.001UF

10%50V

0402X7R-CERM

2

1

XW7401SM


57

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14U7400

QFN

CRITICAL

TPS51916

57

21XW7460SM


2

1

XW7400SM


2

1C7450

10V

402CERM

10%0.22UF

17

2

1C7415

BYPASS=U7400.6:1mm

16V10%

X7R-CERM0402

0.1UF

2

1R7417

MF

200K

201

1/20W1%


2

1R741528.7K


1/20W1%

MF201

2

1R7416

1%


201MF

57.6K

1/20W2

1 C7416

BYPASS=U7400.8:1mm

0.01UF

X7R-CERM0402

10%16V

2

1C7401

10VX5R

10UF

603

BYPASS=U7400.2:1mm

20%

21

R74255% 0

MF-LF1/16W

402

21

L7430CRITICAL

FDSD0630-SM

1.0UH-20%-11A-0.011OHM

43

21

R7450CRITICAL

1%MF-LF1/4W0.002

1206

39 72

39 72

2

1R7418

201

49.9K


MF

1%1/20W

2

1 C7440

POLY-TANT

330UF

CASE-B2-SM1

2.0V

CRITICAL

20%

2

1C7441330UF

POLY-TANTCASE-B2-SM1

2.0V

CRITICAL

20%

2

1 C7430

20%62UF-0.023OHM

CASE-B2STANT-POLY11V 2

1 C7431

CASE-B2S

11V20%

TANT-POLY

62UF-0.023OHM

2

1 C7434

CASE-B2S

62UF-0.023OHM

11VTANT-POLY

20%

SYNC_MASTER=J43_MLB

LPDDR3 Supply



VOLTAGE=0V

GND_DDRREG_SGND

DDRREG_EN PP1V2_S3


DDRREG_VDDQSNS_RMIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.2VPPDDR_S3_REG_R


MIN_LINE_WIDTH=0.2 mmDDRREG_VTTSNS



DDRREG_FBMIN_LINE_WIDTH=0.2 mm

DDRREG_TRIP

DDRREG_MODE

ISNS_1V2_S3_P

PP5V_S5

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmDIDT=TRUE

DDRREG_VBST_RC

MIN_LINE_WIDTH=0.6 MMPDDR_S3_REG_L

DIDT=TRUEMIN_NECK_WIDTH=0.1 MM

PDDR_S3_REG_SNUBDIDT=TRUE

DDRREG_VBSTDIDT=TRUE


PP1V2_S3

PP0V6_S0_DDRVTT

DDRREG_VDDQSNS


DDRREG_PGOOD


GATE_NODE=TRUEDIDT=TRUEDDRREG_DRVL

VOLTAGE=0.6V

PPVTT_S3_DDR_BUFMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

ISNS_1V2_S3_N

DDRREG_1V8_VREF


MEMVTT_PWR_EN


DDRREG_LLSWITCH_NODE=TRUE DIDT=TRUE


DIDT=TRUEGATE_NODE=TRUE

DDRREG_DRVH


<BRANCH>

<SCH_NUM>

<E4LABEL>

74 OF 120

51 OF 73

17 19 20 21 22 23 40 51

60 68

19

34 52 60

17 19 20 21 22 23 40 51 60 68

24 60

39 49 50 53 60 62

w w w

. c h

i n a

f i x

. c o

m

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1

SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2

CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

BG

TGR

TG

PGND

VIN

VSW

BG

TGR

TG

PGND

VIN

VSW

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Auto Skip (Higher Efficiency)

152S1798

Vout = 5.0V

SKIPSEL Strap

VREG3

VREF2

F=400KHZ

7.2A MAX OUTPUT

OOA Auto Skip (Lower Efficiency)

152S1798

Vout = 3.3V

6.5A MAX OUTPUT

353S3905

F=400KHZ

2

1C7500

10%

16V

X5R

402

1UF

21

L7560

CRITICAL

PIME063T2R2MS-SM

2.2UH-20%-9A-0.012OHM

2

1 C7541

10%

1UF

402

16V

X5R

2

1C7564

25V

10%

402

0.1UF

X5R2

1 C7524

10%

X5R

25V

402

0.1UF

2

1

C7552

20%

6.3V

POLY-TANT

CASE-B2-SM

150UF-0.035OHM

CRITICAL

2

1 C7581

402

X5R

16V10%

1UF

2

1

R7506

MF

1/20W

201

249K

1%

57

2

1

XW7561SM


2

1C7501

10%

10V

CERM

402

0.22UF

2

1

R7560

1%

23.2K

MF

1/20W

201

2

1

R7561

10K

1%

MF

1/20W

201

2

1

R7520

41.2K

1%

MF

1/20W

201

2

1

R7521

1%

10K

MF

1/20W

201

21

XW7500


SM

2

1

R7516

1%

6.65K

MF

1/20W

201

21

R7546

1%

MF

1/20W

201

1.54K

2

1

XW7560


SM

21

C75180.1UF

X7R-CERM

10%

16V

0402

21

R7547

1%

1.33K

MF

1/20W

201

2

1

R7556

1%

4.22K

MF

1/20W

201

2

1

XW7520


SM

2

1

XW7521


SM

2

1

R7536

1%

7.5K

MF

1/20W

201

2

1

R7537

NO STUFF

1%

20K

MF

1/20W

201

2

1

XW7562PLACE_NEAR=L7560.2:3mm

SM

2

1

XW7522


SM

2

1

C7592

20%

CASE-B2-SM

CRITICAL

TANT

6.3V

150UF-0.018OHM-1.8A

2

1

R7539

1%

MF

201

1/20W

20K

2

1C7539

5%

NP0-C0G

22PF

0201

6.3V

2

1

R7538

1%

MF

1/20W

201

7.5K

2

1C7538

4700PF

X7R

10V

201

10%

57 57

21

R7548NO STUFF

MF

1/20W 0201

0

5%

2

1

R7549

1/20W

MF

0201

0

5%

2

1 C7572

PLACE_NEAR=L7560.2:1.5mm

X7R-CERM0201

1000PF10%16V

2

1 C7583

16V10%

X7R-CERM

0201

BYPASS=Q7560.1:1.5mm

1000PF

2

1 C75701000PF

BYPASS=Q7520.1:1.5mm

16VX7R-CERM

10%

0201

2

1 C7571

X7R-CERM

1000PF10%16V

0201


29

22

13

23

169

2631

2

33

2532

19

6

3

205

14

11

28

214

12

2730

241

187

178

1510

U7501QFN

TPS51980A

CRITICAL

2

1

R7545

402

1/16W

MF-LF

05%

2

1R7551PLACE_NEAR=U7501.4:2mm

MF1/20W

0201

05%

2

1R7552PLACE_NEAR=U7501.21:2mm

MF1/20W

0201

05%

35 57

35 36 57

2

1C7536

10%

X7R

10V

4700PF

201

2

1C7537

16V

X7R-CERM

270PF

10%

0201-1

21

C7588

X7R-CERM

10%

0.1UF

16V

0402

1

2

R7564

MF-LF

402

1/16W

05%

2

1C7554

20%

62UF

CASE-B2S

6.3V

ELEC

CRITICAL

2

1C7590

20%

603

X5R

10UF

10V

2

1C7550

20%

603

10UF

X5R

10V

21

L7520CRITICAL

2.2UH-20%-9A-0.012OHM

PIME063T2R2MS-SM

2

1C7505

20%

X5R

603

10V

10UF

2

1C7542

CASE-B2S

TANT-POLY

11V

62UF-0.023OHM20%

2

1C7540

TANT-POLY

CASE-B2S

20%

11V

62UF-0.023OHM

2

1C7584

CASE-B2S

20%

62UF-0.023OHM

TANT-POLY

11V 2

1C7582

CASE-B2S

11V

TANT-POLY

62UF-0.023OHM20%

2

1R75000

MF

1/20W

0201

5%

2

1R7501

NOSTUFF

MF

1/20W

0201

05%

2

1C7503

20%

402

10V

2.2UF

X5R-CERM

8

7

6

1

4

3

9

5

Q7560

Q3D

CSD58873Q3D

CRITICAL8

7

6

1

4

3

9

5

Q7520

Q3D

CSD58873Q3D

CRITICAL

2

1 C7562NOSTUFF

0402

50VX7R-CERM

10%0.001UF

2

1R7562NOSTUFF

603MF-LF1/10W

2.25%

2

1R7522

603MF-LF

NOSTUFF

1/10W

2.25%

2

1C75220.001UF

NOSTUFF

10%

X7R-CERM50V

0402

2

1R752310

MF1/20W

201

5%

2

1R756310

MF1/20W

201

5%

2

1

C755320%

POLY-TANT

6.3V

CASE-B2-SM

CRITICAL150UF-0.035OHM

2

1C7593

CASE-B2-SM

150UF-0.018OHM-1.8A20%

TANT6.3V

CRITICAL


5V S4RS3 / 3.3V S5 Power Supply


PP5V_S5

PP5V_S4RS3


MIN_NECK_WIDTH=0.2 mmDIDT=TRUE

P3V3_S5_VBST

DIDT=TRUE



P3V3_S5_VBST_R


GND_P5VP3V3_SGND

VOLTAGE=0V


P3V3_S5_CSP2

P5V_S4RS3_COMP1



P5V_S4RS3_VFB1




DIDT=TRUE GATE_NODE=TRUE

P5V_S4RS3_DRVL

P5V_S4RS3_CSP1

P3V3_S5_REG_SNUBDIDT=TRUE

PP3V3_S5


P5V_S4RS3_VBST_R


DIDT=TRUE



P5V_S4RS3_LL

DIDT=TRUE

P5V_S4RS3_DRVH

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mmDIDT=TRUEGATE_NODE=TRUE

P3V3_S5_DRVH


MIN_NECK_WIDTH=0.2 mmSWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P3V3_S5_LL

DIDT=TRUE


P5V_S4RS3_VBST

DIDT=TRUE

P5V_S4RS3_CSN1


P5VP3V3_VREF2

P5VS4RS3_EN

P3V3_S5_COMP2_R

P5V_S4RS3_COMP1_R

P5VP3V3_VREG3

DIDT=TRUEP5V_S4RS3_REG_SNUB

P5V_S4RS3_VFB1_R



P5V_S4RS3_VFB1_XW


MIN_LINE_WIDTH=0.2 mmP3V3_S5_VFB2_XW



P3V3_S5_VFB2_R


S5_PWR_EN


P5VP3V3_VREG3

P5VP3V3_VREF2

P5VP3V3_SKIPSEL

P5VS4RS3_PGOOD

P5VS4RS3_EN_R

SMC_PM_G2_EN

S5_PWRGD

P3V3S5_EN_R


GATE_NODE=TRUE

P3V3_S5_DRVL

DIDT=TRUE

P5V_S4RS3_FUNC

DIDT=TRUE

P5V_S4RS3_REG_L


P5V_S4RS3_CSP1_R

DIDT=TRUE

PP5V_S4RS3

P3V3_S5_CSP2_R

MIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mm DIDT=TRUE

DIDT=TRUE

P3V3_S5_REG_L

PP3V3_S5_REG_R

P3V3_S5_RF



P3V3_S5_COMP2

P3V3_S5_CSN2


P5VP3V3_VREF2


P3V3_S5_VFB2

52 OF 73

<SCH_NUM>

<E4LABEL>

<BRANCH>

75 OF 120

39 60 62

34 51 60

32 33 45 47 52 53 56 60 62

8 11 13 15 16 17 18 28

29 40 55 56 57

58 60 62 72

52

52

52

52

32 33 45 47 52 53 56 60 62

40

52

w w w

. c h

i n a

f i x

. c o

m

GND

GND

GND

HSG

V+

V+

LSG

SW

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

OUTOUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Vout = 1.05V

21A Max Output

f = 300 kHz

1.05V S0 Regulator

Scrub S3 & S5 pins connections!

2

1 C7630

0402

10%

16V

X7R-CERM

0.1UF

2

1C7623


5%

1000PF

0402CERM

25V

2

1C7622


0402CERM25V5%

1000PF

2

1R7630

5%

603

2.2

MF-LF

1/10W

21

R7631

5%

MF-LF

402

0

1/16W

2

1C7648

CASE-B2-SM1

POLY-TANT

CRITICAL

330UF

2.0V

20%

2

1C7649

POLY-TANT

CASE-B2-SM1

CRITICAL

330UF

2.0V

20%

21

L76301.0UH-20%-11A-0.011OHM

CRITICAL

FDSD0630-SM

2

1C7619

CASE-B2S

11V

TANT-POLY

62UF-0.023OHM

20%

2

1C7620

20%

62UF-0.023OHM

CASE-B2S

11V

TANT-POLY2

1C7621

62UF-0.023OHM

CASE-B2S

20%

TANT-POLY

11V

9

8

4

3

2

7

1

10 6 5

Q7630FDPC1012S

LLP

CRITICAL

2

1 C7624

X5R

1UF

16V10%

402

2

1C7632NOSTUFF

0.001UF

X7R-CERM0402

10%50V

2

1R7632

603

5%2.2

1/10WMF-LF

NOSTUFF

2

1C7650

402CERM

0.22UF

10V10%

2

1

XW7600SM


2

1C7601

BYPASS=U7600.2:1mm

603

10VX5R

10UF20%

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14U7600TPS51916

QFN

CRITICAL

2

1R7614

201

17.4K

1/20WMF

1%


2

1C760010UF

BYPASS=U7600.12:1mm

X5R603

10V20%

2

1R7613


1/20W

201

47.5K1%

MF

2

1 C7616

BYPASS=U7600.8:1mm

0402

0.01UF

X7R-CERM

10%16V

2

1R7611


35.7K

1/20W1%

201MF

2

1R7612


1/20W

201

49.9K1%

MF

2

1C7615

BYPASS=U7600.6:1mm

10%0.1UF

X7R-CERM16V

0402

2

1R76101K

1/20WMF

1%

201

2

1

XW7610SM


21

R7641

5%

MF1/20W

10

201

40 72

40 72 57

43

21

R7640

CYN0612-SHORT

0.0031%1w

OMIT

1.05V S0 Power Supply


P1V05S0_BOOT_RC

DIDT=TRUE



P1V05S0_DRVL

GATE_NODE=TRUE

DIDT=TRUE


PP1V05_S0

P1V05S0_VTT



P1V05S0_VDDQSNS

P1V05S0_MODE

P1V05S0_EN

P1V05S0_LL_SNUBDIDT=TRUE

GATE_NODE=TRUE



P1V05S0_DRVH

DIDT=TRUE

P1V05S0_PGOOD


P1V05_S0_VREF

P1V05S3_EN

PP5V_S4RS3

P1V05S0_VTTREF



DIDT=TRUE

P1V05S0_DRVH_R

GATE_NODE=TRUE



P1V05S0_VDDQSNS_R

VOLTAGE=1.05V


PP1V05_S0_REG_R


PP1V05_S0

ISNS_1V05_S0_P

ISNS_1V05_S0_N


P1V05S0_VBST


DIDT=TRUE

P1V05S0_TRIP


P1V05S0_LL




P1V05S0_AGND


P1V05S0_FB


<BRANCH>

<SCH_NUM>

<E4LABEL>

76 OF 120

53 OF 73

6 8 11 15 16 17 36 40 49 53 56 57 60 62

57

32 33 45 47 52 56 60 62

6 8 11 15 16 17 36

40 49 53

56 57 60

62

39 49 50 51 60 62

w w w

. c h

i n a

f i x

. c o

m

VDDIO VINVLDO

SW_0

SW_1

FB

OUT3

OUT2

OUT1

OUT4

OUT5

OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

TP

BI

NC

VIN

SW

OUTFB

EN

NC

THRMGNDPAD

NC

NC

VER 3

D

SG

VER 3

D

SG

IN

IN

BI

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




Keyboard Backlight Driver & Detection

10.2 ohm resistors for current

measurement on LED strings.

Fpwm=9.62kHz

see spec for others

PPBUS_SW_LCDBKLT_PWR

AND PPBUS_SW_BKL

LOADING

RDS(ON)

I_LED=369/Riset

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

THERE IS A SENSE RESISTOR BETWEEN

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

ON THE SENSOR PAGE

FDC638APZ

P-TYPE

0.65 A (EDP)

43 mOhm @4.5V

518S0793

Keyboard Backlight Connector

Addr: 0x58(Wr)/0x59(Rd)

(GND_BKL_SGND)

I_LED=17.1mA

(EEPROM should set EN_I_RES=1)

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*C7797 AND C7799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

2

1 C7799

PLACE_NEAR=D7701.2:5mm

CRITICAL

10UF

50V

1210-1X5R

10%

2

1 C7797

PLACE_NEAR=D7701.2:3mm

CRITICAL

10UF

50V

1210-1X5R

10%

21

L7701CRITICAL

15UH-2.8A

PIMB053T-SM

D2

D1

C1

C4

B2

B1

D4

D3

A4

E1

E2

E3

C5

D5

E5

B3

A2

A1

B5

E4

B4

C2

A5

C3

A3

U770125-BUMP-MICRO

LP8550

CRITICAL

18

13

2

1R7789147K1%

MF1/20W

201

21

F7700

PLACE_SIDE=BOTTOM

603-HF

3AMP-32V-467

2

1R7788301K1%

MF1/20W

201

2

1C7782

X7R-CERM0402

16V

0.1UF10%

4

3

65

21

Q7706

SSOT6-HF

CRITICAL

FDC638APZ_SBMS001

21

XW7720


SM

2

1R7714

1%21.5K

MF1/20W

201

21

R7731200K1%

MF1/20W

201

2

1R7715100K1%

MF1/20W

201

21

R774110K

MF1/20W

201

5%

21

R7753

MF1/20W

0201

0

5%

21

R7757

MF1/20W

0201

0

5%

21

R770433

MF1/20W

201

5%

2

1 C770433PF

NPO-C0G0201

25V5%

2

1R771690.9K1%

MF1/20W

2012

1R775510K

MF1/20W

201

5%

2

1C7711BYPASS=U7701.C4:4mm

6.3VCERM-X5R

0201

0.1UF10%

2

1 C7714

10V

0201X5R-CERM

0.01UF

BYPASS=U7701.D1:3mm

10%

21R7717


BKLT:PROD

MF-LF1/16W 402

05%

58 62

58 62 21R7718

PLACE_NEAR=U7701.D5:10mm

1/16W MF-LF

BKLT:PROD

402

05%

58 62

58 62

21R7719


BKLT:PROD

MF-LF1/16W 402

05%

21R7720


1/16W MF-LF

BKLT:PROD

402

05%

58 62

58 62

21R7721


BKLT:PROD

MF-LF1/16W 402

05%

21R7722


1/16W MF-LF

BKLT:PROD

402

05%

1TP7701

TP-P6

PLACE_SIDE=BOTTOM

35

2

1R7700

MF-LF1/16W

4.7

402

5%

2

1C7750

BYPASS=U7750.1:2:2 MM

1UF

402-1

10VX5R

10%

21

L775010UH-0.58A-0.35OHM

1098AS-SM

CRITICAL

2

1 C77550.22UF

0603-1X5R-CERM50V10%

2

1 C7756

50VX5R-CERM0603-1

0.22UF10%

2

9

7

1

5

84

6

3

U7750

CRITICAL

MLF

SPN035007G

4

3

2

1

6

5

J7715FF14A-4C-R11DL-B-3H

F-RT-SM

CRITICAL

45

3Q7707DMN5L06VK-7

SOT563

12

6Q7707

SOT563

DMN5L06VK-7

2

1C7712


CRITICAL

805

10UF

X5R

10%25V

2

1 C7713


X5R

0.1UF10%25V

402

2

1 C7796


220PF

0402

50VX7R-CERM

10%

KA

D7701


CRITICAL

RB160M-60G

SOD-123

2

1C7710

603-1

1UF

BYPASS=U7701.D1:5mm

X5R

10%25V

21

XW7710

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

SM

13

14 16 19 38 67

14 16 19 38 67

103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM BKLT:ENG3 R7720,R7721,R7722

3103S0198 R7717,R7718,R7719RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM BKLT:ENG


LCD/KBD Backlight Driver

LCDBKLT_DISABLEEDP_BKLT_EN

LCDBKLT_EN_L

BKLT_PLT_RST_L

LCDBKLT_EN_DIV_L

GND_BKL_SGNDMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=0V

BKL_FLTR

BKL_FSET


BKL_ISEN3


BKL_ISEN4


BKL_ISEN5


BKL_ISEN6BKL_FAULT

PPBUS_G3H



LED_RETURN_1


LED_RETURN_2


LED_RETURN_3

LED_RETURN_4



LED_RETURN_5

SMBUS_PCH_CLK

SMBUS_PCH_DATA

EDP_BKLT_PWM

PP5V_S0

PP3V3_S0


BKL_ISEN1


BKL_ISEN2

PPVIN_S0SW_LCDBKLT

SMC_SYS_KBDLED

PPHV_S0SW_LCDBKLT

PPVIN_S0SW_LCDBKLT

BKL_ISET



PPVIN_S0SW_LCDBKLTFET

PPVOUT_SW_LCDBKLT_FBVOLTAGE=50V


PP5V_S0


LED_RETURN_6

LCDBKLT_BOOST


DIDT=TRUESWITCH_NODE=TRUEVOLTAGE=50V


BKL_SCL

BKL_VSYNC_R

BKL_PWM

BKL_SDA

BKL_EN

KBDLED_ANODE

VOLTAGE=40V


MIN_NECK_WIDTH=0.225 MMSWITCH_NODE=TRUE

KBDLED_SW

DIDT=TRUE


VOLTAGE=40V

KBDLED_FB


<BRANCH>

<SCH_NUM>

<E4LABEL>

77 OF 120

54 OF 73

27 39 40 47 48 60 62

39

16 17 32 43 49 50 54 56 57 59 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 57 59

60 62 63 72

39 54

58 60 62

39 54

16 17 32 43 49 50 54 56 57 59 60 62

62 62

w w w

. c h

i n a

f i x

. c o

mIN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND THRM_PAD

NC NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

Apple Inc.


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REVISION

BRANCH

6 3



152S1870

1.8V S3 REGULATOR

Freq = 1 MHz

Max Current = 1.8A

Vout = 1.794V

<Rb>

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

1.5V S0 LDO

Max Current = 0.02A

<Ra>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.5V

70mA is required to support pull-ups. Alternative is strong voltage

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

1.05V SUS LDO

Vout = 1.05V

Max Current = 0.35A

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

2

1 C7821

603

X5R-CERM-1

6.3V

20%

CRITICAL

22UF

2

1C7822

603

X5R-CERM-1

20%

6.3V

22UF

CRITICAL

2

1 C7823

NP0-C0G-CERM

0201

47PF

25V

5%

2

1

R7820

MF

1/20W

201

1%

113K

21

L7820

2520-SM

2.2UH-20%-2.0A-0.108OHM

CRITICAL

2

1C7820

6.3V

X5R-CERM-1

603

20%

22UF

CRITICAL

2

1C7824

X7R-CERM

10%

16V

0201

1000PF

57

57

2

1R7821

1%

MF

1/20W

201

90.9K

2

1 C7872

402

X5R

6.3V

2.2UF10%

7

1

2

6

5

3

4

U7870

CRITICAL

TPS72015

SON

2

1C7871

402

6.3V

CERM

1UF10%

BYPASS=U7870.6:1mm

2

1C7870

402

1UF

CERM

6.3V

10%

BYPASS=U7870.4:1mm

20 21 22 23 55 60

28 57

1

6

9

4 5

3

8

7

2

U7820ISL8009B

DFN

CRITICAL

43

21

R7829

0612-SHORT

OMIT

MF1W

0.0021%

2

1C7840

6.3V

CERM

402

1UF10%

XDP

7

1

2

6

5

3

4

U7840TPS720105

CRITICAL

SON

XDP

2

1 C7841

6.3V

2.2UF

402

X5R

10%

XDP

2

1C7825

603

X5R-CERM-1

20%

6.3V

22UF

CRITICAL

Misc Power Supplies


PP1V05_SUSPP3V3_SUS

PM_SLP_S3_BUF_L

P1V8S3_PGOOD

P1V8S3_EN

PP3V3_S5

PP1V8_S3

PP1V5_S0

PP1V8_S3

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP1V8_S3_REG_R

PP3V3_S5

P1V8S3_FB


P1V8S3_SW

<BRANCH>

<SCH_NUM>

<E4LABEL>

78 OF 120

55 OF 73

16 60 8 11 14 18 44 56 57 60 62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 56 57 60 62

20 21 22 23 55 60

8 11 13 15 16 17 18 28 29 40

52 55 56 57

58 60 62 72

w w w

. c h

i n a

f i x

. c o

m

INGND

VOUT

ON

VIN

NC NC

GND

VOUT

ON

VIN

IN

NCNC

GND

VOUT

ON

VIN

IN

NC NC

IN

INGND

VOUT

ON

VIN

IN

IN

INGND

VOUT

ON

VININ

GND

VDD

D

SON

CAP

NC NC

GND

VOUT

ON

VIN

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

G

D S

IN

GND

VDD

D

SON

CAP

S

D

ON S

D

VDD

GND

IN

VER 3

D

SG

VER 3

D

SG

Apple Inc.


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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



@ 2.5V

R(on)

1.5V S0 Audio Switch

5V S0 Switch

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e

EDP: 35mA

R(on)

3.3V SUS Switch

Current

25.8 mOhm Max

18.5 mOhm Typ

TPS22924C

Type

Load Switch

18.5 mOhm Typ

U8040

TPS22924C

19.6 mOhm Typ

21.8 mOhm Max

2A Max

@ 2.5V

Current

@ 1.8V

R(on)

Part

Current

3.3V Sensor Switch

Sense R on sensor page

2A Max

25.8 mOhm Max

Type

Current

2A MaxCurrent

Type

R(on)

@ 2.5V

EDP: 1A

2.5A

17 mOhm Max

15 mOhm Typ

25.8 mOhm Max

Load Switch

@ 2.5V

R(on)

Type

Part

Load Switch

Current

R(on)

Part

@ 2.5V

2A Max

EDP: 1.02A

U8010

TPS22924C

Current

EDP: 50mA

18.5 mOhm Typ

Part

Current 2A Max

EDP: 112mA

8.5 mOhm Max

Type Load Switch

Type

Part

U8050

Part

R(on)

Load Switch

U8020

TPS22924C

U8030

Part

3.3V S0 Switch

Type

SLG5AP1438V

Load Switch

18.5 mOhm Typ

TPS22924C

Load Switch

Load Switch

3.3V S3 Switch

EDP: 300mA?

U8080

Part

U8005

Load Switch

Current

Type

R(on)

(HSIOFET_EN_L)

U8070

25.8 mOhm Max

3.3V SSD Switch

Type

18.5 mOhm Typ

25.8 mOhm Max

EDP: 5A

Sense R on sensor page

6A Max

@ 4V Vgs

9.8 mOhm Typ

EDP: 1.84A

1.05V PCH HSIO Switch

3.3V S4 Switch

R(on)

@ 25C

5.3A Max

SLG5AP1453VPart

7.8 mOhm Typ

2A Max

EDP: 1.84A

U8000

TPS22924C

SLG5AP1417V

TBD mOhm Max

EDP: 119mA

HSIO has turn-on requirement of

<65uS from EN to 95% (1.05V)

<0.1V/uS ramp rate and

56 57

2

1C8030

20%

0201-1

1.0UF

6.3VX5R

B1

A1

B2

A2

C2

C1

U8030

CRITICAL

CSPTPS22924

B1

A1

B2

A2

C2

C1

U8000TPS22924

CSP

CRITICAL

18 28 57

2

1C8000

0201-1

20%1.0UF

6.3VX5R

B1

A1

B2

A2

C2

C1

U8020

CSPTPS22924

CRITICAL

2

1C8020

0201-1

20%1.0UF

6.3VX5R

57

2

1C8071

201

4700PF

10VX7R

10%

2

1 C8070

6.3VCERM-X5R0201

0.1UF10%

15 30 57 62

57

2

1C8010

0201-1

20%1.0UF

6.3VX5R

B1

A1

B2

A2

C2

C1

U8010

CSPTPS22924

CRITICAL

43

21

R8011

MF0612-SHORT

0.002

OMIT

1W1%

43

21

R8000

MF0612-SHORT

OMIT

1W1%

0.002

43

21

R8020

MF0612-SHORT

OMIT

1W1%

0.002

2

1C8040

0201-1

20%1.0UF

6.3VX5R

57

2

1R8040

5%

201

1/20WMF

NOSTUFF

10K

21

R8070

5%

0

0201

1/20WMF

NOSTUFF

56 57

21

R8041

5%

0

0201

1/20WMF

21

R8042

5%

0

0201

1/20WMF

NOSTUFF

35 37 40

B1

A1

B2

A2

C2

C1

U8050

CSPTPS22924

CRITICAL

2

1C8050

0201-1

20%1.0UF

6.3VX5R

21

R8050

5%

0

MF-LF402

1/16W

2

1 C8080

16VX5R-CERM0201

0.1UF10%

57

1

52

8

37

U8080

CRITICAL

TDFNSLG5AP1443V

43

21

R8081

MF0612-SHORT

OMIT

1W1%

0.002

2

1C8081

201

4700PF

10VX7R

10%

B1

A1

B2

A2

C2

C1

U8040TPS22924

CRITICAL

CSP

4

1

5

2

3

6

Q8061NTUD3169CZ

SOT-963

NOSTUFF

2

1R8061

5%

201

1/20WMF

330

NOSTUFF

2

1R8062

5%

201

1/20WMF

330

NOSTUFF

2

1C8060

0201

0.01UF

X5R-CERM10V

NOSTUFF

10%

32

1

4

5

Q8060IRFHM830DPBFPQFN3.3X3.3

NOSTUFF

CRITICAL

2

1R8060

5%300

402

1/16WMF-LF

NOSTUFF

2

1R8063

5%

201

1/20WMF

10K

NOSTUFF

15 56 1

52

8

37

U8070SLG5AP1453V

TDFN

CRITICAL

1

7

59

8

3

2

U8005

TDFN

SLG5AP1471V

CRITICAL15 56

2

1C8005

10V

1UF

402X5R

10%

12

6Q8062

SOT563

DMN5L06VK-7

NOSTUFF

45

3Q8062NOSTUFF

DMN5L06VK-7

SOT563

SYNC_MASTER=J43_MLB

Power FETs


HSIOFET_EN_L

HSIOFET_DISCHARGE

PCH_HSIO_PWR_EN

SSD_PWR_EN


PP1V05_S0


P3V3S0SW_SSD_FET_RAMP

PCH_HSIO_PWR_EN

PP5V_S0

PP3V3_S5


PP3V3_S0SW_SSD_FET_RVOLTAGE=3.3VMIN_LINE_WIDTH=0.50MM

HSIOFET_DRV_H

HSIOFET_DRV_L

PP1V05_S0

HSIOFET_EN

PP5V_S0

PP5V_S0

P1V5S0SW_AUDIO_EN

PP1V5_S0

S4_PWR_EN

SMC_SENSOR_PWR_EN

PP3V3_S4SW_SNSVOLTAGE=3.3VMIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm

PP3V3_S4SW_SNS_FET_R

P3V3SUS_EN

PP3V3_SUS

PP3V3_S5


PP3V3_SUS_FET_RVOLTAGE=3.3V

P3V3S3_EN

PP3V3_S3

PP3V3_S5

P3V3S0_EN

PP3V3_S5

PP3V3_S4_FET_RVOLTAGE=3.3VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

PP3V3_S0_FET_R

P5VS0_FET_RAMP

PP3V3_S4

PP1V5_S0SW_AUDIO

PP5V_S4RS3


MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMVOLTAGE=3.3VPP3V3_S3_FET_R

P5VS0_EN PP5V_S0_FET_RVOLTAGE=5VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

PP3V3_S5

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.3 mmPP1V5_S0SW_AUDIO_HDA

VOLTAGE=1.5V


PP1V5_S0SW_AUDIO

MAKE_BASE=TRUE


VOLTAGE=1.5V

PP3V3_S5

P3V3S0_EN

<BRANCH>

<SCH_NUM>

<E4LABEL>

80 OF 120

56 OF 73

8 11 56 60

6 8 11 15 16 17 36 40 49 53 56 57 60 62

8 11 56 60

16 17 32 43 49 50 54 56 57 59 60 62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

39

6 8 11 15 16 17 36 40 49 53 56 57 60 62

16 17 32 43 49 50 54 56 57 59 60 62

16 17 32 43 49 50 54 56 57 59 60 62

8 55 57 60 62

39 40 41 60

8 11 14 18 44 55 57 60 62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

15 18 19 34 38 39 60 62 63

8 11 13 15

16

17 18

28

29 40

52

55 56

57

58 60

62

72

8 11 13 15 16 17

18 28 29

40 52 55

56 57 58

60 62 72

39

25 26 27 29 34 36 37 60 62

56 59 63

32 33 45 47 52 53 60 62

8 11 17 56

8 11 13 15 16 17 18 28

29 40 52 55

56 57 58 60

62 72

8 11 17 56

56 59 63

8 11 13 15 16 17 18 28

29 40 52 55

56 57 58 60

62 72

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

NC

NC

NC

Q3

Q2

Q4

Q1

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND THRM_PAD

IN

OUT

NC

NC

IN

IN

OUT

OUT

IN

SYM_VER_2

G S

D

OUT

IN OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUTIN

OUTIN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

IN

OUT

OUT

OUT

IN

Apple Inc.


124578

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



1.5V Codec Enable

so 1.05V can fall after 1.5V

Vce(sat) 0.1V max @ 1mA

V4MON: 0.572V-0.630V

Vbe 0.7V max @ 2mA

(IPU)

V3MON: 0.572V-0.630V

Thresholds:

S5_PWRGD-->SMC

5V needs to be held up

U8130 Sense input

SSD Enable

VFRQ High: Variable Frequency

5V Divider:

1.5V Divider:

1.05V Divider:

3.19V @ 4.5Vmin

0.718V @ 1.45Vmin

0.723V @ 1.02Vmin

353S2310

S3 Enables

S5 Power Good

SMC-->PM_DSW_PWRGD

S5 Enables

Min delay timeNo stuff C8131, 12ms

threhold is 3.07V

Standby Enables

VFRQ Low: Fix Frequency

SUS Enables

3.3V Divider: 1.07V

VDD: 2.734V-3.010V

5.0V Divider: 1.07V

V2MON: 2.815V-3.099V

Q1 Vth 0.7~1V @Id 250uA

CHGR VFRQ Generation

(ISL version used for development)

S0 Rail PGOOD Circuitry

9ms RC delay

3.3V SUS Detect

S0 Rail PGOOD (BJT Version)

376S0854

PM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_LPM_SUS_EN

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

0

0

0

0

1

0

0

1

11

0

1

0

0

0

0

0

1

Mobile System Power State Table

SMC_S4_WAKESRC_ENSMC_PM_G2_ENABLESMC_ADAPTER_ENState

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

1

1

1

0

1

1

0

1

0

toggle 3Hz

1

X

Battery Off (G3HotAC)

Battery Off (G3Hot)

Sleep (S3AC)

Deep Sleep (S4)

Run (S0)

Deep Sleep (S5AC)

Deep Sleep (S4AC)

Sleep (S3)

Deep Sleep (S5)

S0 Enables

2

1R8131330K

MF1/20W

201

5%

48 2

1R816710K

MF1/20W

201

5%

16 17 35 57

2

1R8157100

MF1/20W

201

5%

21

R8166100

MF1/20W

201

5%

21

R8164100

MF1/20W

201

5%

21

R8162330

S0PGOOD_ISL

MF1/20W

201

5%

53

2

1R8156150K

1%

MF1/20W

201

2

1C8160

10%0.1UF

0201CERM-X5R

6.3V

S0PGOOD_ISL

2

1R8151

1%54.9K

MF1/20W

201

2

1R8152

1%15K

MF1/20W

201

3

2

8

46

1

7

5

Q8150ASMCC0179

CRITICAL

DFN2015H4-8

21

R81541K

MF1/20W

201

5%

21

R81551K

MF1/20W

201

5%

2

1 C81311000PF10%

0201X7R-CERM16V

NO STUFF

2

1R8133100K

MF1/20W

201

5%2

1C8130

10%0.1UF

0201CERM-X5R

6.3V

BYPASS=U8130.6:2.3mm

13 62

72

6

5

3

9

8

1

4

U8160S0PGOOD_ISL

CRITICAL

TDFN

ISL88042IRTEZ

2

1R8173

S0PGOOD_ISL

1%15K

MF1/20W

2012

1R8171

S0PGOOD_ISL

1%15K

MF1/20W

2012

1R8161

S0PGOOD_ISL

15K1%

MF1/20W

201

2

1R8170S0PGOOD_ISL

1%15K

MF1/20W

2012

1R8172S0PGOOD_ISL

1%6.04K

MF1/20W

2012

1R8160S0PGOOD_ISL

1%6.04K

MF1/20W

201

13 40 57

56 57

21

R81531K

MF1/20W

201

5%

21

R8115

MF1/20W

0201

0

5%

4

6

5 3

1

2

U8170NOSTUFF

74LVC1G32SOT89113 35

2

1C8170

10%0.1UF

0201CERM-X5R

6.3V

NOSTUFF

BYPASS=U8170.6:2.3mm

35 36

18 28 56 57

18 28 56 57

51

21

3Q8131DMN32D2LFB4

DFN1006H4-3

21

R8168100

MF1/20W

201

5%

35 52 57

2

1R8141100K


MF1/20W

201

5%

35 36 52 57

21

R8140


100

MF1/20W

201

5%

52 57

13 18 29 34 35 57

2

1 C8111

402

0.1UF


20%

CERM10V

2

1 C8112

402

10%6.3V

NO STUFF


0.47UF

CERM-X5R

2

1R8111


20K

MF1/20W

201

5%

2

1R8112


MF1/20W

0201

05%

2

1 C8114

402

10%6.3VCERM-X5R


0.47UF

NO STUFF

2

1R8114USB_PWR:STBY


100

MF1/20W

201

5%

51 57

56 57

33 57 59 63

13 40 57

2

1R8158

1%15K

MF1/20W

201

2

1R8159

1%7.15K

MF1/20W

201

13 17 18 35 21

R8178100

MF1/20W

201

5% 28 55 57

5

4

1

2

3

U8180

MC74VHC1G08SC70-HF

2

1R8180NOSTUFF

330K

MF1/20W

201

5%

2

1 C8185

402

10%

CERM

0.22UF

10V

NO STUFF


21

R8138


NO STUFF

820

MF1/20W

201

5%

2

1R8185


MF1/20W

0201

05%

2

1 C8186

402

0.1UF


20%10VCERM

2

1R8186


20K

MF1/20W

201

5%

2

1 C8187

402

10%6.3V

NO STUFF


CERM

0.68UF

2

1R8187


MF1/20W

0201

05%

53 57

28 55 57

56 57

55 57

2

1R8116


MF1/20W

0201

05%

2

1 C8116

402

10%6.3VCERM-X5R

0.47UF


NO STUFF

15 30 56 57 62 15 30 56 57 62

56

2

1 C8146

402

25V10%0.1UF

X5R


21

R81461K

MF1/20W

201

5%

21

R8145

PLACE_NEAR=U8040.2:C7mm

100K

MF1/20W

201

5%

13 59 63

2

1 C8180

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U8180.6:3mm

1

7

2 6

4

5

3

U8130

QFNTPS3808G33

CRITICAL

K

A

D8175SM-201

RB521ZS-30

NO STUFFPLACE_NEAR=U7501.4:15mm

21

R8176240

NO STUFF


MF1/20W

201

5%

2

1R8175


MF1/20W

0201

05%

2

1 C8175

402

10%

X5R6.3V

2.2UF

NO STUFF


2

1 C8142

402

10%6.3V

NOSTUFF


CERM-X5R

0.47UF

K

A

D8185

RB521ZS-30

NO STUFF


SM-201

K A

D8146

PLACE_NEAR=U8040.2:C7mm

RB521ZS-30

SM-201

56 57

2

1R8190

MF1/20W

0201

05%

2

1 C8190

402

25V10%0.1UF

X5R

NO STUFF

2

1R8117USB_PWR:S3


100

MF1/20W

201

5%

35 36 52 57

52

21

R8179

USB_PWR:S3

MF1/20W

0201

0

5%

21

R8177

USB_PWR:STBY

MF1/20W

0201

0

5%

21

R8165100

MF1/20W

201

5%

52

2

1C8159

402

10%

X5R

1UF

10V

K A

D8184

RB521ZS-30

SM-201


2

1R8184


330

MF1/20W

201

5%

Power Control


P3V3S0_EN_D

PM_SLP_S3_BUF_LMAKE_BASE=TRUE

MAKE_BASE=TRUEP1V05S0_EN P1V05S0_EN

P3V3S0_ENMAKE_BASE=TRUEP5VS0_EN P5VS0_EN

PM_SLP_S3_BUF_L

PM_SLP_S3_BUF_L

MAKE_BASE=TRUEP3V3S0_EN

PM_SLP_S3_L PM_SLP_S3_R_L

PP3V3_S5

P1V05_EN_D

PM_SLP_S5_L

VMON_Q4_BASE

P1V5CODEC_EN_D

AUD_PWR_EN

USB_PWR_EN

PP1V5_S0PM_SLP_S3_BUF_L

ALL_SYS_PWRGD

VMON_Q2_BASE

S0PGD_BJT_GND_R

P1V8S3_PGOOD

PP3V3_S5

VMON_5V_DIV

VMON_3V3_DIV

VMON_Q3_BASE

PP3V3_S0

TP_SUS_PGOOD_MR_L

PM_SLP_SUS_LMAKE_BASE=TRUE

PP5V_S0

PP3V3_S5

PM_SLP_S3_R_L

PP3V3_SUS

PM_SLP_SUS_L

PM_RSMRST_L

S4_PWR_EN

MAKE_BASE=TRUES4_PWR_EN

SMC_PM_G2_EN

MAKE_BASE=TRUESMC_PM_G2_EN

MAKE_BASE=TRUES5_PWR_EN S5_PWR_EN

DDRREG_PGOOD

ALL_SYS_PWRGDS0PGD_C

P1V05_DIV_VMON

P5V_DIV_VMON

P1V5_DIV_VMON

PP5V_S0

CHGR_VFRQ

PP3V42_G3H

ALL_SYS_PWRGD_R

PP1V05_S0

PP1V5_S0

PP3V42_G3H

S5_PWRGD S5_PWRGDMAKE_BASE=TRUE

SSD_PWR_ENMAKE_BASE=TRUE

PP3V3_SUS

SUS_PGOOD_CT

S4_PWR_EN

S4_PWR_EN

PM_SLP_S4_L

P5VS4RS3_PGOOD

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUEP3V3SUS_EN P3V3SUS_EN

P5VS4RS3_EN

P3V3S3_ENMAKE_BASE=TRUE

P3V3S3_EN

P1V8S3_EN

SSD_PWR_EN

DDRREG_ENMAKE_BASE=TRUE

PP3V3_S0

P1V05S0_PGOOD

PP3V3_S5

P5VS4RS3_EN_RC

DDRREG_EN

P1V8S3_ENMAKE_BASE=TRUE

PM_SLP_S4_L

P5VS4RS3_EN_D

MAKE_BASE=TRUEUSB_PWR_EN

P1V5S0SW_AUDIO_EN

57 OF 73

<SCH_NUM>

81 OF 120

<E4LABEL>

<BRANCH>

28 55 57

53 57

56 57

56 57

57

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 55 56 57 60 62 28 55 57

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 12 13 15 17 18 26 30 34

36 37 38 39 40

41 42 43 54 57 59 60

62 63 72

16 17 32 43 49 50 54 56 57 59 60 62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

57

8 11 14 18 44 55 56 57 60 62

18 28 56 57

52 57

16 17 35 57

16 17 32 43

49 50

54 56

57 59

60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

6 8 11 15 16 17 36 40 49 53 56 60 62

8 55 56 57 60 62

17 30 33 34 35 36 38 44

46 47 48 57

59 60 62 63

35 52 57

8 11 14 18 44 55 56 57 60 62

13 18 29 34 35 57

56 57

56 57

51 57

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

55 57

33 57 59 63

w w w

. c h

i n a

f i x

. c o

m

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

BI

BI

BI

IN

NC

NCNC

Apple Inc.


124578

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SHEET


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REVISION

BRANCH

6 3



4.7 kOhm to 3.3V

Internal DP Connector: 518S0829

LCD Connector

LED Backlight I/F

DisplayPort I/F

Pull-ups on panel side,

(DP_INT_AUX_CH_C_N)

(DP_INT_AUX_CH_C_P)

Sense resistor on

sensor page

2

1 C8312

20%

603

10UF

6.3VX5R2

1C8311

6.3VCERM-X5R

0201

0.1UF10%

2

1 C8309

6.3VCERM-X5R0201

0.1UF10%

5

4

3

2

7

1

6

U8300FPF1009

CRITICAL

MFET-2X2-8IN

2

1C8317PLACE_NEAR=J8300.3:2mm

1000PF

603C0G-CERM

50V5%

2

1C8315

0201

16V

1000PF

X7R-CERM

10%

21

C8324

16VX5R-CERM

0201

0.1UF

10%

21

C8325

16V

0201X5R-CERM

0.1UF

10%

21

C8320

16V

0201X5R-CERM

0.1UF

10%

21

C8321

16V

0201X5R-CERM

0.1UF

10%

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J8300

F-RT-SM20525-130E-01

CRITICAL

2

1R8350


100K

MF1/20W

201

5%

21

R8360

MF1/20W

0201

0

5%

2

1R83801M

MF1/20W

201

5%

2

1R83701M

MF1/20W

201

5%

13

54 62

54 62

54 62

54 62

54 62

54 62

5 65

5 65

13

5 65

5 65

35 38 71

35 38 71

21

R8361

MF1/20W

0201

0

5%

21

R8362

MF1/20W

0201

0

5%

2

1R8318


1M

MF1/20W

201

5%

2

1R8317


1M

MF1/20W

201

5%

2

1R83634.7K

MF1/20W

201

5%

2

1R83644.7K

MF1/20W

201

5%

21

L8304FERR-120-OHM-1.5A

0402-LF


Internal DisplayPort Connector

SMBUS_SMC_0_S0_SCL

DP_INT_HPD

DP_INT_AUX_CH_C_N

DP_INT_AUX_CH_C_P

DP_INT_ML_P<0>

DP_INT_ML_N<0>

SMBUS_SMC_0_S0_SDA

DP_INT_AUXCH_C_P

DP_INT_AUXCH_C_N

DP_INT_ML_C_P<0>

DP_INT_HPD_CONN

DP_INT_ML_C_N<0>

LED_RETURN_6

LED_RETURN_5

LED_RETURN_4

LED_RETURN_3

LED_RETURN_1

LED_RETURN_2

I2C_TCON_SDA_R

PP3V3_S5

EDP_PANEL_PWR

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MMPP3V3_S0SW_LCD_UF

PPHV_S0SW_LCDBKLT

I2C_TCON_SCL_R

PP3V3_S0SW_LCD_R PP3V3_S0SW_LCD

<BRANCH>

<SCH_NUM>

<E4LABEL>

83 OF 120

58 OF 73

62 65

62 65

62 65

62 65

62

62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 60 62 72

62

54 60 62

62

41 41

w w w

. c h

i n a

f i x

. c o

m

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

BI

BI

OUT

IN

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

OUT

Apple Inc.


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SHEET


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REVISION

BRANCH

6 3



LIO Connector516S1036 (HIROSE 3.0mm RCPT)

9

8 7

6

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

16 15

14 13

12 11

10

1

J9500

GND_VOID=TRUE

DF40CG3.0-48DS-0.4V

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

F-ST-SM

CRITICAL

2

1C95000.1UF

16VX5R-CERM

0201

10%

BYPASS=J9500:1.5mm

2

1C95200.1UF

0201X5R-CERM

16V10%

BYPASS=J9500:1.5mm

2

1 C95100.1UF

X5R-CERM0201

10%16V

BYPASS=J9500:1.5mm

2

1

D9521ESD0P2RF-02LSTSSLP-2-1

CRITICAL

GND_VOID=TRUE

2

1

D9520ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

GND_VOID=TRUE

2

1

D9510

TSSLP-2-1ESD0P2RF-02LS

CRITICAL

GND_VOID=TRUE

2

1

D9511

GND_VOID=TRUE

CRITICAL

ESD0P2RF-02LSTSSLP-2-1

14 63 66

14 63 66 21C952110% 0201

0.1UF

16VX5R-CERMGND_VOID=TRUE

21C9522020110%

0.1UF16VX5R-CERMGND_VOID=TRUE

21

C9531

5%

NOSTUFF

15PFGND_VOID=TRUE NP0-CERM25V 0201

21

C9532

5%

NOSTUFF

25V15PF

NP0-CERM 0201GND_VOID=TRUE

14 63 66

14 63 66

21

R95205%

002011/20W MF

GND_VOID=TRUE

21

R95105%

002011/20W MF

GND_VOID=TRUE

13 57 63

45 63

45 63 72

45 63 72

14 63 66

14 63 66

37 63

33 57 63

14 16 63

35 36 48 63

35 63

35 38 63 71

35 38 63 71

12 63 67

12 63 67

12 63 67

12 63 67

12 63 67

21

R9500

5%

0

0201

1/20WMF

NOSTUFF

2

1C9550

5%

NOSTUFF

0402

50VC0G-CERM

10PF

SYNC_DATE=11/13/2012SYNC_MASTER=CLEAN_J41

LIO Connector

HDA_BIT_CLK

PP3V3_S0

PP1V5_S0SW_AUDIO

USB3_EXTB_R2D_C_P

USB3_EXTB_R2D_C_N

USB3_EXTB_D2R_P

HDA_RST_L

XDP_USB_EXTB_OC_L

PP3V42_G3H

USB_PWR_EN

HDA_SYNC

FINSTACKSNS_ALERT_L

SPKRAMP_SHDN_L

SPKRAMP_INR_N

SPKRAMP_INR_P

USB_EXTB_P

AUD_PWR_EN

USB3_EXTB_R2D_N

SMBUS_SMC_2_S3_SCL

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.1MMVOLTAGE=5V

PP5V_S0_ALT_AUD_LDO_EN

PP5V_S0

USB3_EXTB_R2D_P

USB3_EXTB_D2R_RC_P

USB3_EXTB_D2R_RC_N

USB3_EXTB_D2R_N

SMBUS_SMC_2_S3_SDA

SYS_ONEWIRE

SMC_BC_ACOK

HDA_SDOUT

HDA_SDIN0

USB_EXTB_N

<BRANCH>

<SCH_NUM>

<E4LABEL>

95 OF 120

59 OF 73

56 63

17 30 33 34 35 36 38 44 46 47 48 57 60 62 63

63 66

63

16 17 32 43 49 50 54 56 57 60 62

63 66

63 66

63 66

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? mA

5V Rails

3.3V Rails

2A max supply

"G3Hot" (Always-Present) Rails

TBT Rails (off when no cable)1.8V/1.5V/1.2V/1.05V Rails

CPU "VCORE" RAILS

Digital Ground

1.84A

LCDBKLT Rail


Power Aliases


PP3V3_S0

MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUEMIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

PP3V3_S0

PP3V3_S0

PP5V_S0


MAKE_BASE=TRUE




MAKE_BASE=TRUEVOLTAGE=1.05V

PP1V05_TBTCIO

PP1V05_S0MIN_LINE_WIDTH=0.6 MM



PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP0V6_S0_DDRVTT


VOLTAGE=0.75V


PP0V6_S0_DDRVTT

MAKE_BASE=TRUE

PP1V2_S3

PP3V3_S0

PP3V3_S0

MAKE_BASE=TRUE

PP3V3_S4SW_SNSMIN_LINE_WIDTH=0.50MM


VOLTAGE=3.3V

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_SUS

PP3V3_S3

PPDCIN_G3H_ISOL

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

MAKE_BASE=TRUE


PPDCIN_G3H_ISOL


PPDCIN_G3H_ISOL

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V42_G3H

PP3V42_G3H

PP3V3_S3

PP3V3_S3

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

PP3V3_S5

PP3V3_S5

PP3V3_S3

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S4PPDCIN_G3H

PP1V8_S3

PP15V_TBT




PP15V_TBTPP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S4SW_SNS

PP3V3_S4

PP3V3_S4

PP3V3_S4

PP3V3_S5

PP1V05_S0

PP1V05_S0

PP5V_S0

VOLTAGE=1.05V

MAKE_BASE=TRUE


PP1V05_S0SW_PCH_HSIOMIN_LINE_WIDTH=0.6 MM

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP1V5_S0


VOLTAGE=3V

MAKE_BASE=TRUE


PPVRTC_G3H

PP3V42_G3H

PP3V42_G3H

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP5V_S4RS3

PP5V_S0

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0

PPVRTC_G3H

PP5V_S4RS3


PPDCIN_G3H_ISOL

PP3V3_S0SW_SSD

PPHV_S0SW_LCDBKLT

PP1V8_S3

PP3V3_TBTLC

PP3V3_TBTLC

PP3V3_TBTLC

PP1V2_S3

PP1V5_S0


MAKE_BASE=TRUE


PP3V3_TBTLC

PP15V_TBT

PP1V2_S3


MAKE_BASE=TRUE

VOLTAGE=1.8V


PPVCC_S0_CPU

PPVCC_S0_CPU

PPVCC_S0_CPU

PPVCC_S0_CPU

MAKE_BASE=TRUE

PPHV_S0SW_LCDBKLTMIN_LINE_WIDTH=0.5 MM

VOLTAGE=50VMIN_NECK_WIDTH=0.375 MM

PPHV_S0SW_LCDBKLT

PP1V2_S3

PP3V3_S0SW_SSD

PP3V3_S0SW_SSD


MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

MAKE_BASE=TRUE

PPDCIN_G3H

MAKE_BASE=TRUE



PP3V42_G3H



PPDCIN_G3H

PP3V42_G3H

PPBUS_G3H

PPBUS_G3H

PP1V8_S3

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H


VOLTAGE=8.6V



MAKE_BASE=TRUE

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0


PP1V05_S0

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

MAKE_BASE=TRUE


VOLTAGE=8.6V


PPBUS_G3H

PP1V2_S3

PPBUS_G3H




PP1V05_S0

PP1V05_S0

PP3V42_G3H

PP5V_S5

PP5V_S0


PP1V8_S3

MIN_NECK_WIDTH=0.2MMVOLTAGE=1.2VMAKE_BASE=TRUE


PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

PP3V3_S3

PP3V3_S3

PP3V3_SUS

PP3V3_SUSMIN_LINE_WIDTH=0.50MM



PP1V2_S3

VOLTAGE=1.2V

MAKE_BASE=TRUE


PP3V3_S5

PP3V3_S4_TBTAPWR

PP5V_S4RS3

PP5V_S4RS3

PP5V_S4RS3

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S5

PP1V5_S0

PP0V6_S0_DDRVTT

PP1V05_SUS

PP0V6_S0_DDRVTT

PP1V05_SUS

PP1V5_S0


PP1V5_S0


PP1V2_S3

PP1V2_S3

PP1V2_S3


PP1V05_SUSMIN_LINE_WIDTH=0.4 MM




PP3V42_G3HMIN_LINE_WIDTH=0.6 MM

PP3V42_G3H



PPVRTC_G3H

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PP5V_S5

PP5V_S5

MAKE_BASE=TRUEVOLTAGE=5V


VOLTAGE=5V


MAKE_BASE=TRUE

PP5V_S4RS3


PP5V_S4RS3

PP5V_S4RS3

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS


PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5


MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

PP3V3_S5

MAKE_BASE=TRUE

PPVIN_S4SW_TBTBST_FETVOLTAGE=8.6V

VOLTAGE=12.8V

PPVIN_SW_TBTBST

PP3V3_S4

PP3V3_S4

PP3V3_S4MIN_LINE_WIDTH=0.60MM VOLTAGE=3.3V

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM



VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S4_TBTAPWR

GNDVOLTAGE=0V


<BRANCH>

<SCH_NUM>

<E4LABEL>

100 OF 120

60 OF 73

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

16 17 32 43 49 50 54 56 57 59 60 62

26 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

24 51 60

24 51 60

17 19 20 21 22 23 40 51 60 68

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42

43 54 57 59 60 62 63 72

39 40 41 56 60

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60

62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57

59 60 62 63 72

8 11 14 18 44 55 56 57 60 62

15 18 19 34 38 39 56 60 62 63

40 47 48 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

40 47 48 60 62

40 47 48 60 62

8 11 12 13 15 17 18 26 30 34 36 37 38

39 40 41 42 43 54 57 59 60 62

63

72 8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 60 62 63 72

8 11

12 13 15 17 18 26 30 34 36 37

38

39 40 41 42 43 54 57 59 60 62

63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 60 62 63 72 8

11

12

13

15 17 18 26 30 34 36 37 38 39 40 41 42

43 54 57 59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42

43 54 57 59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38

39 40 41 42 43 54 57 59 60 62

63

72 8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42

43 54 57 59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38

39 40 41 42 43 54 57 59 60 62

63

72 8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 60 62 63 72

8 11

12 13 15 17 18 26 30 34 36

37

38 39 40 41 42 43 54 57 59 60

62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59 60 62 63 72 8

11

12

13

15 17 18 26 30 34 36 37 38 39 40 41 42

43 54 57 59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42

43 54 57 59 60 62 63 72

8 11 12 13 15 17 18 26 30 34 36 37 38

39 40 41 42 43 54 57 59 60 62

63

72

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

25 26 27 29 34 36 37 56 60 62 47 48 60 62

20 21 22 23 55 60

27 28 60 62

27 28 60 62 8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

39 40 41 56 60

25 26 27 29 34 36 37 56 60 62

25 26 27 29 34 36 37 56 60 62

25 26 27 29 34 36 37 56 60 62

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

16 17 32 43 49 50 54 56 57 59 60 62

8 11 56 60

39 40 41 56 60

39 40 41 56 60

8 55 56 57 60 62

8 12 13 17 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

39 40 41 56 60

39 40 41 56 60

39 40 41 56 60

39 40 41 56 60

39 40 41 56 60

32 33 45 47 52 53 56 60 62

16 17 32 43 49 50 54 56 57 59 60 62

39 40 41 56 60

39 40 41 56 60

16 17 32 43 49 50 54 56 57 59 60 62

16 17 32 43 49 50 54 56 57 59 60 62

16 17 32 43 49 50 54 56 57 59 60 62

16 17 32 43 49 50 54 56 57 59 60 62

16 17 32 43 49 50 54 56 57 59 60 62

8 12 13 17 60 62

32 33 45 47 52 53 56 60 62

8 11 56 60

40 47 48 60 62

30 39 60 62

54 58 60 62

20 21 22 23 55 60

17 18 25 26 60 62

17 18 25 26 60 62

17 18 25 26 60 62

17 19 20 21 22 23 40 51 60 68

8 55 56 57 60 62

17 18 25 26 60 62

27 28 60 62

17 19 20 21 22 23 40 51 60 68

8 10 40 50 60 62

8 10 40 50 60 62

8 10 40 50 60 62

8 10 40 50 60 62

54 58 60 62 54 58 60 62

17 19 20 21 22 23 40 51 60 68

30 39 60 62

30 39 60 62

47 48 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

39 49 50 51 53 60 62

39 49 50 51 53 60 62

47 48 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

27 39 40 47 48 54

60 62

27 39 40 47 48 54 60 62

20 21 22 23 55 60

27 39 40 47 48 54 60 62

27 39 40 47 48 54 60 62

27 39 40 47 48 54 60 62

8 11 56 60

39 49 50 51 53 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

39 52 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

39 40 41 56 60

39 40 41 56 60

27 39 40 47 48 54 60 62

17 19 20 21 22 23 40 51 60 68

27 39 40 47 48 54 60 62

39 52 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

6 8 11 15 16 17 36 40 49 53 56 57 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

34 51 52 60

16 17 32 43 49 50 54 56 57 59 60 62

20 21 22 23 55 60

39 49 50 51 53 60 62

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

15 18 19 34 38 39 56 60 62 63

15 18 19 34 38 39 56 60 62 63

8 11 14 18 44 55 56 57 60 62

8 11 14 18 44 55 56 57 60 62

17 19 20 21 22 23 40 51 60 68

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

28 60

32 33 45 47 52 53 56 60 62

32 33 45 47 52 53 56 60 62

32 33 45 47 52 53 56 60 62

16 17 32 43 49 50 54 56 57 59 60 62

16 17 32 43 49 50 54 56 57 59 60 62

16 17 32 43 49 50 54 56 57 59 60 62

34 51 52 60

24 51 60

16 55 60

8 55 56 57 60 62

8 55 56 57 60 62

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

17 19 20 21 22 23 40 51 60 68

16 55 60

39 52 60 62

39 49 50 51 53 60

62

17 30 33 34 35 36

38 44 46

47 48 57

59 60 62

63

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

8 12 13 17 60 62

17 30 33 34 35 36 38 44 46 47 48 57 59 60

62 63

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

34 51 52 60

34 51 52 60

32 33 45 47 52 53 56 60 62

32 33 45 47 52 53 56 60 62

32 33 45 47 52 53 56 60 62

39 40 41 56 60

39 40 41 56 60

8 11 56 60

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 62 72

27 62

25 26 27 29 34 36 37 56 60 62

25 26 27 29 34 36 37 56 60 62

25 26 27 29 34 36 37 56 60 62

28 60

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MAKE_BASE

Memory Bit/Byte Swizzle

MAKE_BASEMAKE_BASE

LPDDR3 Command/Address


Signal Aliases

MEM_B_DQ<32>TRUE

MEM_B_DQ<44>TRUE=MEM_B_DQ<32>

=MEM_A_DQ<29>

TP_LPDDR3_RSVD1

MEM_B_CAB<4>TRUE

=MEM_B_A<15>

=MEM_B_A<11>

=MEM_A_A<2>

TRUE MEM_A_CAB<2>

TRUE MEM_A_CAB<5>

TRUE MEM_A_ODT<0>

TP_LPDDR3_RSVD1TRUE

TRUE TP_LPDDR3_RSVD3


TRUE MEM_B_ODT<0>

MEM_B_CAA<0>TRUE

MEM_B_CAA<1>TRUE

MEM_B_CAA<2>TRUE

TRUE MEM_B_CAA<3>

MEM_B_CAA<5>TRUE

MEM_B_CAA<4>TRUE

MEM_B_CAA<6>TRUE

MEM_B_CAA<7>TRUE

MEM_B_CAA<8>TRUE

MEM_B_CAA<9>TRUE

MEM_B_CAB<0>TRUE

MEM_B_CAB<1>TRUE

MEM_B_CAB<2>TRUE

MEM_B_CAB<3>TRUE

MEM_B_CAB<6>TRUE

MEM_B_CAB<8>TRUE

MEM_B_CAB<9>TRUE


TRUE MEM_A_CAB<1>

TRUE MEM_A_CAB<3>

TRUE MEM_A_CAB<8>

TRUE MEM_A_CAB<9>

TRUE MEM_A_CAB<7>

MEM_A_CAA<7>TRUE

MEM_A_CAA<9>TRUE

MEM_A_CAA<8>TRUE

MEM_A_CAB<0>TRUE

TRUE MEM_A_CAB<4>

MEM_A_CAA<1>TRUE

MEM_A_CAA<0>TRUE

TRUE MEM_A_CAA<3>

MEM_A_CAA<4>TRUE

TRUE MEM_A_CAA<6>

TRUE MEM_A_CAB<6>

MEM_B_CAB<7>TRUE

TRUE MEM_B_CAB<5>

TP_LPDDR3_RSVD3

TP_LPDDR3_RSVD4

MEM_A_ODT<0>

=MEM_B_A<5>

=MEM_B_A<9>

=MEM_B_A<6>

=MEM_B_A<8>

=MEM_B_BA<2>

=MEM_B_A<7>

=MEM_B_A<14>

=MEM_B_A<13>

=MEM_B_CAS_L

=MEM_B_WE_L

=MEM_B_RAS_L

=MEM_B_BA<0>

=MEM_B_A<2>

MEM_B_CAB<6>

=MEM_B_A<10>

=MEM_B_A<1>

=MEM_B_A<0>

TP_LPDDR3_RSVD2

=MEM_A_A<15>

=MEM_A_A<1>

=MEM_A_A<0>

=MEM_A_A<11>

=MEM_A_A<13>

=MEM_A_CAS_L

=MEM_A_RAS_L

=MEM_A_BA<0>

=MEM_A_A<9>

=MEM_A_A<6>

=MEM_A_A<5>

=MEM_A_A<8>

=MEM_A_A<7>

MEM_A_CAA<6>

=MEM_A_A<10>

=MEM_A_BA<2>

=MEM_A_A<14>

=MEM_A_WE_L

MEM_B_CAA<6>

MEM_A_CAB<6>

MEM_B_ODT<0>





MEM_B_DQ<14>TRUE







TRUE MEM_B_DQ<7>=MEM_B_DQ<11>

MEM_A_DQ<12>TRUE=MEM_A_DQ<1>


TRUE MEM_A_DQ<13>=MEM_A_DQ<5>


MEM_A_DQ<14>TRUE

MEM_A_DQ<10>TRUE


MEM_A_DQ<1>TRUE



=MEM_A_DQ<11>

MEM_A_DQ<0>TRUE

MEM_B_DQ<4>TRUE


















=MEM_B_DQ<31>


MEM_B_DQ<47>TRUE


MEM_B_DQ<33>TRUEMEM_B_DQ<33>

MEM_B_DQ<46>TRUE













=MEM_A_DQ<16>








=MEM_A_DQ<22>




MEM_A_DQ<21>TRUE

TRUE MEM_A_DQ<19>



MEM_A_DQ<17>TRUE



=MEM_A_DQ<33>

=MEM_A_DQ<34>


=MEM_A_DQ<35>







MEM_A_DQ<33>TRUE

=MEM_A_DQ<46>


MEM_A_DQ<39>TRUE

MEM_A_DQ<32>TRUEMEM_A_DQ<32>

















MEM_B_DQS_P<1>TRUE=MEM_B_DQS_P<0>

MEM_B_DQS_N<0>TRUE=MEM_B_DQS_N<1>










TRUE MEM_B_DQS_N<7>=MEM_B_DQS_N<6>



MEM_B_DQS_P<6>TRUEMEM_B_DQS_P<6>

MEM_B_DQS_N<6>TRUEMEM_B_DQS_N<6>












MEM_A_DQS_P<0>TRUE=MEM_A_DQS_P<1>

MEM_A_DQS_N<0>TRUE=MEM_A_DQS_N<1>










MEM_A_DQS_N<6>TRUEMEM_A_DQS_N<6>

MEM_A_DQS_P<6>TRUEMEM_A_DQS_P<6>




MEM_A_DQ<26>TRUE

MEM_A_DQ<7>TRUE

=MEM_A_DQ<9>

=MEM_A_DQ<8>

=MEM_A_DQ<6>

=MEM_A_DQ<2>

TRUE MEM_A_DQ<44>

MEM_A_DQ<35>TRUE

=MEM_A_DQ<45>

=MEM_A_DQ<25>

MEM_A_CAA<5>TRUE

MEM_A_CAA<2>TRUE

=MEM_A_DQ<31>

=MEM_A_DQ<43>

MEM_A_DQ<47>TRUE

MEM_A_DQ<46>TRUE

=MEM_B_DQ<33>

MEM_B_DQ<19>TRUE

MEM_B_DQ<21>TRUE

=MEM_B_DQ<12>

=MEM_B_DQ<6>

MEM_A_DQ<29>TRUE

=MEM_B_DQ<37>

=MEM_B_DQ<40>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

MEM_B_DQ<40>TRUE

MEM_B_DQ<45>TRUE

MEM_B_DQ<43>TRUE

MEM_B_DQ<41>TRUE

=MEM_B_DQ<28>

<BRANCH>

<SCH_NUM>

<E4LABEL>

102 OF 120

61 OF 73

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20

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7 23 61 68 7 23 61 68

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7 21 61 68 7 21 61 68

7 21 61 68 7 21 61 68

7 68 21

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7 68

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20

20

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21

20

20 24 68

20 24 68

20

21

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22

w w w

. c h

i n a

f i x

. c o

m

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Unused nets with offpage(Nets with offpages not used on this project)

(Need 4 TPs)

(Need to add 5 GND TPs)

J7000: DC-In Connector


J6404: Speaker Connector

(Need 2 TPs)

FUNC_TEST

J7050 and 1 for shield)



(Only a subset are needed

for FCT HVM test fixture)

J1800: XDP Connector

FUNC_TEST

J7715: KB BKLT Connector


FUNC_TEST

TBT


FUNC_TEST

(Need TBD TPs)

(Need 6 TPs)

(Need 2 TPs)

(Need to add TBD GND TPs)

J4002: Camera Connector

FUNC_TEST

J3700: SSD Connector

FUNC_TEST


FUNC_TEST

J6100: LPC+SPI Connector

SMC

NO_TEST Nets

MAKE_BASENO_TEST

CPU/PCH

J6950: Battery Connector


J8300: Internal DP Connector

(Need to add 4 GND TPs near


FUNC_TEST

FUNC_TEST

J6000: Fan Connector

Functional Test Points

FUNC_TEST FUNC_TEST

Misc Voltages & Control Signals

(Need 3 TPs)

(Need 4 TPs)

(Need 5 TPs)

(Need to add 1 GND TP)

FUNC_TEST

FUNC_TEST

J4800: IPD Flex Connector

J3501: AirPort / BT Connector


I776

I777

I778

I779

I780

I781

I782

I783

I784

I785

I786

I787

I788

I789

I790

I791

I792

I793

Func Test / No Test


PCH_BT_UART_CTS_L

AUD_SPI_CS_L

PCH_BT_UART_D2R

PCH_BT_UART_R2D

PCH_BT_UART_RTS_L

AUD_SPI_MISO

AUD_SPI_CLK

TRUE PP1V05_TBTCIO

TRUE PPDCIN_G3H

TRUE USB_BT_CONN_P

TRUE USB_BT_CONN_N

TRUE PP3V3_S4

TRUE PCIE_AP_R2D_N

TRUE USB_TPAD_N

TRUE TPAD_SPI_CS_R_LTRUE PP3V3_S4_IPDTRUE TPAD_SPI_MOSI_RTRUE TPAD_WAKE_LTRUE TPAD_SPI_CLK_R

TRUE USB_TPAD_PTRUE TPAD_SPI_MISO_R

SMC_LIDTRUE

TRUE TPAD_SPI_IF_EN_CONN

TRUE PCIE_WAKE_L

AP_CLKREQ_Q_LTRUE

SMC_LSOC_RST_LTRUE

PP5V_S0TRUE

TRUE PCIE_SSD_R2D_P<3..0>

TRUE PP3V3_S0

SMC_OOB1_R2D_CONN_LTRUE

TRUE PPVBAT_G3H_CONN

HDMITBTMUX_FLAG

FW_PWR_EN

LCD_IRQ_L

LCD_PSR_EN

ENET_MEDIA_SENSE

FW_PME_L

AP_PCIE_DEV_WAKE

TRUE PPVIN_S4SW_TBTBST_FET

NC_DP_TBTPB_AUXCH_CN NC_DP_TBTPB_AUXCH_CNTRUE TRUE

NC_DP_TBTPB_ML_CN<3..1:2> TRUE TRUE NC_DP_TBTPB_ML_CN<3..1:2>

NC_DP_TBTPB_AUXCH_CP TRUE TRUE NC_DP_TBTPB_AUXCH_CP

NC_DP_TBTPB_ML_CP<3..1:2> TRUE TRUE NC_DP_TBTPB_ML_CP<3..1:2>

NC_TBT_B_LSTX TRUE TRUE NC_TBT_B_LSTX

TBT_B_D2R_N<1..0> TRUE TRUE NC_TBT_B_D2RN<1..0>

TBT_B_R2D_C_P<1..0> TRUE TRUE NC_TBT_B_R2D_CP<1..0>

TBT_B_D2R_P<1..0> TRUE TRUE NC_TBT_B_D2RP<1..0>

TBT_B_R2D_C_N<1..0> TRUE TRUE NC_TBT_B_R2D_CN<1..0>

NC_SMC_T25_EN_L

NC_PCI_PME_L

NC_CLINK_DATA

NC_CLINK_RESET_L

NC_SMC_FAN_1_CTL

NC_ENET_ASF_GPIO

TRUETRUE NC_SMBUS_SMC_4_ASF_SDA

TRUE PP3V3_S0SW_SSD

TRUE PP3V3_SUS

TRUE PP1V5_S0

TRUE PP3V3_S0

TRUE PPBUS_G3H

TRUE PPBUS_S5_HS_COMPUTING_ISNS

PP3V42_G3HTRUE

TRUE PP5V_S4_IPDTRUE TPAD_SPI_INT_S4_WAKE_L_CONN

TRUE TPAD_USB_IF_EN_CONN

FAN_RT_TACHTRUE

FAN_RT_PWMTRUE

SMBUS_SMC_5_G3_SCLTRUE

TRUE PP5V_S4RS3

SPKRAMP_ROUT_PTRUE

TRUE SPKRAMP_ROUT_N

TRUE PP3V42_G3H

SMC_ONOFF_LTRUE

TRUE PP3V3_S0SW_LCD_UF

DP_INT_HPD_CONNTRUE

LED_RETURN_2TRUE

TRUE PPHV_S0SW_LCDBKLT

TRUE DP_INT_ML_N<0>TRUE DP_INT_ML_P<0>

TRUE TRUE NC_PCIE_CLK100M_SDPNC_PCIE_CLK100M_SDP

TRUE TRUE NC_PCIE_CLK100M_SDNNC_PCIE_CLK100M_SDN

TRUE TRUE NC_PCIE_CLK100M_FWPNC_PCIE_CLK100M_FWP

TRUE TRUE NC_PCIE_CLK100M_FWNNC_PCIE_CLK100M_FWN

NC_PCIE_FW_D2RNTRUETRUENC_PCIE_FW_D2RN

NC_PCIE_FW_D2RPTRUE TRUENC_PCIE_FW_D2RP

TRUE TRUE NC_PCIE_FW_R2D_CPNC_PCIE_FW_R2D_CP

NC_PCIE_FW_R2D_CNTRUE TRUENC_PCIE_FW_R2D_CN

TRUE TRUE NC_USB_IRNNC_USB_IRNTRUE TRUE NC_USB_IRPNC_USB_IRP

TRUE NC_USB_CAMERAPTRUENC_USB_CAMERAP

TRUE TRUE NC_USB_CAMERANNC_USB_CAMERAN

TRUE TRUE NC_USB_SDPNC_USB_SDP

NC_INT_ML_CP<3..1>TRUETRUEDP_INT_ML_C_P<3..1>TRUE TRUE NC_USB_SDNNC_USB_SDN

NC_INT_ML_CN<3..1>TRUE TRUEDP_INT_ML_C_N<3..1>

TRUE TRUE NC_HDA_SDIN1NC_HDA_SDIN1

TRUE TRUE NC_PCI_PME_L

TRUE TRUE NC_CLINK_CLKNC_CLINK_CLK

NC_CLINK_DATATRUE TRUE

TRUE TRUE NC_CLINK_RESET_L

TRUE TRUE NC_SMC_SYS_LEDNC_SMC_SYS_LED

TRUE TRUE NC_IR_RX_OUT_RCNC_IR_RX_OUT_RC

NC_USB_SMCPTRUE TRUENC_USB_SMCP

NC_USB_SMCNTRUE TRUENC_USB_SMCN

NC_SMC_GFX_OVERTEMPTRUE TRUENC_SMC_GFX_OVERTEMP

NC_SMC_GFX_THROTTLE_LTRUETRUENC_SMC_GFX_THROTTLE_L

NC_SMC_FAN_1_CTLTRUE TRUE

NC_SMC_FAN_5_CTLTRUETRUENC_SMC_FAN_5_CTL

NC_SMC_FAN_1_TACHTRUETRUENC_SMC_FAN_1_TACH

TRUETRUE NC_ENET_ASF_GPIO

TRUE NC_SMC_MPM5_LED_PWRTRUENC_SMC_MPM5_LED_PWR

TRUETRUE NC_SMC_MPM5_LED_CHGNC_SMC_MPM5_LED_CHG

TRUE NC_SMC_DP_HPD_LTRUENC_SMC_DP_HPD_LTRUETRUE NC_SMC_T25_EN_L

TRUETRUE NC_SMBUS_SMC_4_ASF_SCLNC_SMBUS_SMC_4_ASF_SCL

NC_SMBUS_SMC_4_ASF_SDA

TRUETRUE NC_BDV_BKL_PWMNC_BDV_BKL_PWM

TRUE DP_INT_AUX_CH_C_N

I2C_TCON_SCL_RTRUE

TRUE PCIE_SSD_R2D_N<3..0>

PCIE_AP_D2R_NTRUE

TRUE PCIE_AP_D2R_P

TRUE PP3V3_S0SW_SSD_FLT

TRUE PP3V3_WLAN

TRUE PCIE_CLK100M_AP_NTRUE PCIE_AP_R2D_P

TRUE WIFI_EVENT_L

TRUE MIPI_CLK_CONN_PTRUE MIPI_CLK_CONN_N

TRUE CAM_SENSOR_WAKE_L_CONN

TRUE PCIE_SSD_D2R_P<3..0>

TRUE SMC_PWRFAIL_WARN_LTRUE SSD_SR_EN_LTRUE SSD_PCIE_SEL_LTRUE SMC_OOB1_D2R_CONN_L

TRUE SSD_RESET_CONN_L

SSD_CLKREQ_CONN_LTRUE

TRUE PCIE_CLK100M_SSD_N

TRUE PCIE_CLK100M_SSD_P

MIPI_DATA_CONN_NTRUE

TRUE MIPI_DATA_CONN_P

TRUE SMBUS_SMC_1_S0_SCLTRUE SMBUS_SMC_1_S0_SDA

TRUE I2C_CAM_SCK

TRUE I2C_CAM_SDA

TRUE PP5V_S3RS0_ALSCAM_F

TP_SMC_MD1TRUE

TRUE SMC_TX_L

TRUE LPC_FRAME_L

SPI_ALT_IO1_MISOTRUE

TRUE PM_CLKRUN_LTRUE SPIROM_USE_MLB

TRUE SPI_ALT_CLK

TRUE LPC_SERIRQTRUE SPI_ALT_CS_L

TRUE LPC_PWRDWN_L

TRUE SMC_TDI

TRUE SMC_TCK

TRUE SMC_RESET_L

TRUE SMC_ROMBOOT

SMC_RX_LTRUE

TRUE PP3V3_S5

TRUE PP3V3_S3

TRUE PP15V_TBT

TRUE PP3V3_TBTLC

PP1V05_TBTTRUE

TRUE LED_RETURN_3

TRUE LED_RETURN_5TRUE LED_RETURN_6

TRUE PPBUS_S5_HS_OTHER_ISNS

TRUE PPDCIN_G3H

PPVRTC_G3HTRUE

AUD_I2C_INT_L

AUD_IP_PERIPHERAL_DET

ENET_LOW_PWR

SMBUS_SMC_5_G3_SDATRUE

ODD_PWR_EN_L

PP1V05_S0TRUE

TRUE PPVCC_S0_CPU

TRUE PPDCIN_G3H_ISOL

TRUE PP3V3_S4







NC_DP_TBTSRC_ML_CP<1>

NC_DP_TBTSRC_ML_CN<1>

NC_DP_TBTSRC_AUXCH_CP

NC_DP_TBTSRC_AUXCH_CN NC_DP_TBTSRC_AUXCH_CNTRUE TRUE

NC_DP_TBTSRC_AUXCH_CPTRUE TRUE

NC_DP_TBTSRC_ML_CN<1>TRUE TRUE

NC_DP_TBTSRC_ML_CP<1>TRUE TRUE

TRUE NC_DP_TBTSRC_ML_CN<0>TRUE

TRUE NC_DP_TBTSRC_ML_CP<0>TRUE





KBDLED_ANODETRUE

TRUE KBDLED_FB

TRUE XDP_CPU_TDOTRUE XDP_CPU_TDI

TRUE XDP_CPU_TMSTRUE XDP_CPUPCH_TRST_L

TRUE XDP_PCH_TDITRUE XDP_PCH_TMS

TRUE XDP_CPU_PREQ_LTRUE XDP_PCH_TDO

TRUE XDP_CPU_VCCST_PWRGDTRUE XDP_CPU_PRDY_L

TRUE XDP_SYS_PWROKTRUE PM_RSMRST_L

TRUE CPU_CFG<3>TRUE PM_SYSRST_L

TRUE XDP_CPU_TCK

TRUE XDP_PCH_TCK

TRUE PP1V05_S0

TRUE GND

TRUE LPCPLUS_RESET_L

SMC_TDOTRUE

TP_SMC_TRST_LTRUE

TRUE XDP_LPCPLUS_GPIO

TRUE DP_INT_AUX_CH_C_P

TRUE I2C_TCON_SDA_R

TRUE SYS_DETECT_L

LED_RETURN_1TRUE

TRUE LED_RETURN_4

LPC_AD<3..0>TRUE

SPI_ALT_IO0_MOSITRUE

TRUE PCIE_SSD_D2R_N<3..0>TRUE SSD_PWR_EN

SMBUS_SMC_3_SCLTRUE

TRUE AP_RESET_CONN_L

TRUE SMBUS_SMC_3_SDA

TRUE PCIE_CLK100M_AP_P

HDMITBTMUX_LATCH

HDD_PWR_EN

WOL_EN

BT_PWRRST_L

AUD_SPI_MOSI

SMC_TMSTRUE

SPI_ALT_IO2_WP_LTRUE

SPI_ALT_IO3_HOLD_LTRUE

<BRANCH>

<SCH_NUM>

<E4LABEL>

104 OF 120

62 OF 73

15

15

15

15

15

15

15

26 60

47 48 60 62

29 66

29 66

25 26 27 29 34 36 37 56 60 62

29 67

14 34 66

34

34

34

34

34

14 34 66

34

34 35 36 46

34

13 29 31

29

34 36

16 17 32 43 49 50 54 56 57 59 60

30 65

8 11 12 13 15 17 18 26 30 34 36 37 38 39

40 41 42 43 54 57 59

60 62 63 72

30

46 48

13

15

15

15

13

27 60

25 62 69 25 62 69

62 69 62 69

25 62 69 25 62 69

62 69 62 69

25 62 25 62

69 25

69 25

69 25

69 25

35 62

13 62

14 62

14 62

35 62

62

35 62

30 39 60

8 11 14 18 44 55 56 57 60

8 55 56 57 60

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 63 72

27 39 40 47 48 54 60

39 49 50 51 53 60

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

34

34

34

43

43

35 38 46 48 71

32 33 45 47 52 53 56 60

45 72

45 72

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

34 35 36

58

58

54 58

54 58 60

58 65

58 65

62 62

62 62

12 62 12 62

12 62 12 62

14 62 14 62

14 62 14 62

14 62 14 62

14 62 14 62

14 62 14 62

14 62 14 62

14 62 14 62

14 62 14 62

14 62 14 62

5 65

14 62 14 62

5 65

12 62 12 62

13 62

14 62 14 62

14 62

14 62

35 62 35 62

62 62

62 62

62 62

35 62 35 62

35 62 35 62

35 62

35 62 35 62

35 62 35 62

62

62 62

62 62

35 62 35 62

35 62

35 62 35 62

35 62

35 62 35 62

58 65

58

30 65

14 29 67

14 29 67

30

29 35 36 37 39

12 29 67

29 67

29 35 36

32 70

32 70

32

12 30 65

30 35

15 30

30

30

30

30

12 30 65

12 30 65

32 70

32 70

14 32 35 38 41 42 67 71

14 32 35 38 41 42 67 71

31 32

31 32

32

35 36

14 35 67

44

13 35

15 44

44

15 35

44

13 35

35 36

35 36 44

35 36 44 48

35 36

8 11 13 15 16 17 18 28 29 40 52 55 56 57 58 60 72

15 18 19 34 38 39 56 60 63

27 28 60

17 18 25 26 60

26

54 58

54 58

54 58

39 52 60

47 48 60 62

8 12 13 17 60

13

35 38 46 48 71

13

6 8 11 15 16 17 36 40 49 53 56 57 60 62

8 10 40 50 60

40 47 48 60

25 26 27 29 34 36 37 56 60 62

25

25

25

25

25

25

25 62

25 62

25 62

25 62 25 62

25 62

25 62

25 62

54

54

6 16 65

6 16 65

6 16 65

6 12 16 65

12 16 67

12 16 67

6 16 65

12 16 67

16

6 16 65

16

13 57

6 16 65

13 17 35

6 16 65

12 16 67

6 8 11 15 16 17 36 40 49 53 56 57 60 62

67

35 36

15 16

58 65

58

46

54 58

54 58

14 35 67

44

12 30 65

15 30 56 57

34 35 38 42 71

29

34 35 38 42 71

12 29 67

13

15

14

15

15

35 36 44

44

44

w w w

. c h

i n a

f i x

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TP

TP

TP

TP

TP

TP

TP

TP

Apple Inc.


124578

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6 3



FUNC_TEST

J6955: HALL EFFECT Connector


J9500: LIO Connector

Power AliasesNO_TEST NetsFunctional Test Points

Bead Probes

NO_TESTMAKE_BASE

FUNC_TEST

Unused nets with offpage(Nets with offpages not used on this project)

CPU/PCH

SMC

1BPA522BEAD-PROBESM

1BPA523BEAD-PROBESM

1BPA512BEAD-PROBESM

1BPA521BEAD-PROBESM

1BPA513BEAD-PROBESM

1BPA520BEAD-PROBESM

1BPA510BEAD-PROBESM

1BPA511BEAD-PROBESM

Project FCT/NC/Aliases


NC_SMC_ADC16 NC_SMC_ADC16TRUETRUE

NC_USB3RPCIE_SD_R2D_CNTRUE TRUENC_USB3RPCIE_SD_R2D_CN

NC_USB3RPCIE_SD_R2D_CP

NC_USB3RPCIE_SD_D2RPTRUE TRUE

NC_USB3RPCIE_SD_D2RNTRUETRUE

NC_USB3RPCIE_SD_R2D_CPTRUETRUE

NC_USB3RPCIE_SD_D2RP

USB3_EXTB_D2R_N

USB3_EXTB_D2R_P

USB3_EXTB_D2R_RC_N

USB3_EXTB_D2R_RC_P

USB3_EXTB_R2D_C_N

USB3_EXTB_R2D_N

USB3_EXTB_R2D_C_P

NC_USB3RPCIE_SD_D2RN

USB3_EXTB_R2D_P

PP3V3_S3 PP3V3_S3


SD_RESET_L

SD_PWR_EN

SMC_BC_ACOKTRUE

SYS_ONEWIRETRUE

SMBUS_SMC_2_S3_SDATRUE

SMBUS_SMC_2_S3_SCLTRUE

TRUE PP3V42_G3H

USB3_EXTB_R2D_PTRUE

USB3_EXTB_R2D_NTRUE

USB_EXTB_PTRUE

USB_EXTB_NTRUE

TRUE USB3_EXTB_D2R_RC_PTRUE USB3_EXTB_D2R_RC_NTRUE SPKRAMP_INR_PTRUE SPKRAMP_INR_NTRUE PP3V3_S0

PP1V5_S0SW_AUDIOTRUE

TRUE SPKRAMP_SHDN_LTRUE PP5V_S0_ALT_AUD_LDO_ENTRUE AUD_PWR_EN

TRUE HDA_SDIN0TRUE HDA_SDOUT

HDA_RST_LTRUE

HDA_SYNCTRUE

TRUE FINSTACKSNS_ALERT_L

USB_PWR_ENTRUE

XDP_USB_EXTB_OC_LTRUE

HDA_BIT_CLKTRUE

SMC_LID_RTRUE

TRUE PP3V42_G3H

<BRANCH>

<SCH_NUM>

<E4LABEL>

105 OF 120

63 OF 73

35 37 63 35 37 63

14 63 66 14 63 66

14 63 66

14 63 66

14 63 66

14 63 66

14 63 66

14 59 66

14 59 66

59 63 66

59 63 66

14 59 66

59 63 66

14 59 66

14 63 66

59 63 66

15 18 19 34 38 39 56 60 62 63 15 18 19 34 38 39 56 60 62 63

15 16

15

15

35 36 48 59

35 59

35 38 59 71

35 38 59 71

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

59 63 66

59 63 66

14 59 66

14 59 66

59 63 66

59 63 66

45 59 72

45 59 72

8 11 12 13 15 17 18 26 30 34 36 37 38 39 40 41 42 43 54 57 59

60 62 72

56 59

45 59

59

13 57 59

12 59 67

12 59 67

12 59 67

12 59 67

37 59

33 57 59

14 16 59

12 59 67

46

17 30 33 34 35 36 38 44 46 47 48 57 59 60 62 63

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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD






























TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS



TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM









LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD







AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD

PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD

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J41/J43 Board-Specific Spacing & Physical Constraints

Differential Pair Physical Constraints

Single-ended Physical Constraints Spacing Constraints

Y 0.115 MM0.115 MM0.081 MM0.081 MM80_OHM_DIFF ISL2,ISL11

0.115 MM0.115 MM0.081 MM0.081 MMYISL3,ISL1080_OHM_DIFF

0.110 MM0.110 MM0.088 MM0.088 MMYISL4,ISL980_OHM_DIFF

100 MMN* =STANDARD =STANDARD80_OHM_DIFF 100 MM =STANDARD


PCB Rule Definitions

=STANDARD =STANDARD45_OHM_SE =STANDARD* N 100 MM 100 MM

0.080 MM45_OHM_SE ISL4,ISL9 Y 0.080 MM

ISL3,ISL1040_OHM_SE Y 0.096 MM0.096 MM

=STANDARD =STANDARD=STANDARD100 MM35_OHM_SE * N 100 MM

0.125 MM 0.125 MM35_OHM_SE ISL4,ISL9 Y

35_OHM_SE 0.125 MM0.125 MMISL3,ISL10 Y

* 0.070 MM 0.075 MM5 MMP070MM_BGA

100 MM =STANDARD40_OHM_SE =STANDARD=STANDARD* N 100 MM

0.170 MM40_OHM_SE YTOP,BOTTOM 0.170 MM

55_OHM_SE 0.090 MMYTOP,BOTTOM 0.090 MM

YISL3,ISL10 0.150 MM 0.150 MM73_OHM_DIFF 0.106 MM 0.106 MM

0.115 MM0.115 MM 0.200 MM0.200 MM90_OHM_DIFF YTOP,BOTTOM

0.180 MM0.180 MM0.070 MM 0.070 MM90_OHM_DIFF ISL2,ISL11 Y

0.096 MM40_OHM_SE YISL2,ISL11 0.096 MM

100 MM100 MM85_OHM_DIFF =STANDARD=STANDARD=STANDARD* N

0.140 MM0.140 MM0.082 MM0.082 MM85_OHM_DIFF ISL4,ISL9 Y

0.160 MM0.160 MM0.078 MM0.078 MM85_OHM_DIFF YISL3,ISL10


0.120 MM0.120 MM85_OHM_DIFF TOP,BOTTOM Y 0.150 MM 0.150 MM

0.150 MM0.150 MMTOP,BOTTOM Y73_OHM_DIFF 0.165 MM 0.165 MM

100 MM 100 MMN* =STANDARD =STANDARD =STANDARD73_OHM_DIFF



0.075 MM 0.075 MM45_OHM_SE YISL2,ISL11

DEFAULT =45_OHM_SE=45_OHM_SEYISL4,ISL9

* BGA P070MM_BGA

?TOP,BOTTOM1x_DIELECTRIC 0.071 MM

1x_DIELECTRIC ?ISL3,ISL10 0.053 MM

?0.050 MMISL4,ISL91x_DIELECTRIC

?0.1 MM*DEFAULT

1x_DIELECTRIC ?0.090 MM*

?*1:1_SPACING 0.100 MM

=DEFAULT =DEFAULT=DEFAULT=DEFAULT*STANDARD =DEFAULT=DEFAULT

0.099 MMISL4,ISL9 Y40_OHM_SE 0.099 MM

?=DEFAULT*STANDARD

TOP,BOTTOM 0.310 MM 0.310 MM27P4_OHM_SE Y

?*BGA_P075MM 0.075 MM

* * BGA_P075MMBGA

0 MMDEFAULT * N 100 MM100 MM 10 MM 0 MM

0.135 MM45_OHM_SE YTOP,BOTTOM 0.135 MM

NO_TYPE,BGA,MEM_TERMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM MM 16.2

Y =50_OHM_SEDEFAULT =50_OHM_SETOP,BOTTOM

=45_OHM_SE=45_OHM_SEYDEFAULT ISL2,ISL11

=45_OHM_SE=45_OHM_SEYISL3,ISL10DEFAULT

ISL2,ISL1127P4_OHM_SE Y 0.182 MM0.182 MM

27P4_OHM_SE ISL3,ISL10 Y 0.182 MM 0.182 MM

=STANDARD =STANDARD =STANDARD100 MM100 MM*27P4_OHM_SE N

0.195 MM 0.195 MMYTOP,BOTTOM35_OHM_SE

27P4_OHM_SE YISL4,ISL9 0.182 MM0.182 MM

ISL2,ISL11 0.125 MMY35_OHM_SE 0.125 MM

0.075 MM 0.075 MM45_OHM_SE ISL3,ISL10 Y

0.110 MMTOP,BOTTOM Y50_OHM_SE 0.110 MM

0.110 MM0.110 MM0.165 MM0.165 MMTOP,BOTTOM70_OHM_DIFF Y

0.076 MM0.076 MM 0.180 MM 0.180 MM90_OHM_DIFF ISL4,ISL9 Y

100 MM90_OHM_DIFF * 100 MM =STANDARD=STANDARD=STANDARDN


0.132 MMTOP,BOTTOM 0.130 MM0.130 MM0.132 MMY80_OHM_DIFF

100 MM 100 MM =STANDARD70_OHM_DIFF N* =STANDARD =STANDARD

0.110 MM 0.095 MM0.095 MM0.110MM70_OHM_DIFF YISL4,ISL9

0.100 MM0.100 MM0.105 MM0.105 MMISL2,ISL1170_OHM_DIFF Y

0.105 MM 0.100 MM0.100 MM0.105 MMYISL3,ISL1070_OHM_DIFF

=STANDARD100 MM100 MMN* =STANDARD55_OHM_SE =STANDARD

50_OHM_SE =STANDARD =STANDARD=STANDARD* N 100 MM 100 MM

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(FSB_CPURST_L)

CPU PCIE Spacing

CPU Signal Constraints

PCIE Clock Spacing

PCH PCIE Spacing

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

Note: CPU_8MIL and CPU_ITP can be converted

back to TABLE_SPACING_RULE

once rdar://10308147 is resolved

Note: DisplayPort tables are on Page 113DP

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

SPACING

PCIe SSD

PCI-Express Interface Constraints

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I214

I215

SYNC_MASTER=J43_MLB

CPU Constraints


PCIE_RX2OTHERRX ?TOP,BOTTOM =5x_DIELECTRIC

PCIE_CPU_TX ** PCIE_2OTHER

*PCIE_CPU_TX *_RX PCIE_2OTHERHS

CPU_8MIL CPU_8MIL_2ANY**

?=2x_DIELECTRICCPU_AGTL TOP,BOTTOM

=45_OHM_SE* =STANDARDCPU_45S =45_OHM_SE=45_OHM_SE =45_OHM_SE =STANDARD

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFFCLK_PCIE_80D * =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

CLK_PCIE_2SELF * ?=4x_DIELECTRIC

CPU_8MIL_2ANY ?8 MIL*

=4x_DIELECTRIC* ?CPU_ITP_2ANY

?* =4x_DIELECTRICPCIE_2OTHERHS

PCIE_RX2OTHERRX =4x_DIELECTRIC* ?

PCIE_TX2RX ?=7x_DIELECTRICTOP,BOTTOM

*CLK_PCIE CLK_PCIE CLK_PCIE_2SELF

CLK_PCIE_2OTHER =10x_DIELECTRIC ?TOP,BOTTOM

?*PCIE_TX2RX =6x_DIELECTRIC

=4x_DIELECTRICPCIE_TX2OTHERTX * ?

=2.5x_DIELECTRICPCIE_RX2RX ?*

?PCIE_TX2TX =2.5x_DIELECTRIC*

TOP,BOTTOMPCIE_2OTHER =5x_DIELECTRIC ?

PCIE_2OTHERHS TOP,BOTTOM ?=6x_DIELECTRIC

PCIE_RX2TX TOP,BOTTOM ?=7x_DIELECTRIC

PCIE_TX2OTHERTX ?TOP,BOTTOM =5x_DIELECTRIC

PCIE_TX2TX TOP,BOTTOM =5x_DIELECTRIC ?

PCIE_PCH_TXPCIE_PCH_TX * PCIE_TX2TX

PCIE_RX2RX*PCIE_PCH_RX PCIE_PCH_RX

*PCIE_PCH_TX *_PCH_TX PCIE_TX2OTHERTX

PCIE_PCH_RX * PCIE_RX2OTHERRX*_PCH_RX

PCIE_2OTHERHS*_RX *PCIE_PCH_TX

PCIE_PCH_RX * PCIE_2OTHERHS*_TX

PCIE_PCH_TX PCIE_2OTHERHS**_TX

*_PCH_RX * PCIE_TX2RXPCIE_PCH_TX

*_PCH_TX * PCIE_RX2TXPCIE_PCH_RX

*_RX * PCIE_2OTHERHSPCIE_PCH_RX

PCIE_PCH_TX * PCIE_2OTHER*

PCIE_PCH_RX * * PCIE_2OTHER

PCIE_CPU_RX * PCIE_2OTHER*

PCIE_CPU_RX * PCIE_2OTHERHS*_RX

PCIE_2OTHERHSPCIE_CPU_RX *_TX *

*_CPU_TXPCIE_CPU_TX * PCIE_TX2OTHERTX

*_CPU_RX PCIE_RX2OTHERRX*PCIE_CPU_RX

PCIE_CPU_RX * PCIE_RX2RXPCIE_CPU_RX

PCIE_CPU_TX * PCIE_TX2TXPCIE_CPU_TX

=3x_DIELECTRIC* ?PCIE_2OTHER

*PCIE_RX2TX ?=6x_DIELECTRIC

*CLK_PCIE * CLK_PCIE_2OTHER

=27P4_OHM_SE 0.100 MM*CPU_27P4S =27P4_OHM_SE =27P4_OHM_SE 0.100 MM=27P4_OHM_SE

CPU_VCCSENSE CPU_VCCSENSE_2SELF*CPU_VCCSENSE

PCIE_CPU_TX *_TX * PCIE_2OTHERHS

* PCIE_RX2TXPCIE_CPU_RX *_CPU_TX

PCIE_TX2RX**_CPU_RXPCIE_CPU_TX

CPU_VCCSENSE_2OTHER* *CPU_VCCSENSE

=6x_DIELECTRIC* ?CLK_PCIE_2OTHER

?TOP,BOTTOM =6x_DIELECTRICCPU_VCCSENSE_2SELF

=6x_DIELECTRIC* ?CPU_COMP_2OTHER

=4x_DIELECTRIC* ?CPU_COMP_2SELF

?*CPU_AGTL =STANDARD

CLK_PCIE_2SELF =6x_DIELECTRIC ?TOP,BOTTOM

CPU_VCCSENSE_2OTHER =6x_DIELECTRIC* ?

CPU_VCCSENSE_2SELF =4x_DIELECTRIC* ?

CPU_COMP_2SELF ?TOP,BOTTOM =6x_DIELECTRIC

TOP,BOTTOMCPU_COMP_2OTHER ?=10x_DIELECTRIC

PCIE_RX2RX =5x_DIELECTRIC ?TOP,BOTTOM

CPU_VCCSENSE_2OTHER ?TOP,BOTTOM =10x_DIELECTRIC

* * CPU_ITP_2ANYCPU_ITP

CPU_COMP_2SELF*CPU_COMPCPU_COMP

* * CPU_COMP_2OTHERCPU_COMP

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF*PCIE_80D =80_OHM_DIFF=80_OHM_DIFF

DP_INT_AUX_CH_C_PDP_AUXDP_80DDP_INT_AUXCH

DP_INT_AUXCH DP_80D DP_AUX DP_INT_AUXCH_C_N

DP_80D DP_AUX DP_INT_AUXCH_P

DP_INT_AUXCH DP_INT_AUXCH_C_PDP_AUXDP_80D

DP_INT_AUX_CH_C_NDP_AUXDP_80DDP_INT_AUXCH

DP_INT_ML_C_N<3..0>DP_TXDP_80D

DP_INT_ML_C_P<3..0>DP_TXDP_80D

DP_INT_ML_N<3..0>DP_TXDP_80DDP_INT_ML

DP_INT_ML_P<3..0>DP_TXDP_80DDP_INT_ML

DP_80D DP_TBTSNK1_AUXCH_C_NDP_AUX

DP_TBT_AUXCH DP_80D DP_TBTSNK1_AUXCH_NDP_AUX

DP_80D DP_TBTSNK1_AUXCH_C_PDP_AUX

DP_TBTSNK1_ML_C_N<3..0>DP_80D DP_TX

DP_TBTSNK1_ML_C_P<3..0>DP_80D DP_TX

DP_80D DP_TBTSNK1_AUXCH_PDP_TBT_AUXCH DP_AUX

DP_TBTSNK1_ML_P<3..0>DP_80DDP_TBT_ML DP_TX

DP_TBTSNK1_ML_N<3..0>DP_80DDP_TBT_ML DP_TX

DP_80D DP_TBTSNK0_AUXCH_C_NDP_AUX

DP_80D DP_TBTSNK0_AUXCH_C_PDP_AUX

DP_80D DP_TBTSNK0_AUXCH_PDP_TBT_AUXCH DP_AUX

DP_80D DP_TBTSNK0_AUXCH_NDP_TBT_AUXCH DP_AUX

DP_80D DP_TBTSNK0_ML_C_P<3..0>DP_TX

DP_80DDP_TBT_ML DP_TBTSNK0_ML_N<3..0>DP_TX

DP_80D DP_TBTSNK0_ML_C_N<3..0>DP_TX

DP_80DDP_TBT_ML DP_TBTSNK0_ML_P<3..0>DP_TX

CPU_AXG_VALSENSE_PCPU_VCCSENSECPU_VALSENSE CPU_27P4S

CPU_COMPCPU_SVIDALERT_L CPU_45S CPU_VIDALERT_L

DP_80D DP_AUX DP_INT_AUXCH_N

PCIE_SSD_D2R_C_P<3..0>PCIE_80D PCIE_CPU_RX

PCIE_SSD_D2R_C_N<3..0>PCIE_80D PCIE_CPU_RX

PCIE_SSD_D2R_P<3..0>PCIE_CPU_SSD_D2R PCIE_CPU_RXPCIE_80D

PCIE_SSD_D2R_N<3..0>PCIE_CPU_SSD_D2R PCIE_CPU_RXPCIE_80D

PCIE_CLK100M_SSD PCIE_CLK100M_SSD_PCLK_PCIE_80D CLK_PCIE

PCIE_CLK100M_SSD_NPCIE_CLK100M_SSD CLK_PCIE_80D CLK_PCIE

DPLL_REF_CLKPCLK_PCIEDPLL_REF_CLK120M CLK_PCIE_80D

XDP_CPU_CLK100M_PCLK_PCIEITPCPU_CLK100M CLK_PCIE_80D

XDP_CPU_TDOCPU_ITPXDP_TDO CPU_45S

XDP_CPU_TCKXDP_TCK CPU_45S CPU_ITP

XDP_CPU_TMSCPU_45S CPU_ITPXDP_TMS

PCIE_CPU_TXPCIE_80D PCIE_SSD_R2D_P<3..0>

PCIE_SSD_R2D_N<3..0>PCIE_80D PCIE_CPU_TX

CPU_PECICPU_45S CPU_COMPCPU_PECI

PM_MEM_PWRGDCPU_AGTLPM_MEM_PWRGD CPU_45S

PM_SYNCCPU_AGTLPM_SYNC CPU_45S

XDP_DBRESET_LCPU_ITPCPU_45S

XDP_CPU_PRDY_LCPU_45S CPU_ITP

XDP_CPU_PREQ_LCPU_45S CPU_ITP

EDP_COMPCPU_27P4S CPU_COMP

CPU_PEG_COMPCPU_27P4S CPU_COMP

CPU_SM_RCOMP<0>CPU_COMPCPU_SM_RCOMP CPU_27P4S

CPU_COMP CPU_SM_RCOMP<1>CPU_27P4SCPU_SM_RCOMP

CPU_SM_RCOMP<2>CPU_COMPCPU_SM_RCOMP CPU_27P4S

CPU_CFG<11..0>CPU_ITPCPU_45S

CPU_CATERR_LCPU_AGTLCPU_CATERR_L CPU_45S

CPU_VCCIO_SELCPU_AGTLCPU_45S

CPU_PROCHOT_LCPU_AGTLCPU_PROCHOT_L CPU_45S

CPU_PWRGDCPU_AGTLCPU_PWRGD CPU_45S

PM_THRMTRIP_LCPU_8MILPM_THRMTRIP_L CPU_45S

CLK_PCIE_80D DMI_CLK100M_CPU_PCLK_PCIEDMI_CLK100M

CLK_PCIE ITPXDP_CLK100M_NITPCPU_CLK100M CLK_PCIE_80D

CPU_VCCSENSE_PSENSE_1TO1_P2MM CPU_VCCSENSECPU_VCCSENSE

CLK_PCIEITPCPU_CLK100M CLK_PCIE_80D ITPCPU_CLK100M_N

XDP_CPUPCH_TRST_LXDP_TRST_L CPU_45S CPU_ITP

CPU_VCCIOSENSE_PCPU_VCCIOSENSE CPU_VCCSENSESENSE_1TO1_P2MM

CPU_COMPCPU_45SCPU_SVIDSCLK CPU_VIDSCLK

PCIE_CPU_SSD_R2D PCIE_CPU_TXPCIE_80D PCIE_SSD_R2D_C_N<3..0>

CPU_VDDQ_SENSE_PCPU_27P4SCPU_VALSENSE CPU_VCCSENSE

CPU_VCCIOSENSE_NCPU_VCCSENSECPU_VCCIOSENSE SENSE_1TO1_P2MM

XDP_OBSDATA_B<3..0>CPU_ITPCPU_45S

CPU_ITPXDP_BPM_L XDP_BPM_L<1..0>CPU_45S

CPU_ITPCPU_45S XDP_BPM_L<7..2>

CPU_27P4S CPU_VCCSENSECPU_VALSENSE CPU_VDDQ_SENSE_N

XDP_CPURST_LCPU_ITPCPU_45S

CPU_VALSENSE CPU_VCCSENSECPU_27P4S CPU_VCC_VALSENSE_P

CPU_27P4SCPU_VALSENSE CPU_VCCSENSE CPU_VCC_VALSENSE_N

CPU_COMPCPU_45SCPU_SVIDSOUT CPU_VIDSOUT

PCIE_CPU_SSD_R2D PCIE_80D PCIE_CPU_TX PCIE_SSD_R2D_C_P<3..0>

CPU_27P4SCPU_VALSENSE CPU_VCCSENSE CPU_AXG_VALSENSE_N

CPU_AXG_SENSE_NCPU_AXG_SENSE CPU_VCCSENSESENSE_1TO1_P2MM

CPU_AXG_SENSE_PCPU_VCCSENSECPU_AXG_SENSE SENSE_1TO1_P2MM

CPU_VCCSENSE_NSENSE_1TO1_P2MMCPU_VCCSENSE CPU_VCCSENSE

XDP_CPU_TDICPU_45S CPU_ITPXDP_TDI

XDP_CPU_CLK100M_NCLK_PCIEITPCPU_CLK100M CLK_PCIE_80D

CPU_CFG<15..12>CPU_ITPCPU_45S

CLK_PCIEITPCPU_CLK100M CLK_PCIE_80D ITPXDP_CLK100M_P

ITPCPU_CLK100M_PITPCPU_CLK100M CLK_PCIE_80D CLK_PCIE

DPLL_REF_CLKNCLK_PCIEDPLL_REF_CLK120M CLK_PCIE_80D

DMI_CLK100M_CPU_NCLK_PCIECLK_PCIE_80DDMI_CLK100M

<BRANCH>

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58 62

5 58

5 58

58 62

5 58 62

5 58 62

58 62

58 62

13 18 25

25

13 18 25

5 18 25

5 18 25

25

25

25

13 25

13 25

25

25

5 25

25

5 25

25

8 49

12 30 62

12 30 62

12 30 62

12 30 62

6 16 62

6 16 62

6 16 62

30 62

30 62

6 36

16 17

6 16 62

6 16 62

6

6

6

6 16 62

6 35

6 35 36 49

6

15 36

8 49

6 12 16 62

8 49

12 30

6 16

6 16

16

8 49

12 30

9 49

6 16 62

6 16

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USB EXTB nets (Left USB port)

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

SATA Interface Constraints

ELECTRICAL_CONSTRAINT_SET SPACING

NET_TYPE

PHYSICAL

PCH Net Properties

USB 3.0 Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 2.0 Interface Constraints

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB EXTA nets (Right USB port)

USB Hucopyb nets

UART Interface Constraints

TP SPI nets

=STANDARD* =STANDARD 8 MIL =STANDARD8 MILPCH_USB_RBIAS =STANDARD

=80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFFUSB_80D =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

UART ?* =2x_DIELECTRIC

?USB * =2x_DIELECTRIC

USB3_RX2RXUSB3_PCH_RXUSB3_PCH_RX *

=80_OHM_DIFFSATA_80D =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFF

=4x_DIELECTRICSATA_ICOMP * ?

?USB =4x_DIELECTRICTOP,BOTTOM

USB3_TX2TX ?=5x_DIELECTRICTOP,BOTTOM

=5x_DIELECTRICUSB3_RX2RX ?TOP,BOTTOM

TOP,BOTTOMUSB3_TX2OTHERTX ?=5x_DIELECTRIC

USB3_RX2OTHERRX ?=5x_DIELECTRICTOP,BOTTOM

USB3_TX2RX TOP,BOTTOM ?=7x_DIELECTRIC

=7x_DIELECTRICUSB3_RX2TX ?TOP,BOTTOM

USB3_2OTHERHS =6x_DIELECTRIC ?TOP,BOTTOM

TOP,BOTTOMUSB3_2OTHER ?=5x_DIELECTRIC

* =2.5x_DIELECTRIC ?USB3_RX2RX

* =6x_DIELECTRIC ?USB3_TX2RX

* =4x_DIELECTRIC ?USB3_TX2OTHERTX

* =4x_DIELECTRIC ?USB3_RX2OTHERRX

* =6x_DIELECTRIC ?USB3_RX2TX

* =3x_DIELECTRICUSB3_2OTHER ?

* ?USB3_2OTHERHS =4x_DIELECTRIC

USB3_TX2TXUSB3_PCH_TXUSB3_PCH_TX *

USB3_RX2TXUSB3_PCH_RX **_PCH_TX

USB3_PCH_TX USB3_TX2OTHERTX**_PCH_TX

USB3_RX2OTHERRXUSB3_PCH_RX **_PCH_RX

USB3_TX2RXUSB3_PCH_TX **_PCH_RX

USB3_PCH_RX **_TX USB3_2OTHERHS

USB3_PCH_TX **_TX USB3_2OTHERHS

USB3_PCH_TX **_RX USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_RX **

USB3_PCH_RX **_RX USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_TX *** ?USB3_TX2TX =2.5x_DIELECTRIC

SYNC_DATE=11/13/2012SYNC_MASTER=CLEAN_J41

PCH Constraints 1

=45_OHM_SE=45_OHM_SE=45_OHM_SEUART_45S * =45_OHM_SE =45_OHM_SE=45_OHM_SE

USBUSB_80D USB_BT_WAKE_P

USB_SDCARD USB_80D USB USB_SDCARD_N

TPAD_SPI_MOSISPI_45S SPI

SPISPI_45S TPAD_SPI_MISO

USB_80D USB USB_TPAD_CONN_N

UART_45S UART SMC_DEBUGPRT_RX_L

USBUSB_TPAD USB_TPAD_PUSB_80D

USB USB_BT_WAKE_NUSB_80D

USBUSB_80D USB_BT_CONN_N

USB_HUB_UP_NUSB_80D USBUSB_HUB1_UP

USB3_SD_RX NC_USB3RPCIE_SD_D2RPUSB3_PCH_RXUSB_80D

USB3_SD_TX NC_USB3RPCIE_SD_R2D_CPUSB3_PCH_TXUSB_80D

USB_80D USB3_PCH_RX USB3_SD_D2R_C_P

USB3_SD_R2D_PUSB3_PCH_TXUSB_80D

PCIE_CLK100M_PCH_PCLK_PCIECLK_PCIE_80DPCH_DIFFCLK_UNUSED_

USB3_SD_TX NC_USB3RPCIE_SD_R2D_CNUSB3_PCH_TXUSB_80D

USB3_SD_RX NC_USB3RPCIE_SD_D2RNUSB3_PCH_RXUSB_80D

USB3_EXTB_R2D_C_NUSB3_PCH_TXUSB_80D

USB3_EXTB_TX USB3_EXTB_R2D_NUSB3_PCH_TXUSB_80D

USB3_PCH_RXUSB_80DUSB3_EXTB_RX USB3_EXTB_D2R_N

USB3_EXTB_D2R_RC_PUSB3_PCH_RXUSB_80D

USB3_EXTB_R2D_C_PUSB_80D USB3_PCH_TX

USB_80D USB3_SD_D2R_C_NUSB3_PCH_RX

USB3_PCH_TX USB3_SD_R2D_NUSB_80D

PCH_CLK96M_DOT_PCLK_PCIE_80D CLK_PCIEPCH_DIFFCLK_UNUSED_

PCH_CLK96M_DOT_NPCH_DIFFCLK_UNUSED_ CLK_PCIE_80D CLK_PCIE

PCH_CLK100M_SATA_PCLK_PCIE_80DPCH_DIFFCLK_UNUSED_ CLK_PCIE

PCH_CLK100M_SATA_NPCH_DIFFCLK_UNUSED_ CLK_PCIECLK_PCIE_80D

PCH_CLK14P3M_REFCLKCPU_45S CLK_PCIE

USB_EXTB_NUSB_80DUSB_EXTB USB

USB_EXTB_PUSBUSB_80DUSB_EXTB

USB3_EXTB_D2R_PUSB_80D USB3_PCH_RXUSB3_EXTB_RX

USB3_EXTB_D2R_RC_NUSB3_PCH_RXUSB_80D

USB3_EXTA_R2D_C_NUSB_80D USB3_PCH_TX

USB3_EXTA_TX USB3_PCH_TXUSB_80D USB3_EXTA_R2D_N

USB3_EXTA_R2D_F_PUSB_80D USB3_PCH_TX

USB_80D USB3_PCH_TX USB3_EXTA_R2D_C_P

USB3_EXTB_R2D_PUSB3_EXTB_TX USB_80D USB3_PCH_TX

USB3_EXTA_R2D_F_NUSB_80D USB3_PCH_TX

USB USB_BT_PUSB_80DUSB_BT

USBUSB_TPAD USB_80D USB_TPAD_N

USBUSB_80D USB_BT_CONN_P

USB USB_HUB_UP_PUSB_80DUSB_HUB1_UP

PCIE_CLK100M_PCH_NPCH_DIFFCLK_UNUSED_ CLK_PCIECLK_PCIE_80D

USB3_EXTA_D2R_F_NUSB_80D USB3_PCH_RX

USB3_PCH_RXUSB_80D USB3_EXTA_D2R_F_P

USB3_EXTA_TX USB_80D USB3_PCH_TX USB3_EXTA_R2D_P

USB_80DUSB_BT USB USB_BT_N

SATA_ICOMPPCH_SATA_ICOMP PCH_SATAICOMP

USB2_EXTA USBUSB_80D USB2_EXTA_MUXED_P

USB_80D USB USB_TPAD_CONN_P

PCH_USB_RBIASPCH_USB_RBIAS PCH_USB_RBIAS

USBUSB_80D TPAD_SPI_MISO_USB_NUSBUSB_80D TPAD_SPI_MOSI_USB_P

USB3_EXTA_RX USB_80D USB3_EXTA_D2R_NUSB3_PCH_RX

USB3_EXTA_RX USB_80D USB3_PCH_RX USB3_EXTA_D2R_PUSB2_EXTA USBUSB_80D USB2_EXTA_MUXED_F_NUSB2_EXTA USB_80D USB USB2_EXTA_MUXED_F_PUSB2_EXTA USBUSB_80D USB2_EXTA_MUXED_N

UART_45S SMC_DEBUGPRT_TX_LUART

USB_EXTA USB_80D USB USB_EXTA_NUSBUSB_EXTA USB_80D USB_EXTA_P

SPISPI_45S TPAD_SPI_CLK

USB_80D USB USB_SDCARD_PUSB_SDCARD

USB USB_TPAD_M_NUSB_80DUSB_TPAD_M

USB USB_TPAD_M_PUSB_80DUSB_TPAD_M

<BRANCH>

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<E4LABEL>

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15 34

15 34

33 35 36

14 34 62

29 62

14 63

14 63

14 63

14 63

14 59 63

59 63

14 59 63

59 63

14 59 63

14 59 63

14 59 63

14 59 63

59 63

14 33

33

14 33

59 63

14 29

14 34 62

29 62

33

14 29

33

14

14 33

14 33

33

33

33

33 35 36

14 33

14 33

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ON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SETTABLE_PHYSICAL_RULE_HEAD




Apple Inc.


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ELECTRICAL_CONSTRAINT_SET

SIO Signal Constraints



SMBus Interface Constraints

SPI Interface Constraints

XDP Constraints

LPC Bus Constraints

NOTE: 25MHz system clocks very sensitive to noise.

HD Audio Interface Constraints

PHYSICAL

NET_TYPE

System Clock Signal Constraints

DisplayPort

NET_TYPE

PCH Net Properties

SPACING

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET

Clock Net Properties

=4x_DIELECTRICDP_2OTHER TOP,BOTTOM ?

DP_2DP =3x_DIELECTRIC* ?

=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARDCLK_SLOW_45S =45_OHM_SE

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARDCLK_25M_45S

DP_2OTHERHS*_TXDP_TX *

DP_2OTHER ?* =3x_DIELECTRIC

=3x_DIELECTRIC ?*DP_AUX

=4x_DIELECTRICDP_2OTHERHS ?*

=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD=45_OHM_SE =STANDARDCLK_SLOW_45S

=45_OHM_SE =45_OHM_SE* =STANDARD =STANDARD=45_OHM_SE=45_OHM_SECLK_LPC_45S

* ?=3x_DIELECTRICLPC

?CLK_LPC * =4x_DIELECTRIC

* =5x_DIELECTRIC ?CLK_25M

LPC_45S =45_OHM_SE=45_OHM_SE =45_OHM_SE =45_OHM_SE* =STANDARD =STANDARD

SMB_45S_R_50S TOP,BOTTOM =50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

SMB * =2x_DIELECTRIC ?

* =2x_DIELECTRIC ?HDA

* ?CLK_SLOW =2x_DIELECTRIC

* ?=4x_DIELECTRICCLK_SLOW

*PCH_ITP ?=2:1_SPACING

*SPI ?=4x_DIELECTRIC

=45_OHM_SE =45_OHM_SE =STANDARD* =45_OHM_SEPCH_45S =45_OHM_SE =STANDARD

SMB_45S_R_50S =45_OHM_SE =45_OHM_SE =45_OHM_SE* =STANDARD=STANDARD=45_OHM_SE

=45_OHM_SESPI_45S * =STANDARD=STANDARD=45_OHM_SE =45_OHM_SE=45_OHM_SE

=80_OHM_DIFF=80_OHM_DIFFDP_80D =80_OHM_DIFF=80_OHM_DIFF* =80_OHM_DIFF=80_OHM_DIFF

*DP_TX DP_TX DP_2DP

DP_2OTHERHSDP_TX **_RX

DP_2OTHER*DP_TX *

=4x_DIELECTRICDP_AUX TOP,BOTTOM ?

=4x_DIELECTRICTOP,BOTTOM ?DP_2DP

=6x_DIELECTRICDP_2OTHERHS TOP,BOTTOM ?


PCH Constraints 2

SYNC_MASTER=J43_MLB

=STANDARD=45_OHM_SE=45_OHM_SE=45_OHM_SEHDA_45S * =45_OHM_SE =STANDARD

CLK25M_CAM_CLKPCLK_25MCLK_25M_45S

CLK_25MCLK_25M_45S CLK25M_CAM_CLKN

CLK_25M_45S CLK_25M SDCLK_CLK25M_X2_R

CLK_25M_45S CLK_25M SDSCLK_CLK25M_X1

SYSCLK_CLK32K_RTCX1CLK_SLOWCLK_SLOW_45SSYSCLK_CLK32K_RTC

CLK_25M SYSCLK_CLK25M_CAMERACLK_25M_45SSYSCLK_CLK25M_SB

CLK_25M_45S CLK_25M SDCLK_CLK25M_X2

SYSCLK_CLK25M_X2_RCLK_25M_45S CLK_25M

CLK25M_CAM_XTALP_RCLK_25MCLK_25M_45S

CLK_25M_45S CLK25M_CAM_XTALPCLK_25M

CLK25M_CAM_XTALNCLK_25MCLK_25M_45S

SYSCLK_CLK25M_TBTCLK_25M_45S CLK_25MSYSCLK_CLK25M_TBT

CLK_25M SYSCLK_CLK25M_TBT_RCLK_25M_45S

CLK_25M_45S CLK_25MSYSCLK_CLK25M_XTAL SYSCLK_CLK25M_X1

CLK_25M_45S SYSCLK_CLK25M_X2CLK_25M

PM_CLK32K_SUSCLK_RPM_SUS_CLK CLK_SLOW_45S CLK_SLOW

SMC_CLK32KCLK_SLOWCLK_SLOW_45S

SPI_CLK_RSPI_45S SPISPI_CLK

SPISPI_45S SPI_CLK

SPISPI_45SSPI_MOSI SPI_MOSI_R

SPISPI_45S SPI_MOSI

SMB_45S_R_50S SMB SML_PCH_0_DATASMBUS_PCH_0_DATA

SMB_45S_R_50S SMB SMBUS_PCH_DATASMBUS_PCH_DATA

SMBSMB_45S_R_50S SMBUS_SMC_1_S0_SCLSMBUS_SMC_1_S0_SCL

LPC_CLK24M_SMCLPC_CLK33M CLK_LPCCLK_LPC_45S

HDA_45S HDA HDA_SDIN0HDA_SDIN0

HDA_SYNC HDAHDA_45S HDA_SYNC

HDA_RST_LHDAHDA_45S

HDA_45S HDA_RST_R_LHDA_RST_L HDA

HDA_45S HDA_SDOUT_RHDA

HDAHDA_45S HDA_SDOUTHDA_SDOUT

HDAHDA_45S HDA_SYNC_R

SMBUS_SMC_1_S0_SDA SMBSMB_45S_R_50S SMBUS_SMC_1_S0_SDA

SMB SML_PCH_0_CLKSMB_45S_R_50SSMBUS_PCH_0_CLK

HDAHDA_45S HDA_BIT_CLK_R

SMB_45S_R_50S SMBSMBUS_PCH_CLK SMBUS_PCH_CLK

CLK_LPC_45S CLK_LPC LPC_CLK24M_SMC_R

LPCPLUS_RESET_LLPC_45S LPC

LPC_FRAME_L LPC_45S LPC_FRAME_LLPC

LPC_AD LPC_45S LPC LPC_AD<3..0>

CLK_LPCCLK_LPC_45S LPC_CLK24M_LPCPLUS_RCLK_LPCLPC_CLK33M CLK_LPC_45S LPC_CLK24M_LPCPLUS

HDA_45SHDA_BIT_CLK HDA HDA_BIT_CLK

SPI_45S SPI SPI_SMC_CS_L

SPI_SMC_MISOSPI_45S SPI

SPI_45S SPI SPI_SMC_MOSI

SPI_SMC_CLKSPI_45S SPI

SPI_CS0 SPI SPI_CS0_R_LSPI_45S

SPI_45S SPI_CS0_LSPI

SPI_MISOSPISPI_45SSPI_MISO

SPI_45S SPI SPI_MISO_R

CLK_PCIE_80D PCIE_CLK100M_CAMERA_C_NCLK_PCIE

CLK_PCIE_80D PCIE_CLK100M_CAMERA_C_PCLK_PCIE

PCIE_CLK100M_CAM CLK_PCIE_80D PCIE_CLK100M_CAMERA_NCLK_PCIE

PCIE_CLK100M_CAM PCIE_CLK100M_CAMERA_PCLK_PCIE_80D CLK_PCIE

PCIE_80D PCIE_PCH_RX PCIE_CAMERA_D2R_C_N

PCIE_CAMERA_D2R_C_PPCIE_80D PCIE_PCH_RX

PCIE_CAM PCIE_CAMERA_D2R_NPCIE_80D PCIE_PCH_RX

PCIE_CAM PCIE_80D PCIE_PCH_RX PCIE_CAMERA_D2R_P

PCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_C_P

PCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_C_N

PCIE_CAM PCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_P

PCIE_CAM PCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_N

XDP_PCH_TCKPCH_45S PCH_ITPXDP_TCK

PCH_45S PCH_ITPXDP_TMS XDP_PCH_TMSXDP_TDO PCH_ITPPCH_45S XDP_PCH_TDOXDP_TDI PCH_45S PCH_ITP XDP_PCH_TDI

CLK_PCIE_80D CLK_PCIE PEG_CLK100M_NCLK_PCIE_80D PEG_CLK100M_PCLK_PCIE

PCIE_CLK100M_TBT CLK_PCIECLK_PCIE_80D PCIE_CLK100M_TBT_N

PCIE_80D PCIE_PCH_RX PCIE_TBT_D2R_C_N<3..0>

PCIE_CLK100M_TBT CLK_PCIE_80D CLK_PCIE PCIE_CLK100M_TBT_P

PCIE_PCH_RXPCIE_80D PCIE_TBT_D2R_C_P<3..0>PCIE_80DPCIE_TBT_D2R PCIE_PCH_RX PCIE_TBT_D2R_N<3..0>

PCIE_PCH_RXPCIE_80D PCIE_TBT_D2R_P<3..0>PCIE_TBT_D2R

PCIE_80D PCIE_PCH_TX PCIE_TBT_R2D_C_N<3..0>PCIE_PCH_TX PCIE_TBT_R2D_C_P<3..0>PCIE_80D

PCIE_80D PCIE_PCH_TX PCIE_TBT_R2D_N<3..0>PCIE_TBT_R2D

PCIE_PCH_TXPCIE_80DPCIE_TBT_R2D PCIE_TBT_R2D_P<3..0>

CLK_PCIE_80D PCIE_CLK100M_AP_NPCIE_CLK100M_AP CLK_PCIE

CLK_PCIE_80D PCIE_CLK100M_AP_PCLK_PCIEPCIE_CLK100M_AP

PCIE_AP_D2R_NPCIE_80DPCIE_AP_D2R PCIE_PCH_RX

PCIE_80DPCIE_AP_D2R PCIE_PCH_RX PCIE_AP_D2R_PPCIE_80D PCIE_PCH_TX PCIE_AP_R2D_C_NPCIE_80D PCIE_AP_R2D_C_PPCIE_PCH_TX

PCIE_AP_R2D_NPCIE_PCH_TXPCIE_80DPCIE_AP_R2D

PCIE_PCH_TXPCIE_80DPCIE_AP_R2D PCIE_AP_R2D_P

SPI_MLB_IO2_WP_LSPI_45S SPI

SPI_MLB_IO3_HOLD_LSPI_45S SPI

SPI_MLB_CLKSPISPI_45S

SPI_MLB_CS_LSPI_45S SPI

SPI_IO<2>SPI_45S SPI

SPI_IO2_RSPI_45S SPI

SPI_IO<3>SPI_45S SPI

SPI_IO3_RSPI_45S SPI

<BRANCH>

<SCH_NUM>

<E4LABEL>

113 OF 120

67 OF 73

31 32

31 32

17 32

17

32

32

32

17 25

25

17

17

13 36

35 36

14 44

44

14 44

44

14 38

14 16 19 38 54

14 32 35 38 41 42 62 71

17 35

12 59 63

12 59 63

12 59 63

12

12 17

12 59 63

12

14 32 35 38 41 42 62 71

14 38

12

14 16 19 38 54

12 17

62

14 35 62

14 35 62

12 59 63

35 44

35 44

35 44

35 44

14 44

44

14 44

44

31 32

31 32

12 32

12 32

31 32

31 32

14 32

14 32

14 32

14 32

31 32

31 32

12 16 62

12 16 62

12 16 62

12 16 62

12 25

25

12 25

25

14 25

14 25

14 25

14 25

25

25

12 29 62

12 29 62

14 29 62

14 29 62

14 29

14 29

29 62

29 62

44

44

44

44

14 44

44

14 44

44

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TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM

















































PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD




















Spacing Rule Sets

Memory Bus Constraints

Memory to GND Spacing

Memory to Power Spacing

Memory Bus Spacing Group Assignments

SPACING

Memory Net Properties

PHYSICAL

NET_TYPE


** MEM_2OTHERMEM_A_DATA_1


**MEM_A_DATA_3 MEM_2OTHER



**MEM_A_DATA_6 MEM_2OTHER

MEM_A_DATA_7 * * MEM_2OTHER

** MEM_2OTHERMEM_B_DATA_0



**MEM_B_DATA_3 MEM_2OTHER



* MEM_2OTHER*MEM_B_DATA_7

*MEM_B_DATA_6 * MEM_2OTHER

*MEM_B_DQS_4 MEM_2OTHER*

MEM_A_DQS_4 * * MEM_2OTHER

MEM_A_DQS_3 MEM_2OTHER* *

MEM_CLK MEM_CLK2CLK*MEM_CLK

MEM_B_DATA_7 MEM_DQS2OWNDATAMEM_B_DQS_7 *

MEM_B_DATA_6 MEM_DQS2OWNDATA*MEM_B_DQS_6

MEM_DATA2OTHERMEMMEM_* *MEM_*_DATA_*

MEM_CTRL *MEM_CTRL MEM_CTRL2CTRL

MEM_B_DQS_6 MEM_2OTHER* *

MEM_40S MEM_TERM MEM_50S

MEM_70D MEM_TERM MEM_73D

* MEM_2OTHERMEM_B_DQS_7 *

MEM_DQS2OWNDATAMEM_A_DATA_7 *MEM_A_DQS_7

MEM_DQS2OWNDATAMEM_A_DATA_6 *MEM_A_DQS_6

MEM_DQS2OWNDATA*MEM_A_DQS_5 MEM_A_DATA_5

MEM_DQS2OWNDATA*MEM_A_DQS_4 MEM_A_DATA_4

=6x_DIELECTRICMEM_2OTHER ?*

*MEM_PWR DEFAULT*

MEM_2PWRMEM_PWR MEM_* *

MEM_2GNDMEM_*GND *

MEM_A_DATA_2MEM_A_DQS_2 MEM_DQS2OWNDATA*

MEM_CTRL *MEM_CMD MEM_CMD2CTRL

MEM_2OTHER*MEM_CTRL *

*MEM_CMD * MEM_2OTHER

=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFFMEM_70D * =70_OHM_DIFF =70_OHM_DIFF

=73_OHM_DIFF*MEM_73D =73_OHM_DIFF =73_OHM_DIFF =73_OHM_DIFF =73_OHM_DIFF =73_OHM_DIFF

*MEM_50S =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

* =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SEMEM_40S =40_OHM_SE

MEM_2GND 10000=2x_DIELECTRIC*

=2x_DIELECTRICMEM_DATA2SELF ?*

MEM_CLK ** MEM_2OTHER

MEM_DATA2OTHERMEM * ?=8x_DIELECTRIC

MEM_DQS2OWNDATA ?* =3x_DIELECTRIC

MEM_CMD2CMD * =3x_DIELECTRIC ?

MEM_CMD2CTRL =3x_DIELECTRIC ?*

MEM_CTRL2CTRL ?* =3x_DIELECTRIC

MEM_CLK2CLK =6x_DIELECTRIC* ?

MEM_2OTHERMEM ?* =4x_DIELECTRIC

=2x_DIELECTRICMEM_2PWR 10000*

MEM_A_DATA_3 MEM_DQS2OWNDATAMEM_A_DQS_3 *

MEM_A_DATA_1 MEM_DQS2OWNDATA*MEM_A_DQS_1

MEM_DQS2OWNDATAMEM_A_DATA_0 *MEM_A_DQS_0 MEM_A_DQS_0 MEM_2OTHER* *


=SAME MEM_DATA2SELFMEM_*_DATA_* *

MEM_A_DATA_0 ** MEM_2OTHER



* MEM_2OTHER*MEM_B_DQS_3

MEM_B_DQS_2 MEM_2OTHER**






MEM_DQS2OWNDATAMEM_B_DATA_2 *MEM_B_DQS_2


MEM_DQS2OWNDATAMEM_B_DATA_0MEM_B_DQS_0 *

MEM_DQS2OWNDATAMEM_B_DATA_1 *MEM_B_DQS_1


MEM_DQS2OWNDATA*MEM_B_DATA_5MEM_B_DQS_5

*MEM_CMDMEM_CMD MEM_CMD2CMD

MEM_2OTHERMEMMEM_* MEM_* *


Memory Constraints

SYNC_MASTER=CHINMAY_J41

*MEM_A_DATA_1 MEM_*_DATA_* MEM_2OTHERMEM






MEM_A_DATA_7 *MEM_*_DATA_* MEM_2OTHERMEM


*MEM_B_DATA_0 MEM_*_DATA_* MEM_2OTHERMEM








MEM_PWR PP0V6_S3_MEM_VREFDQ_BMEM_PWR PP0V6_S3_MEM_VREFCA_B

PP0V6_S3_MEM_VREFDQ_AMEM_PWR

PP0V6_S3_MEM_VREFCA_AMEM_PWR

MEM_PWR PP1V2_S3

MEM_70D MEM_B_DQS_N<7>MEM_B_DQS7 MEM_B_DQS_7

MEM_70D MEM_B_DQS_7 MEM_B_DQS_P<7>MEM_B_DQS7

MEM_70DMEM_B_DQS6 MEM_B_DQS_6 MEM_B_DQS_N<6>


MEM_70DMEM_B_DQS6 MEM_B_DQS_P<6>MEM_B_DQS_6

MEM_B_DQS5 MEM_B_DQS_5 MEM_B_DQS_P<5>MEM_70D


MEM_70D MEM_B_DQS_P<4>MEM_B_DQS_4MEM_B_DQS4


MEM_70D MEM_B_DQS_P<3>MEM_B_DQS3 MEM_B_DQS_3






MEM_B_DQS0 MEM_70D MEM_B_DQS_P<0>MEM_B_DQS_0

MEM_B_DQ_BYTE7 MEM_40S MEM_B_DQ<63..56>MEM_B_DATA_7

MEM_B_DQ_BYTE6 MEM_40S MEM_B_DATA_6 MEM_B_DQ<55..48>MEM_B_DQ_BYTE5 MEM_40S MEM_B_DQ<47..40>MEM_B_DATA_5

MEM_B_DQ<39..32>MEM_B_DATA_4MEM_40SMEM_B_DQ_BYTE4

MEM_40S MEM_B_DQ<31..24>MEM_B_DQ_BYTE3 MEM_B_DATA_3


MEM_40S MEM_B_DQ<23..16>MEM_B_DATA_2MEM_B_DQ_BYTE2


MEM_40S MEM_CMD MEM_B_CAB<9..0>MEM_B_CMD1

MEM_40S MEM_CMD MEM_B_CAA<9..0>MEM_B_CMD0

MEM_40S MEM_CMD MEM_B_CKE<3..2>MEM_B_CKE1

MEM_40S MEM_CMDMEM_B_CKE0 MEM_B_CKE<1..0>MEM_40S MEM_CTRL MEM_B_ODT<0>MEM_B_CTRL

MEM_40S MEM_CTRL MEM_B_CS_L<1..0>MEM_B_CTRL

MEM_70D MEM_CLK MEM_B_CLK_N<1>MEM_B_CLK1

MEM_B_CLK1 MEM_70D MEM_CLK MEM_B_CLK_P<1>MEM_B_CLK0 MEM_70D MEM_CLK MEM_B_CLK_N<0>MEM_B_CLK0 MEM_70D MEM_CLK MEM_B_CLK_P<0>

MEM_A_DQS7 MEM_A_DQS_N<7>MEM_70D MEM_A_DQS_7

MEM_A_DQS7 MEM_A_DQS_P<7>MEM_70D MEM_A_DQS_7

MEM_A_DQS_N<6>MEM_70D MEM_A_DQS_6MEM_A_DQS6

MEM_A_DQS_N<5>MEM_70D MEM_A_DQS_5MEM_A_DQS5MEM_A_DQS_P<6>MEM_70DMEM_A_DQS6 MEM_A_DQS_6

MEM_A_DQS_P<5>MEM_A_DQS5 MEM_70D MEM_A_DQS_5

MEM_A_DQS_P<4>MEM_A_DQS4 MEM_70D MEM_A_DQS_4MEM_A_DQS_N<4>MEM_A_DQS4 MEM_70D MEM_A_DQS_4

MEM_A_DQS_N<3>MEM_A_DQS_3MEM_A_DQS3 MEM_70D

MEM_A_DQS_2MEM_A_DQS2 MEM_70D MEM_A_DQS_N<2>MEM_A_DQS_P<3>MEM_A_DQS_3MEM_A_DQS3 MEM_70D

MEM_A_DQS_1MEM_A_DQS1 MEM_70D MEM_A_DQS_N<1>MEM_A_DQS_2MEM_A_DQS2 MEM_70D MEM_A_DQS_P<2>

MEM_A_DQS_1MEM_A_DQS1 MEM_70D MEM_A_DQS_P<1>MEM_A_DQS_0MEM_A_DQS0 MEM_70D MEM_A_DQS_N<0>MEM_A_DQS_0MEM_A_DQS0 MEM_70D MEM_A_DQS_P<0>

MEM_A_DATA_6MEM_A_DQ_BYTE6 MEM_40S MEM_A_DQ<55..48>MEM_A_DATA_7MEM_A_DQ_BYTE7 MEM_40S MEM_A_DQ<63..56>

MEM_A_DQ<47..40>MEM_A_DATA_5MEM_A_DQ_BYTE5 MEM_40S

MEM_A_DQ<31..24>MEM_A_DATA_3MEM_A_DQ_BYTE3 MEM_40SMEM_A_DQ<39..32>MEM_A_DATA_4MEM_A_DQ_BYTE4 MEM_40S

MEM_A_DQ<15..8>MEM_A_DATA_1MEM_A_DQ_BYTE1 MEM_40SMEM_A_DQ<23..16>MEM_A_DATA_2MEM_A_DQ_BYTE2 MEM_40S

MEM_A_DQ<7..0>MEM_A_DATA_0MEM_A_DQ_BYTE0 MEM_40S

MEM_A_CMD0 MEM_CMD MEM_A_CAA<9..0>MEM_40S

MEM_A_CMD1 MEM_CMD MEM_A_CAB<9..0>MEM_40S

MEM_A_CKE1 MEM_A_CKE<3..2>MEM_40S MEM_CMD

MEM_CMDMEM_40S MEM_A_CKE<1..0>MEM_A_CKE0

MEM_A_CTRL MEM_CTRLMEM_40S MEM_A_ODT<0>MEM_40S MEM_CTRLMEM_A_CTRL MEM_A_CS_L<1..0>

MEM_A_CLK1 MEM_CLKMEM_70D MEM_A_CLK_N<1>MEM_70D MEM_CLKMEM_A_CLK1 MEM_A_CLK_P<1>

MEM_CLKMEM_70D MEM_A_CLK_P<0>MEM_A_CLK0

MEM_70D MEM_CLK MEM_A_CLK_N<0>MEM_A_CLK0

<BRANCH>

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<E4LABEL>

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18 19 22 23

18 19 22 23

18 19 20 21

18 19 20 21

17 19 20 21 22 23 40 51 60

7 61

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Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

Thunderbolt IC Net Properties

SPACING

Only used on hosts supporting Thunderbolt video-in

Thunderbolt/DP Net PropertiesDisplayPort Signal Constraints

Thunderbolt SPI Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.


NET_TYPE

PHYSICAL SPACING

Thunderbolt/DP Connector Signal Constraints

TBTDP_TX2TXTBTDP_TX TBTDP_TX *

Thunderbolt Constraints

SYNC_DATE=09/07/2012SYNC_MASTER=CHINMAY_J41

=10x_DIELECTRICTBTDP_TX2RX ?TOP,BOTTOM

TBTDP_2OTHERHS =10x_DIELECTRICTOP,BOTTOM ?

=6x_DIELECTRICTBTDP_RX2RX ?TOP,BOTTOM

TBTDP_TX *_TX TBTDP_2OTHERHS*

TBTDP_2OTHERTBTDP_RX **

TBTDP_2OTHER*TBTDP_TX *

*_RX TBTDP_2OTHERHS*TBTDP_RX

TBTDP_2OTHER =6x_DIELECTRIC ?TOP,BOTTOM

TBTDP_TX2RXTBTDP_TX TBTDP_RX *

?TBTDP_TX2TX * =4x_DIELECTRIC

TBTDP_TX2RX ?* =6x_DIELECTRIC

TBTDP_RX2RX ?* =4x_DIELECTRIC

=4x_DIELECTRICTBTDP_2OTHER ?*

=6x_DIELECTRICTBTDP_2OTHERHS * ?

*_TX TBTDP_2OTHERHS*TBTDP_RX

TBTDP_2OTHERHS*_RX *TBTDP_TX

TBT_SPI * =2x_DIELECTRIC ?

=80_OHM_DIFFTBTDP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

TBTDP_RX TBTDP_RX * TBTDP_RX2RX

TBTDP_TX TBTDP_TX2RXTBTDP_RX *

=6x_DIELECTRICTBTDP_TX2TX ?TOP,BOTTOM

TBT_SPI_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD

TBTDP_RXTBTDP_80D TBT_A_D2R_C_P<1..0>

TBTDP_RXTBTDP_80DTBT_A_D2R1 TBT_A_D2R_P<1>

TBTDP_RXTBT_A_D2R1 TBT_A_D2R_N<1>TBTDP_80D

TBTDP_RXTBT_A_D2R0 TBT_A_D2R_P<0>TBTDP_80D

TBTDP_RXTBT_A_D2R0 TBT_A_D2R_N<0>TBTDP_80D

DP_AUXTBT_A_AUXCH DP_80D DP_TBTPA_AUXCH_C_P

DP_AUXDP_80DTBT_A_AUXCH DP_TBTPA_AUXCH_C_N

DP_AUX DP_TBTPA_AUXCH_PDP_80D

DP_AUX DP_TBTPA_AUXCH_NDP_80D

DP_AUXDP_80D DP_A_AUXCH_DDC_P

TBTDP_RXTBTDP_80D TBT_A_D2R_C_N<1..0>

TBTDP_RXTBTDP_80D TBT_A_D2R1_AUXDDC_P

TBTDP_RXTBTDP_80D TBT_A_D2R1_AUXDDC_N

TBTDP_TX TBT_B_R2D_C_N<1..0>TBT_B_R2D TBTDP_80D

TBTDP_TX TBT_B_R2D_N<1..0>TBTDP_80D

TBTDP_TX TBT_A_R2D_C_P<1..0>TBT_A_R2D TBTDP_80D

TBTDP_TX TBT_A_R2D_C_N<1..0>TBT_A_R2D TBTDP_80D

TBTDP_TX TBT_A_R2D_N<1..0>TBTDP_80D

TBTDP_TX TBT_A_R2D_P<1..0>TBTDP_80D

DP_TBTSRC_ML_C_P<3..0>DP_80D DP_TX

DP_TBTSRC_ML_C_N<3..0>DP_80D DP_TX

DP_TBTSRC_AUXCH_C_PDP_80D DP_AUX

DP_TBTSRC_AUXCH_C_NDP_80D DP_AUX

TBT_SPI_CLKTBT_SPI_CLK TBT_SPI_45S TBT_SPI

TBT_SPI_MOSITBT_SPI_MOSI TBT_SPI_45S TBT_SPI

TBT_SPI_MISOTBT_SPI_MISO TBT_SPI_45S TBT_SPI

TBT_SPI_CS_LTBT_SPI_45S TBT_SPITBT_SPI_CS_L

TBTDP_TXTBT_B_R2D TBT_B_R2D_C_P<1..0>TBTDP_80D

TBTDP_TX TBT_B_R2D_P<1..0>TBTDP_80D

DP_TBTPB_ML NC_DP_TBTPB_ML_CP<3..1:2>DP_80D DP_TX

DP_TBTPB_ML_P<3..1:2>DP_80D DP_TX

NC_DP_TBTPB_ML_CN<3..1:2>DP_TBTPB_ML DP_80D DP_TX

DP_TBTPB_ML_N<3..1:2>DP_80D DP_TX

DP_80D DP_TX DP_B_LSX_ML_N<1>DP_80D DP_TX DP_B_LSX_ML_P<1>

TBTDP_RXTBTDP_80D TBT_B_D2R_C_P<1..0>

TBTDP_RX TBT_B_D2R_C_N<1..0>TBTDP_80D

TBTDP_RX TBT_B_D2R_P<1..0>TBTDP_80DTBT_B_D2R

TBTDP_RX TBT_B_D2R_N<1..0>TBT_B_D2R TBTDP_80D

DP_AUX NC_DP_TBTPB_AUXCH_CPTBT_B_AUXCH DP_80D

DP_AUX NC_DP_TBTPB_AUXCH_CNTBT_B_AUXCH DP_80D

DP_AUX DP_B_AUXCH_DDC_PDP_80D

DP_AUX DP_TBTPB_AUXCH_PDP_80D

DP_AUX DP_TBTPB_AUXCH_NDP_80D

DP_AUX DP_B_AUXCH_DDC_NDP_80D

TBTDP_RX TBT_B_D2R1_AUXDDC_PTBTDP_80D

TBTDP_RX TBT_B_D2R1_AUXDDC_NTBTDP_80D

DP_AUXDP_80D DP_A_AUXCH_DDC_N

DP_TXDP_80D DP_A_LSX_ML_P<1>

DP_TXDP_80DDP_TBTPA_ML1 DP_TBTPA_ML_C_N<1>DP_TXDP_80DDP_TBTPA_ML1 DP_TBTPA_ML_C_P<1>

DP_80D DP_TXDP_TBTPA_ML3 DP_TBTPA_ML_C_P<3>

DP_80D DP_A_LSX_ML_N<1>DP_TX

DP_TXDP_TBTPA_ML3 DP_TBTPA_ML_C_N<3>DP_80D

DP_TX DP_TBTPA_ML_N<3..1:2>DP_80D

DP_TX DP_TBTPA_ML_P<3..1:2>DP_80D

<BRANCH>

<SCH_NUM>

<E4LABEL>

115 OF 120

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28

28

28

62

25 28

25 28

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25

25

25

25

62

62

62

62

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25 28

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28

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Memory Bus Constraints

NET_TYPE

PHYSICAL SPACING

Memory to GND Spacing

Memory to Power Spacing

Spacing Rule Sets

MIPI Interface Constraints

Memory Bus Spacing Group Assignments

Camera Net Properties


I101

I102

I103

I104

I106

I107

I108

I109

I110

I127

I128

I129

I130

I131

I132

I133

I134

I145

I146

I147

I148

I149

* ?S2_CMD2CTRL =2x_DIELECTRIC

=2x_DIELECTRIC ?*S2_CMD2CMD

Camera Constraints

SYNC_MASTER=CHINMAY_J41 SYNC_DATE=09/07/2012

S2_MEM_DQS1 S2_DQS2OWNDATAS2_MEM_DATA1 *

=6x_DIELECTRICS2MEM_2OTHER * ?

?*S2MEM_2GND =2x_DIELECTRIC

MIPI_2OTHER ?* =4X_DIELECTRIC

MIPI_2CLK * =6X_DIELECTRIC ?

MIPICLK_2OTHER * =7X_DIELECTRIC ?

* * MIPI_2OTHERMIPI_DATA

* MIPI_2CLKCLK_MIPIMIPI_DATA

*CLK_MIPI * MIPICLK_2OTHER

=45_OHM_SE =STANDARD=45_OHM_SE =STANDARD=45_OHM_SE*S2_MEM_45S =45_OHM_SE

* =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFFS2_MEM_85D

*MIPI_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

GND S2MEM_2GNDS2_MEM_* *

S2_2OTHERMEM*S2_MEM_*S2_MEM_*

S2_MEM_CTRL S2_MEM_CTRL S2_CTRL2CTRL*

S2_MEM_CMD S2_CMD2CMDS2_MEM_CMD *

S2_MEM_CLK * S2MEM_2OTHER*

S2MEM_2OTHERS2_MEM_CTRL * *

S2MEM_2OTHER**S2_MEM_CMD

S2_MEM_DQS0 S2_DQS2OWNDATAS2_MEM_DATA0 *

S2_MEM_PWR ** DEFAULT

S2MEM_2PWRS2_MEM_*S2_MEM_PWR *

=SAME * S2_DATA2SELFS2_MEM_DATA*

S2MEM_2OTHERS2_MEM_DATA* * *

S2_MEM_DQS* ** S2MEM_2OTHER

S2_MEM_CMD S2_MEM_CTRL S2_CMD2CTRL*

=2x_DIELECTRICS2_DATA2SELF ?*

?* =2x_DIELECTRICS2MEM_2PWR

=2x_DIELECTRIC ?*S2_DQS2OWNDATA

S2_2OTHERMEM =4x_DIELECTRIC* ?

?*S2_CTRL2CTRL =2x_DIELECTRIC =4x_DIELECTRICTOP,BOTTOM ?S2_CTRL2CTRL

S2MEM_2GND TOP,BOTTOM =4x_DIELECTRIC ?

S2_2OTHERMEM ?=6x_DIELECTRICTOP,BOTTOM

=4x_DIELECTRICTOP,BOTTOM ?S2_CMD2CMD

TOP,BOTTOM ?S2_DQS2OWNDATA =4x_DIELECTRIC

TOP,BOTTOM =4x_DIELECTRIC ?S2_DATA2SELF

MIPI_2OTHER TOP,BOTTOM ?=6X_DIELECTRIC

TOP,BOTTOM ?=8X_DIELECTRICMIPI_2CLK

?TOP,BOTTOM =10X_DIELECTRICMIPICLK_2OTHER

TOP,BOTTOM ?S2_CMD2CTRL =4x_DIELECTRIC

=4x_DIELECTRICS2MEM_2PWR ?TOP,BOTTOM

S2MEM_2OTHER ?=10x_DIELECTRICTOP,BOTTOM

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D MEM_CAM_CLK_P

MIPI_DATA_S2 MIPI_DATA MIPI_DATA_PMIPI_85D

MIPI_DATA_NMIPI_DATAMIPI_DATA_S2 MIPI_85D

MIPI_DATA_CONN_PMIPI_DATAMIPI_85D

MIPI_DATA_CONN_NMIPI_DATAMIPI_85D

S2_MEM_DQS1 S2_MEM_85D S2_MEM_DQS1 MEM_CAM_DQS_P<1>

S2_MEM_PWR PP1V35_CAM

S2_MEM_DATA1 MEM_CAM_DQ<15..8>S2_MEM_45SS2_MEM_DATA_1

S2_MEM_85D S2_MEM_DQS1 MEM_CAM_DQS_N<1>S2_MEM_DQS1

PP0V675_MEM_CAM_VREFCAS2_MEM_PWR

CLK_MIPI MIPI_CLK_NMIPI_CLK_S2 MIPI_85D

MEM_CAM_BA<2>S2_MEM_CMDS2_MEM_45SS2_MEM_CMD

S2_MEM_CMDS2_MEM_CMD S2_MEM_45S MEM_CAM_BA<0>

S2_MEM_45S S2_MEM_CTRLS2_MEM_CNTL MEM_CAM_CS_L

S2_MEM_CLK S2_MEM_85D S2_MEM_CLK MEM_CAM_CLK_N

S2_MEM_DATA0S2_MEM_45S MEM_CAM_DQ<7..0>S2_MEM_DATA_0

MIPI_CLK_PCLK_MIPIMIPI_CLK_S2 MIPI_85D

S2_MEM_CMDS2_MEM_45SS2_MEM_CMD MEM_CAM_WE_LS2_MEM_CTRLS2_MEM_45SS2_MEM_CMD MEM_CAM_RAS_L

S2_MEM_CNTL S2_MEM_CTRL MEM_CAM_CKES2_MEM_45S

S2_MEM_CMD S2_MEM_45S S2_MEM_CTRL MEM_CAM_CAS_LS2_MEM_CTRLS2_MEM_45S MEM_CAM_ODT

CLK_MIPI MIPI_CLK_CONN_NMIPI_85D

S2_MEM_CMD MEM_CAM_BA<1>S2_MEM_CMD S2_MEM_45S

PP0V675_CAM_VREFS2_MEM_PWR

S2_MEM_45SS2_MEM_DATA_1 MEM_CAM_DM<1>S2_MEM_DATA1

MEM_CAM_A<14..0>S2_MEM_CMDS2_MEM_A S2_MEM_45S

S2_MEM_DATA0 MEM_CAM_DM<0>S2_MEM_DATA_0 S2_MEM_45S

S2_MEM_DQS0 MEM_CAM_DQS_P<0>S2_MEM_DQS0 S2_MEM_85D

S2_MEM_DQS0S2_MEM_85D MEM_CAM_DQS_N<0>S2_MEM_DQS0

PP0V675_MEM_CAM_VREFDQS2_MEM_PWR

CLK_MIPI MIPI_CLK_CONN_PMIPI_85D

<BRANCH>

<SCH_NUM>

<E4LABEL>

116 OF 120

70 OF 73

31 32

31 32

31 32

32 62

32 62

31 32

31 32

31 32

31 32

32

31 32

31 32

31 32

31 32

31 32

31 32

31 32

31 32

31 32

31 32

31 32

32

32 62

31 32

31 32

31 32

31 32

31 32

31 32

31 32

32

32 62

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NET_TYPE

SPACING

NET_TYPE

PHYSICAL SPACING


SMBus Charger Net Properties

PHYSICAL

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET0.1 MM* =STANDARD =STANDARD=STANDARD 0.1 MM=STANDARD1TO1_DIFFPAIR

0.1 MM*2TO1_DIFFPAIR 0.2 MM=STANDARD 0.1 MM =STANDARD 0.1 MM

SYNC_DATE=09/13/2012SYNC_MASTER=CHINMAY_J41

SMC Constraints

SMB_45S_R_50S SMBUS_SMC_1_S0_SDASMBSMBUS_SMC_1_S0_SDA

CHGR_CSO_NSENSE_DIFFPAIR 2TO1_DIFFPAIR

CHGR_CSO_R_P2TO1_DIFFPAIR

CHGR_CSO_R_N2TO1_DIFFPAIR

SMBUS_SMC_2_S3_SCLSMBUS_SMC_2_S3_SCL SMB_45S_R_50S SMB

SMB_45S_R_50S SMBUS_SMC_1_S0_SCLSMBSMBUS_SMC_1_S0_SCL

SENSE_DIFFPAIR CHGR_CSI_N2TO1_DIFFPAIR

CHGR_CSI_R_P2TO1_DIFFPAIR

CHGR_CSI_R_N2TO1_DIFFPAIR

CHGR_CSO_PSENSE_DIFFPAIR 2TO1_DIFFPAIR

SMB SMBUS_SMC_0_S0_SCLSMB_45S_R_50SSMBUS_SMC_0_S0_SCL

SMBSMB_45S_R_50S SMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SDA

SENSE_DIFFPAIR CHGR_CSI_P

SMB SMBUS_SMC_5_G3_SDASMBUS_SMC_5_G3_SDA SMB_45S_R_50S

SMB SMBUS_SMC_3_SCLSMB_45S_R_50SSMBUS_SMC_3_SCL

SMBSMBUS_SMC_5_G3_SCL SMB_45S_R_50S SMBUS_SMC_5_G3_SCL

SMBUS_SMC_3_SDASMBUS_SMC_3_SDA SMBSMB_45S_R_50S

SMBUS_SMC_2_S3_SDASMB_45S_R_50S SMBSMBUS_SMC_2_S3_SDA

<BRANCH>

<SCH_NUM>

<E4LABEL>

117 OF 120

71 OF 73

14 32 35 38 41 42 62 67

48

41 48

41 48

35 38 59 63

14 32 35 38 41 42 62 67

48

48

48

48

35 38 58

35 38 58

48

35 38 46 48 62

34 35 38 42 62

35 38 46 48 62

34 35 38 42 62

35 38 59 63

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J11/J13 Specific Net Properties

PHYSICAL SPACING

NET_TYPE


I348

I349


Project Specific Constraints

AUDIO * =2:1_SPACING ?

GND_P2MM*LVDS*GND

=45_OHM_SE=1TO1_DIFFPAIR*SENSE_1TO1_45S =45_OHM_SE =1TO1_DIFFPAIR=45_OHM_SE =1TO1_DIFFPAIR

0.100 MM =1TO1_DIFFPAIR*SENSE_1TO1_P2MM 0.200 MM=1TO1_DIFFPAIR =1TO1_DIFFPAIR =1TO1_DIFFPAIR

CPU_VCCSENSE GND_P2MMGND *

GND_P2MM*SATA*GND

0.20 MMGND_P2MM * 10000

0.300 MM =1TO1_DIFFPAIR* =1TO1_DIFFPAIR=1TO1_DIFFPAIR 0.100 MMSPKR_DIFFPAIR =1TO1_DIFFPAIR

GND_P2MM*PCIE*GND

THERM_1TO1_45S =45_OHM_SE =1TO1_DIFFPAIR=45_OHM_SE* =45_OHM_SE=1TO1_DIFFPAIR =1TO1_DIFFPAIR

GND * ?=STANDARD

SATA*SB_POWER PWR_P2MM*

PWR_P2MM * 100000.20 MM

?=2:1_SPACING*SENSE GND *CPU_COMP GND_P2MM

USB* GND_P2MM*GND

* =2:1_SPACINGTHERM ?

GND_P2MMCLK_PCIE *GND

SB_POWER PWR_P2MM*CLK_PCIE

SB_POWER PWR_P2MMSATA* *

ISNS_HS_GAIN_PSENSE_1TO1_45S SENSESENSE_DIFFPAIR

ISNS_HS_GAIN_NSENSE_1TO1_45S SENSESENSE_DIFFPAIR

ISNS_PANEL_NSENSE_DIFFPAIR SENSESENSE_1TO1_45S

ISNS_PANEL_PSENSE_DIFFPAIR SENSESENSE_1TO1_45S

SENSE_DIFFPAIR SENSE ISNS_CPUDDR_PSENSE_1TO1_P2MM

ISNS_P3V3S5_PSENSESENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45S ISNS_3V3_S0_PSENSESENSE_DIFFPAIR

SENSE_1TO1_P2MM ISNS_1V05_S0_PSENSE_DIFFPAIR SENSE

ISNS_1V2_S3_PSENSE_1TO1_45SSENSE_DIFFPAIR SENSE

ISNS_1V2_S3_NSENSE_1TO1_45SSENSE_DIFFPAIR SENSE

SENSE ISNS_HS_OTHER_PSENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_HS_COMPUTING_N

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_P3V3_S0_N

SENSE_DIFFPAIR SENSE_1TO1_45S ISNS_AIRPORT_NSENSE

SENSE_DIFFPAIR SENSE_1TO1_45S ISNS_AIRPORT_PSENSE

SENSESENSE_DIFFPAIR ISNS_SSD_NSENSE_1TO1_45S

CPUVR_ISUM_R_NSENSESENSE_1TO1_45S

SENSE_DIFFPAIR SENSESENSE_1TO1_P2MM ISNS_CPUDDR_N

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_3V3_S0_N

SENSE_1TO1_45S SENSE ISNS_CAMERA_PSENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE ISNS_CAMERA_NSENSE_1TO1_45S

SENSE_DIFFPAIR ISNS_P3V3S5_NSENSE_1TO1_45S SENSE

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_P3V3_S0_P

SENSE_DIFFPAIR SENSE_1TO1_45S ISNS_SSD_PSENSE

CPUVR_ISNS1_P_RSENSE_1TO1_P2MM SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE CPUVR_ISNS2_NSENSE_1TO1_45S CPUVR_ISNS2_PSENSE_DIFFPAIR SENSE

THERMTHERM_1TO1_45SSENSE_DIFFPAIR TBT_MLBBOT_THMSNS_P

SENSE_DIFFPAIR THERMTHERM_1TO1_45S TBTTHMSNS_D2_R_NSENSE_DIFFPAIR THERMTHERM_1TO1_45S TBTTHMSNS_D2_R_P

TBTTHMSNS_D2_PSENSE_DIFFPAIR THERMTHERM_1TO1_45S

CPUVR_ISNS1_NSENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE

SENSE CPUVR_ISUM_R_PSENSE_1TO1_45S

ISNS_BMON_GAIN_PSENSESENSE_DIFFPAIR SENSE_1TO1_45S

ISNS_1V05_S0_NSENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE ISNS_HS_COMPUTING_P

SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE CPUVR_ISNS1_P

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE TBDTHMSNS_D2_NSENSE_DIFFPAIR SENSE TBDTHMSNS_D2_PSENSE_1TO1_45S

SENSESENSE_1TO1_45SSENSE_DIFFPAIR CPUTHMSNS_D2_NSENSE_DIFFPAIR SENSE CPUTHMSNS_D2_PSENSE_1TO1_45S

THERMTHERM_1TO1_45SSENSE_DIFFPAIR MLBBOT_THMSNS_D3_NTHERMTHERM_1TO1_45S MLBBOT_THMSNS_D3_PSENSE_DIFFPAIR

SENSE_1TO1_P2MMSENSE_DIFFPAIR CPUVCCIOS0_CS_NSENSE

SENSESENSE_1TO1_P2MM CPUVCCIOS0_CS_PSENSE_DIFFPAIR

THERM_1TO1_45S THERM TBTTHMSNS_D2_NSENSE_DIFFPAIR

THERM_1TO1_45S THERM TBT_MLBBOT_THMSNS_NSENSE_DIFFPAIR

SENSE_DIFFPAIR INLET_THMSNS_D1_PTHERMTHERM_1TO1_45S

SENSE_DIFFPAIR INLET_THMSNS_D1_NTHERM_1TO1_45S THERM

SENSE_1TO1_45SSENSE_DIFFPAIR ISNS_BMON_GAIN_NSENSE

SENSE_1TO1_45S ISNS_HS_OTHER_NSENSE_DIFFPAIR SENSE

CPUVR_ISNS1_N_RSENSE_1TO1_P2MM SENSE

SPKRAMP_INR_P1TO1_DIFFPAIR AUDIOAUD_DIFF

SPKRAMP_INR_N1TO1_DIFFPAIR AUDIOAUD_DIFF

MAX98300_R_P1TO1_DIFFPAIR AUDIO

SPKR_DIFFPAIR AUDIOSPKR_OUT SPKRAMP_ROUT_P

MAX98300_R_N1TO1_DIFFPAIR AUDIO

SPKR_DIFFPAIR AUDIOSPKR_OUT SPKRAMP_ROUT_N

PP3V3_S0SB_POWER

SB_POWER PP3V3_S5

ISNS_LCDBKLT_PSENSE_DIFFPAIR SENSESENSE_1TO1_45S

SENSE_DIFFPAIR SENSE ISNS_LCDBKLT_NSENSE_1TO1_45S

GNDGND

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<rdar://component/508414> J41 HW EE Schematic | DVT<rdar://component/508413> J41 HW EE Schematic | EVT<rdar://component/508412> J41 HW EE Schematic | Proto 1

<rdar://component/497588> MobileMac HW | Layout<rdar://component/497585> MobileMac HW | New Bugs

Other Info:

<rdar://component/497591> MobileMac HW | TaskMobileMac HW Radar:

afp://kismet.apple.com/Kismet-Projects/J41-J43

Useful Wiki Links:

Kismet:

<rdar://component/497589> MobileMac HW | Architecture<rdar://component/497590> MobileMac HW | Investigation

Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventionsSchematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design

Page Allocations - <rdar://problem/11791318> 2012 Schematic Page Allocations

<rdar://component/497587> MobileMac HW | Schematic

<rdar://component/512995> J41 HW EE Schematic | Pre Proto 1<rdar://component/508389> J41 HW EE Schematic | Proto 0Change List:

Reference


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w w w . c h i n a f i x . c o m - Assistenza PC · 870-5071 870-1940 ALL ALT POGO PIN W_O CAP ......

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