Vsia Signal Integrity

8/2/2019 Vsia Signal Integrity

1/65

VSI AllianceTM

Signal Integrity VSI Specification Version 2.0

(IMP 1 2.0)

Signal Integrity Sub Development Working Group

[SI sub-DWG of the Implementation DWG ]

Released January 2004


2/65

i

Signal Integrity Document Sub-Development Working Group

Members of the Signal Integrity Sub-Development Working Group:Motorola Intel CorporationIBM Cadence Design Systems, Inc.ARM PhillipsVSIA Japanese Special Interest Group InfineonLucentCOMLsi

The participants include analog/mixed-signal designers, mixed-signal VC providers, Process Design Kitengineers, EDA developers, CAD Research engineers, and Microprocessor designers.

Active Contributors:Juan-Antonio Carballo (Chair)... IBMRaminderpal Singh. .....................................................................IBMPrashant Saxena .Intel CorporationFrancois Clement. Cadence Design Systems, Inc.Steffen Rochel Cadence Design Systems, Inc.Savithri Sundareswaran .. MotorolaKaushik Gala . MotorolaChanhee Oh .Motorola

Previous Contributors: Paul Hoxey ... ARM plcDavid Overhauser . Cadence Design Systems, Inc.Takahide Inoue .VSIA Japanese Special Interest Group

Special acknowledgment goes to the following: Henry Chang, Chair of the VSIA AMS DWG ...Cadence Design Systems, Inc.Paul van de Wiel ..Philips ResearchLaurence H. Cooke VSIA

Also, the team would like to thank:The VSIA AMS DWG membershipKang Lee .Lucent Microelectronics

Silvia Straehle .... Infineon TechnologiesThomas Brandtner .. Infineon TechnologiesRaj Nair..... .ComLSI


3/65

VSI Alliance (IMP 1 2.0 )

ii

Copyright 2004 byVSI Alliance, Inc.

401 Edgewater Place, Suite 600Wakefield, MA 01880 USA

Phone: (781)-876-8822, Fax: (781) 224-1239http://www.vsi.org, [email protected]

This document may be downloaded by VSI Alliance Members for personal use from the VSI Alliance members website

at http://members.vsi.org . All other rights reserved by VSI Alliance, Inc.

VSI Alliance is a trademark of the VSI Alliance, Inc. All other trademarksare the property of their respective owners.


4/65


iii

Signal Integrity VSI Specification Version IMP 1 2.0

(IMP 1 2.0)

NoticeThe VSI Alliance (VSIA) is the copyright owner of the VSIA IP identified above. The VSIAwill make royalty-free copyright licenses for this IP available to VSIA Members.Non-members must pay a fee for the copyright license. Use of the IP by members andnon-members of the VSIA is subject to the terms of the license. You are not entitled to use theVSIA IP unless you agree to the terms of the license (and, if applicable, pay the fee). Thelicense terms are set forth on the website of the VSIA at http://www.vsi.org .

THE VSIA IP IS PROVIDED BY VSIA ON AN AS-IS BASIS, AND VSIA HAS NOOBLIGATION TO PROVIDE ANY LEGAL OR TECHNICAL ASSISTANCE INRESPECT THERETO, TO IMPROVE, ENHANCE, MAINTAIN OR MODIFY THE VSIAIP, OR TO CORRECT ANY ERRORS THERE IN. VSIA SHALL HAVE NOOBLIGATION FOR LOSS OF DATA OR FOR ANY OTHER DAMAGES, INCLUDINGSPECIAL OR CONSEQUENTIAL DAMAGES IN CONNECTION WITH THE USE OFTHE VSIA IP BY SUBSCRIBER. VSIA MAKES NO REPRESENTATIONS ORWARRANTIES, EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANYWARRANTY AS TO INFRINGEMENT, OR THE IMPLIED WARRANTIES OFMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. SUBSCRIBER

SHOULD BE AWARE THAT IMPLEMENTATION OF THE VSIA IP MAY REQUIREUSE OF A SUBJECT MATTER COVERED BY PATENT OR OTHER INTELLECTUALPROPERTY RIGHTS OF THIRD PARTIES. NO LICENSE, IMMUNITY OR OTHERRIGHT IS GRANTED BY THIS LICENSE IN ANY SUCH THIRD-PARTY RIGHTS.NEITHER VSIA NOR ITS MEMBERS TAKE ANY POSITION WITH RESPECT TO THEEXISTENCE OR VALIDITY OF ANY SUCH RIGHTS.


5/65


iv

Table of Contents 1. Overview .. 1

1.1 Scope . 11.2 Assumptions . 11.2.1 Technology . 21.2.2 Product trends 21.2.3 Design Methods 21.2.4 Organization of document . 31.2.5 Relationship to I-V and AMS Specifications 31.3 Methodology Description for VC Usage 41.4 Referenced IP 41.5 Definition of Terms 51.6 Summary of Deliverables 6

1.6.1 Key to Deliverables Level of Requirements 61.6.2 Definitions of Deliverables Table Columns 71.6.3 Summary of Deliverables Table 7

2. Specification of Deliverables . 102.1 Interconnect Crosstalk (Voltage Noise and Delay Variance) 102.1.1 Overview ..... 102.1.2 Electrical data 10

2.1.2.1 Maximum permissible noise propagating into input ports . 102.1.2.2 Maximum permissible external (to VC) crosstalk coupling and effective aggressor slewfor failure- and delay-critical sensitive nets (if any) inside VC 112.1.2.3 Maximum noise possible at output ports (due to propagation) 11

2.1.2.4 Electrical characteristics for strong potential aggressors (for OTH signals) 112.1.2.5 Electrical characteristics for failure- or delay-critical sensitive VC nets122.1.2.6 Best and worst case slew permissible at input ports 122.1.2.7 Best and worst case slew at output ports (and variation with load) 12 2.1.2.8 Maximum permissible load/distributed RC driven by output ports 12

2.1.3 Physical data 132.1.3.1. Location of failure- or delay- sensitive interconnect VC polygons 132.1.3.2. Location of strong potential OTH aggressors lying within VC 132.1.3.3 Location of top-layer/peripheral supply and ground wires 142.1.3.4 No-fly zone /external shielding requirements 142.1.3.5 Safe regions for OTH signals (possibly classified by slew) 14

2.1.4 Timing data 14

2.1.4.1. Variation of timing arcs within VC with external crosstalk 142.1.4.2. Transition windows available at output ports 152.1.4.3. Transition windows required at input ports 152.1.4.4. Transition windows for strong potential aggressors (for OTH signals) or failure/delaycritical sensitive nets lying within VC 15

2.1.5 Logical data 152.1.5.1. Mutex/One-hot relationships required between input signals 152.1.5.2. Mutex/One-hot relationships available between output signals 16


6/65


v

2.2 Signal Electromigration 162.2.1 Electrical Data 16

2.2.1.1. Current density limits on metal and via layers 172.2.1.2. Max load for electromigration limits on outputs 172.2.1.3. Max slew rate for electromigration limits on inputs 17

2.2.1.4 Max Switching factor 172.2.1.5. Drive Strength 172.2.1.6. Input Load . 18

2.2.2 Physical Data . 18

2.3 Supply and Ground Grid Noise & Electromigration . 18 2.3.1 Overview 182.3.2 Electrical data Specification 18

2.3.2.1 Specification Requirements for Static Power Model 182.3.2.2 Specification Requirements for Dynamic Power Model 19

2.3.3 Physical data 202.3.3.1 External Geometrical data of the supply and ground nets (supply and ground

ports)202.3.3.2 Internal Geometrical data of the supply and ground nets 21

2.3.4 Timing data 212.3.4.1 Variation in timing on output pins (delay & edge rates) due to IR drop in power grid 212.3.4.2 Variation in timing on input pins (setup/hold time) due to IR drop in power grid 22

2.3.5 Multiple power supplies for analog blocks, multi Vt circuits, pads 222.3.6 Supply and Ground Electromigration Verification 22

2.4 Substrate Noise and Coupling 23 2.4.1 Overview 232.4.2 Electrical data 23

2.4.2.1. Block-level impedance model . 23

2.4.2.2. Noise sources for aggressor access ports . 242.4.2.3. Maximum allowed noise for each victim access port 24

2.4.3 Physical data 252.4.3.1 Regions 262.4.3.2. Substrate access ports . 27

2.5 SI Requirements Document 28

3. Design Guidelines . 28

3.1 Interconnect Crosstalk (Voltage Noise and Delay Variance) 28

3.2 Inductance effects 303.3 Signal Electromigration 323.4 Supply and Ground Grid Noise & Electromigration . 333.4.1 IR-drop in the Supply and Ground Wires (Grid) .. 33

3.5 Substrate Noise and Coupling 353.6 Other Important SI Effects 36

Appendices . 38


7/65


vi

A Implementation of Specifications on an Example Design .. 38A.1 Overview of SoC Design . 38A.2 Example Deliverables 39

B Table mapping implementation deliverables 47

C Interconnect-centric existing standards analysis 49D Glossary of Acronyms 57E Bibliography 58


8/65


Copyright 2004 by the VSI Alliance, Inc.All Rights Reserved.

1

1. Overview

1.1 ScopeThe scope of this document is to specify and explain deliverables, data formats,associated design guidelines, and example designs for the signal-integrity (SI) issuesof both digital and analog mixed-signal virtual components (VC) in SoC design.This specification is focused on SI issues in the communication between the VCauthors and integrators for the integration of Digital and Analog Mixed-Signal blocks(VC) in SoC designs, including design of the interface. It is assumed that the virtualcomponents are provided for integration as hard blocks.

The scope of the work is defined by the boundary conditions, and is currently limited tosupply and power grids, interconnect crosstalk, and substrate coupling, both foruniformly doped silicon substrates and silicon substrates with an EPI layer on heavilydoped bulk substrates. This document also discusses the issues related to power gridand signal electromigration. Issues such as IC package noise are very important tounderstanding the noise SI issues in SoC design, but consistent with other VSIAspecification documents, they are currently out-of-scope.This specification focuses on the 0.18um process generation dealing with issues thatmay occur down to 0.07um and beyond. The SI issues covered in this document areexperienced in processes >0.18um, and much of this document can be applied to helpVC transfer in these technologies. However, the focus of this work is on a specific

technology node range that meets the design requirements of the majority of VCauthors and integrators.The scope of this document has been bounded by the following considerations: (a)Current and future severity and seriousness of the issues, (b) Verifiability beforemanufacturing on silicon, (c) Appropriateness for the documented informationbetween the VC author and integrator.With respect to Version 1.0, this document incorporates (a) the addition of a table inAppendix B, mapping SI deliverables to AMS and I-V deliverables, (b) an analysis ofemerging and existing standards, and their SI extensions in Appendix C, with a viewtoward future unified wire models, (c) further content across the document about theimpact of inductance on crosstalk and supply noise, and (d) separation of the SignalEM sub-section from the crosstalk section (Sections 2.2 and 2.1, respectively).

1.2 Assumptions The following assumptions attempt to identify SI problems in SoC designs, and howspecifications provide value to designers. The assumptions are divided into threecategories: technology, product trends, and design methods.


9/65



2

1.2.1 Technology The following assumptions are made about the severity of the SI problems from atechnology or process point of view:

As published in the annual International Technology Roadmap for Semiconductor (ITRS)[ITRS], CMOS process technology progress is still marching toward the UDSM area.According to the 1999 ITRS document, the 2002 process generation will reach 0.13um,and then 90nm in a few years.

Because of necessity of the non-linear shrink of dimensions, signal interference betweenneighboring wires become more tangible and make SoC behavior unstable.

Although new metal materials such as copper can delay many problems by a processgeneration or so, thinner and narrower metal layers are required for power supply andground wires, so some key

signal interconnects may suffer from electromigration problems.

1.2.2 Product Trends In the past, the semiconductor industry and system manufacturers have enjoyedperformance improvements through Moores law. Now, leading edge products arelooking for chips containing multi-million gates running at speeds close to 2GHz.These performance and packaging density needs lead to severe design challenges:

Rising power density will cause both static and dynamic thermal interferences betweenVCs.

High slew rate and narrow skew margins for high performance chips make designsunmanageable in terms of hard-to-predict signal interference between neighboringinterconnects.

1.2.3 Design Methods It is very common that the chip designs over a few million gates are developed throughconcurrent and collaborative work of several design teams either in the same ordifferent organizations, or even in different businesses. This causes additionaldifficulty in necessary information sharing and feedback among the participatingdesigners. Categories of this information include:

Electrical information, such as static or dynamic voltage changes on the block powersupply and ground terminals, allowance of noise level on the block input terminals, andpossible noise levels on the block output terminals

Physical layout information, such as the location of noise-sensitive or aggressive wires,blockage for the chip-level interconnect, allowable space for signal feed-through, andsupply and ground wire connection strategy to ensure sufficient current capacity for blockinternal supply and current feed-through

Timing information, such as the slew allowance on block input terminalsAbove all, these specifications attempt to make the work of designers anddesign-managers easier when they have to share their designs with internal or


10/65



3

external partners. In one sense, these specifications define not only the necessaryinformation flow from VC author to integrator, but also the information flow from VCintegrators and manufacturers to VC authors.

1.2.4 Organization of Document

This document has been written for designers experienced in the SI issues covered.The document does not discuss the background to the issues. For an in-depth tutorialon each of the issues, as well as advanced coverage of the topics, the reader isreferred to [Singh01].In the preparation of this document, attention has been paid to the way in which thespecifications will be read. It is understood that readers have very different technicalbackgrounds and requirements, and may not need to read all the sections. Forexample, analog and process engineers may read only Section 3.3, Substrate Noiseand Coupling, as they try to author or integrate analog VCs. Conversely,microprocessor designers may be only interested in Section 2.1, InterconnectCrosstalk (Voltage Noise and Delay Variance) and Signal Electromigration. With this

understanding in mind, the document has been structured such that there is no directoverlap between the sections, so that each section can be read separately. Thedocument is divided into sections relating to the following SI issues: InterconnectCrosstalk (Voltage Noise and Delay Variance) and Signal Electromigration, Supplyand Ground Noise and Electromigration, and Substrate Noise and Coupling.

1.2.5 Relationship to I-V and AMS Specifications The SI specification overlaps into design scopes covered by the Implementation-Verification (I-V) and Analog Mixed-Signal (AMS) specifications. Therefore, it isimportant that the reader understands the emphasis and focus of this document, andhow to apply the specifications from each area effectively. The I-V and AMS

documents cover the broad requirements for designing and integrating digital andanalog VCs. The SI work overlays important (and many times critical) requirementsabove the ones described in those documents, and as such borrows many of theformats from them (see Appendix B). Figure 1 below shows a high-level flow for usingthe various specification documents in an SoC design.


11/65



4

Figure 1: High-level Methodology for Using the Specifications for SI, I-V, and AMS

This document uses different attributes of the formats to specify SI-relateddeliverables. For example, SDF, SPEF, VC Hspice, and GDSII are commonly referredto in all three documents. This allows the reader to accomplish compliance with theuse of standard formats.

1.3 Methodology Description for VC Usage SI issues are very much related to issues in the physical silicon process. For example,detailed information about the target process is necessary for VC authors to make SIdata useful for VC integrators. It is also crucial for building first-time success for VCs in

the target SoC. In some cases, especially for high performance design, VC authorsneed to define SI specifications such that the VC integrator is able to understand theconditions in which the VC will work.VC integrators sometimes explore details of the VC to be used, but they are oftenrestricted by business conditions. In any case, it is necessary to have compact yetsufficiently precise abstracted SI models, since full SI verification is too expensive inactual SoC designs.

1.4 Referenced IPSimilar to other VSIA specifications, the proposed approach is to leverage existingstandards (publicly available industry-wide formats and models) as much as possible.However, it has been observed that there is a need to select and combine parts ofexisting intellectual property (IP) to build concise and consistent specifications. Thefollowing standards are used in this specifications document, as deliverables:

Spice: VC Hspice 1.0a (Spice)

Owner: Synopsys CorporationStatus: Licensed through VSIA Technology Contribution Agreement

Analog/MSVC

Digital VC

AMS Spec I-V Spec

SI Spec SI Spec

VC Integration


12/65



5

http://www.vsi.org

GDSII: GDSII Stream Format 6.0.0

Owner: Cadence Design Systems, Inc.Status: Licensed through VSIA Technology Contribution Agreement

http://www.vsi.org SPEF: IEEE P1481, 1998

Owner: IEEEStatus: IEEE Ballot Standardhttp://www.eda.org/dpc

SDF: IEEE P1497

Owner: IEEEStatus: IEEE Ballot Standardhttp://www.eda.org/sdf

VC LEF: VC LEF 5.5

Owner: Cadence Design Systems, Inc.Status: Licensed through VSIA Technology Contribution Agreementhttp://www.vsi.org

PDEF: IEEE P1481, 1998

Owner: IEEEStatus: IEEE Ballot Standardhttp://www.eda.org/dpc

1.5 Definition of TermsFor clarity, the following terms are defined below. For a detailed listing of acronymsused in this document, see Appendix C, Glossary of Acronyms . A complete Definitionof Terms can be found in the VSIA Taxonomy Document [VSIA].RTL source Defines the VC source description, and is the primary input for the

implementation and verification of the VC within a system-chip design.Basic delay model Defines timing specification of the VC.Timing analysis model Defines the static timing characteristics of the VC.Power model Defines the power specification of the VC.

Peripheral interconnect model (PIM) Specifies the interconnection RCs for theperipheral interconnect between the physical I/O ports and the internal gates ofthe VC.

Physical blocks A model of the physical implementation of the VC and the systemchip.

VC port The pad or point of interconnection between the VC and the system chip.


13/65



6

Behavioral model Describes the component function and timing without describingthe internal structure.

Cell-level netlist A structural interconnection of design objects ranging from simplelogic gates to complex functions.

Circuit-level netlist A structural interconnection of semiconductor devices such astransistors, resistors, and capacitors.

Crosstalk Any deviation from the ideal signal waveform propagating in aninterconnect wire caused by signal transitions in other wires in the neighborhood.

Slew The slope of a digital signal propagating in an interconnect (in voltage changeper unit time).

Transition window The temporal interval containing every instant within a clockcycle at which a specified signal transition may occur.

Miller Coupling Factor In the context of interconnects, the multiplier used for thecapacitive coupling from neighboring wires to account for the impact on the delaybecause of their simultaneous switching.

Timing arc The input pin to output pin delay between the pins of a VC or cell.Mutex A logical guarantee of the mutual exclusivity of the transitions of two signals.One hot A set of signals such that exactly one of them is active at any instant.

1.6 Summary of DeliverablesNote that Appendix A includes an example design that applies the specifications listedbelow.SI in SoC designs is an emerging topic, so many of the specifications are currentlydefined as Document , with some Comments provided where appropriate. Many of thecomments discuss possible standards that may not yet be endorsed by VSIA. It is

expected that future specifications and standards will address emerging industrystandards.The formats specified in this document complement those of other DWGs in VSIA.However, the formats in this document do not directly overlap other VSIA documents,including the I-V and AMS specifications. Where formats are specified differently fromAMS, I-V, and VCT, the format is necessary due to additional information specificallyneeded for SI. Section 1.2.5 describes the use-model of this document, with relation tothe AMS and I-V specifications.

1.6.1 Key to Deliverables M MandatoryCM Conditionally MandatoryR RecommendedCR Conditionally RecommendedWhere CM or CR has been specified, the condition is provided in the appropriatesub-section in Section 2 of this document.Where document and any other formats are specified, all are required, as opposed to


14/65



7

any one of the formats being acceptable to meet the deliverable.

1.6.2 Definition of Columns in Summary of Deliverables Table Section The section number referred toDeliverable A summary of the deliverable

Currently Used Formats Standards used in current design flowsVSIA Specified Format The VSIA endorsed and specified format. Where two formatsare specified, both are required.SI Hard The Level of Requirement. All deliverables for this document are for HardVCs only.Comply Enables the user to check off requirements when using this tableComments The conditions for the relevant deliverables

1.6.3 Summary of Deliverables TableWith respect to version 1, this table separates the interconnect crosstalk section and

the signal electromigration section.Table 1: Summary of Deliverables Table (Continued)

Section Deliverable Currently

Used

Formats

VSIA

Specified

Format

SI

Hard

Comply Comments

2.1. Interconnect Crosstalk

(Voltage Noise and Delay Variance)

2.1.2 Electrical data

2.1.2.1. Maximum permissible noise propagating into

input ports

VC

Hspice

CM If available,

otherwise

document inSection 2.4


15/65



8

2.1.2.2. Maximum permissible external (to VC) crosstalk

coupling and effective aggressor slew for

failure- and delay-critical sensitive nets (if any)

inside VC

SPEF,

Document

CM If available,

otherwise

document in

Section 2.4

2.1.2.3. Maximum noise possible at output ports (due to

propagation/coupling within VC)

VC

Hspice

CM If available,

otherwise

document in

Section 2.4

2.1.2.4. Electrical characteristics for strong potential

lying within VC

2.1.2.4.1 I/O Driver Models VC

Hspice,

R

2.1.2.4.2 Interconnect Models SPEF R

2.1.2.5 . Electrical characteristics for failure- or

delay-critical sensitive nets lying within VC

VC

Hspice,

SPEF

R

2.1.2.5.1 I/O Driver Models VC

Hspice,

R

2.1.2.5.2 Interconnect Models SPEF R

2.1.2.6. Best and worst case slew permissible at input

ports VC

Hspice,

Document

2.1.2.6.1 Min/max Slew Limits Document M

2.1.2.6.2 Input environment models VC

Hspice,

M

2.1.2.7. Best and worst case slew available at output

ports (and its variation with load)

2.1.2.7.1 Min/max Slew Limits Document M

2.1.2.7.2 Driver Models VC

Hspice,

M

2.1.2.8. Maximum permissible load/distributed RC that

can be driven by output ports

SPEF M

2.1.3. Physical data

2.1.3.1. Location of failure- or delay-critical sensitive

interconnect polygons inside VC

PDEF M

2.1.3.2. Location of strong potential aggressors (for

OTH signals) lying within VC

PDEF M

2.1.3.3 Location of top-layer/peripheral supply and

ground wires inside VC

PDEF M

2.1.3.4 No-fly zone or external shielding requirements PDEF M

2.1.3.5 Safe regions for OTH signals (possibly

classified by slew)

PDEF R

2.1.4. Timing data


16/65



9

2.1.4.1. Variation of timing arcs within VC with external

crosstalk

SDF CM If available,

otherwise

document in

Section 2.4

2.1.4.2. Transition windows available at output ports SDF M

2.1.4.3. Transition windows required at input ports SDF M

2.1.4.4. Transition windows for strong potential

aggressors (for OTH signals) or failure/delay

critical sensitive nets lying within VC

SDF M

2.1.5. Logical data

2.1.5.1. Mutex/One-hot relationships required between

input signals

Pathmill

cfg files

Document M

2.1.5.2. Mutex/One-hot relationships available between

output signals

Pathmill

cfg files

Document M

2.2. Signal Electromigration 2.2.1. Electrical Data2.2.1.1. Current density limits on metal and via layers Document M2.2.1.2. Max load for electromigration limits on outputs VC

Hspice

M

2.2.1.3. Max slew rate for electromigration limits on inputs SDF R2.2.1.4 Max Switching factor VC

Hspice

R

2.2.1.5 Drive Strength Document M2.2.1.6 Input Load Document M2.2.2 Physical Data GDSII M

2.3. Supply and Ground Grid Noise &

Electromigration

2.3.2. Electrical data Specification

2.3.2.1 Specification Requirements for Static Power

Model

Document M

2.3.2.2 Specification Requirements for Dynamic Power

Model

Document R


2.3.3.1 External Geometrical data of the supply and

ground nets (supply and ground ports)

VC LEF M

2.3.3.2 Internal Geometrical data of the supply and

ground nets

Document M

2.3.3 Timing data

2.3.4.1 Variation in timing on output pins (delay & edge

rates) due to IR drop in power grid

Symopsys

.lib file

Document M

2.3.4.2 Variation in timing on input pins (setup/holdtime) due to IR drop in power grid

Symopsys.lib file

Document R

2.3.4.3 Variation in Timing due to inductive noise .lib file Document CR

2.3.5 Multiple power supplies for analog blocks,

multi Vt circuits, pads

Document M

2.3.6 Supply and Ground Electromigration

Verification

Document M

2.4. Substrate Noise and Coupling


17/65



10

2.4.2. Electrical data2.4.2.1. Block-level impedance model VC

Hspice

M

2.4.2.2. Noise sources for aggressor access ports VC

Hspice

M

2.4.2.3. Maximum allowed noise for each victim accessport

VC

Hspice

M


2.4.3.1 Regions Document M

2.4.3.2. Substrate access ports Annotated

GDSII

Document M

2.5. SI Requirements Document Document M

2. Specification of Deliverables

2.1 Interconnect Crosstalk (Voltage Noise and Delay Variance)

2.1.1 Overview

Although the techniques used to combat crosstalk vary from one design/integration house to another, itis possible to abstract the issues that are common to all interconnect crosstalk scenarios. The data thatneeds to be communicated for effective control of crosstalk effects across the boundary of the VC canbe listed at a level high enough to be largely independent of the signal integrity methodologies andalgorithms employed by the designers and integrators. Ideally, it includes some metrics for the

maximum permissible noise pulse (along with slew and transition window requirements) at the inputports and the maximum noise pulse possible at the output ports (along with slews and transitionwindows and their variation with external load). The VC author can also specify external no-flyzone/shielding requirements. The goal is to present a simplified yet reasonably accurate model for theVC while still preserving its gray/black box nature. In a similar vein, although crosstalk due to the boardand packaging is out of the scope of this document, it is important to note that some interface modelingmay be required even for these levels of the hierarchy in order to analyze and optimize crosstalkaccurately. Furthermore, since long global wires at the chip integration level are typically more prone tocrosstalk than local VC wires, it is good practice for the VC authors to identify and communicate anydata within the VC that can be exploited by the chip integrator to make the global convergence easierand the design more crosstalk- immune.

For potential victim/aggressorwires, the electrical data should be cross-referenced to correspondinggeometric and/or timing data; however, VC hiding issues may dictate that some or all of these wires notbe identified logically. In such scenarios, it may make sense to merely index the wires of interest withoutnaming them (or giving them dummy names), and then cross-referencing all the relevant data for the i th wire of interest across the various specification files.

2.1.2. Electrical data


18/65



11

Since noise is primarily an electrical phenomenon, VC authors should abstract and communicateelectrical and parasitic parameters for ports as well as nets/paths on which they anticipate noiseproblems. In general, the electrical data includes wire parasitics for the selected wires, along withoutput impedance for their drivers and the input impedances for their receivers. Another issue thatmerits some debate is the noise model itself. This is currently an area of active research both withinacademia and industry. Models range from simple noise peaks to accurate waveforms. It is expectedthat different applications will opt for different levels of accuracy in their noise model, depending on theanticipated severity of the crosstalk experienced by them.

2.1.2.1. Maximum permissible noise propagating into input portsThis documents the VC authors assumption about the worst case noise pulse at the VC inputs that cansafely propagate into the VC without causing any failures (with the external crosstalk being specified asdocumented in 2.1.2.2 below). It must be guaranteed by the chip integrator for the VC to functioncorrectly. Depending on the noise model adopted, this data item can vary from a simple mV peakspecification or combination of pulse width and peak to a piecewise linear (PWL) waveform.

CONDITIONALLY MANDATORYSpecifications : VC Hspice (for noise waveforms, assumes pulse limits can be expressed)Condition : VC Hspice format is available. Otherwise, provide document in Section 2.4.

2.1.2.2. Maximum permissible external (to VC) switching cross-coupling and effective aggressor slew for failure- or delay-critical sensitive nets (if any) inside VC This data item specifies the maximum switching cross-coupling capacitance that can be safely experienced by sensitive nets within the VC (for a given pulse width/height)without creating negative slacks/races. This data item should be interpreted either in conjunction with data about its physical location and timing windows (see 2.13.1 and 2.1.4.4 below) as well as on electrical characteristics of the sensitive VC nets (see 2.1.2.5 below), or in the context of broad safe zones required around the VC (when the safe zone is predicated on the absence of exceptionally strong over the hierarchy (OTH) aggressors; see 2.1.3.4 and 2.1.3.5 below.

CONDITIONALLY MANDATORYSpecifications : SPEF to capture distributed coupling if required; else, a mere maximum permissiblecapacitance value for each sensitive net. Effective aggressor slew represented in mV/ps.Condition : SPEF format is available. Alternatively, document can be provided if the SPEF format is notavailable.Comments : Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.

2.1.2.3. Maximum noise possible at output ports (due to propagation/coupling inside VC)

This documents the worst case noise pulse that the integrator can expect at the VC outputs, and helps theintegrator accurately analyze the noise/delay experienced by the global wires connected to these ports (and topropagate the noise into downstream logic along these wires).

CONDITIONALLY MANDATORYSpecifications : See specifications for 2.1.2.1 above.

2.1.2.4. Electrical characteristics for strong potential aggressors (for OTH signals) lying inside VCThis data, although optional, can help the chip integrator to achieve global convergence by avoiding thelayout ofsensitive OTH inter-VC wires in high risk regions dominated by strong intra-VC aggressors thatwould otherwise not be visible. It should include a model for the driver as well as the interconnect. This


19/65



12

data item should be interpreted in conjunction with the corresponding physical data item 2.1.3.2.Comments : Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.

2.1.2.4.1 Driver ModelsRECOMMENDEDSpecifications : VC Hspice.

2.1.2.4.2 Interconnect ModelsRECOMMENDEDSpecifications : SPEF.2.1.2.5. Electrical characteristics for failure - or delay-critical sensitive nets lyinginside VCAs with 2.1.2.4, this optional item can help the chip integrator analyze sensitive VC wires that wouldotherwise not be visible, in order to ensure that global wires close to these wires are not strong enoughto causefailures within the VC. It should include models for the driver, the interconnect and the receivers.Comments : Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.

2.1.2.5.1 Driver ModelsRECOMMENDEDSpecifications : VC Hspice.

2.1.2.5.2 Interconnect ModelsRECOMMENDEDSpecifications : SPEF.

2.1.2.6. Best and worst case slew permissible at input portsIf the transition slopes of the input signals of the VC are too high, it can cause them to act asunexpectedly strong aggressors within the VC. Conversely, too low slopes can cause them to bevictimized severely. The permissible slew range at the input ports documents the assumptions made by

the VC author and must be guaranteed by the VC environment for the VC to function correctly asadvertised.

2.1.2.6.1 Min/max Slew LimitsMANDATORYSpecifications : DocumentComments: To be specified in units of mV/ns in the SI Requirements Document

2.1.2.6.2 Input environment modelsMANDATORYSpecifications : VC HspiceComments: A model for the environment driving the port.

2.1.2.7. Best and worst case slew available at output ports (and its variation with load)The slew ranges at the output ports can be used by the integrator to accurately analyze the noise/delayexperienced by the global wires connected to these ports (and to propagate the noise into downstreamlogic along these wires).Comments : Note that this data is usually also included in the standard timing view of the VC.

2.1.2.7.1 Min/max slew limits


20/65



13

MANDATORYSpecifications : DocumentComments: To be specified in units of mV/ns in the SI Requirements Document

2.1.2.7.2 Driver modelsMANDATORYSpecifications : VC HspiceComments: For driver modeling (to compute variation of slew with load)

2.1.2.8. Maximum permissible load/distributed RC that can be driven by output portsAlthough this data is required primarily by the timing/performance models of the VC, it is also valuablein a signal integrity context, since it ensures that the signals in the wires inside the VC that feed theoutput ports do not become unexpected victims due to deterioration in the slew caused by excessiveload. This data could be combined with 2.1.2.7, since the driver model can lead to min/max slew rate anoutput can drive.MANDATORYSpecifications : SPEF.Comment : Note that this data item is usually also included in the standard timing view of the VC.

2.1.3. Physical dataPhysical data complements electrical data (and, at times, timing data) for potential aggressors andvictims within the VC, thus providing sufficient visibility into the VC to enable reasonably accurate signalintegrity analysis.

It can also be used to specify broad external shielding requirements for sensitive signals within the VC.

2.1.3.1. Location of failure- or delay-critical sensitive interconnect polygons inside VCThis data indicates the physical regions of the VC that must be protected from external aggressors, andshould be specified in conjunction with the electrical (and possibly timing) properties of theseinterconnects, as described in 2.1.2.5 and 2.1.4.4. A coarser (and more conservative) way ofrepresenting this is through external shielding requirements and designated no-fly zones as describedin 2.1.3.4 below.

Strong potential aggressor within VC (cross-referenced in timing

Weak potential victim within VC (cross-referenced in timing and

No fl zone

Figure 2.1.1 Physical data to be communicated (cross-referenced with electrical/timing data)


21/65



14

MANDATORYSpecifications : PDEFComments : Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.

2.1.3.2. Location of strong potential aggressors (for OTH signals) lying inside VCThis is the other side of the coin from 2.1.3.1 that dealt with potential victims within the VC. In contrast,this item deals with potential aggressors within the VC and should be specified in conjunction withelectrical (and possibly timing) data for these aggressors that can be used by the chip integrator todecide whether or not to route sensitive global wires in the vicinity of these aggressors.

MANDATORYSpecifications : PDEF Comments : Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.

2.1.3.3 Location of top-layer/peripheral supply and ground wires inside VCThis data allows the chip integrator to exploit the Vdd and Vss wireswithin the VC to provide shieldingfor sensitive global wires routed close to the VC.

MANDATORYSpecifications : PDEF

2.1.3.4 No-fly zone or external shielding requirementsThis documents the assumptions made by the VC author about the absence of external aggressorswhile designing the VC, and must be guaranteed by the chip integrator. It could involve constraintsranging from OTH supply and ground wires required in certain designated tracks to supply or groundplanes or non-metalized blockages covering designated areas over the VC.

MANDATORYSpecifications : PDEFComments : Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.

2.1.3.5 Safe regions for OTH signals (possibly classified by slew)This data item generalizes the constraints described in 2.1.3.4 by designating safe tracks or regions forglobal wires routed over/through the VC Thus, it identifies the preferred corridors for OTH signalsbased on their susceptibility to crosstalk from within the VC (as determined by their slew). In somesense, this data item is a usage guideline for the chip integrator based on the intra-VC aggressor datacommunicated in 2.1.3.2.

RECOMMENDEDSpecifications : PDEF. Also, associated with each safe region should be a document describing themin/max slew ranges (in mV/ns) for which it is safe.

2.1.4. Timing dataTiming data about sensitive/strong VC nets and VC ports complements physical and electrical datadescribed in the previous two sections (2.1.2 and 2.1.3) to enable the integrator to respect theassumptions made by the VC author while converging the VC design, It also helps plan aroundpotential problems in global nets due to crosstalk from within the VC. However, we note that withincreasing clock frequencies, transition window widening due to crosstalk and process variation, it isoften difficult to guarantee temporal separation of transitions without any underlying logical exclusivityrelationship.


22/65



15

2.1.4.1. Variation of timing arcs within VC with external crosstalkThe pin-to-pin delays (timing arcs) within the VC are computed with certain assumptions on the extentof crosstalk that the VC wires experience from signals outside the VC. Therefore, it is important todocument how these delays vary with external crosstalk. Thus, associated with each timing arc withinthe VC should be a formula or lookup table describing the delay variation with external coupling.

However, since the VC author may not wish to explicitly identify candidate victim wires within the VC, itmay be possible to give only a range for the delay variation of the timing arc. Thus, unlike the case ofdelay variation with external load, the chip integrator will be unable to explicitly compute the exact delayfor any given integration environment. (Also see 2.1.6.1 below).

CONDITIONALLY MANDATORYSpecifications : SDF (for delay variation range)Condition : SDF format is available. Otherwise, provide document in Section 2.4.

2.1.4.2. Transition windows available at output portsThis enables the chip integrator to both to carry out less conservative timing analysis by assuming MillerCoupling Factors (MCFs) of 1 for pairs of adjacent nets with non-overlapping timing windows as well asto use such signals as relative shields for each other. (Also see 2.1.5.2 below).

MANDATORYSpecifications : SDF Comments : Note that this data item is usually also included in the standard timing view of the VC.

2.1.4.3. Transition windows assumed at input portsThis describes the non-overlapping timing windows, if any, for the input signals that have beenexploited by the VC designer to enable VC convergence that must be enforced by the integrationenvironment. (Also see 2.1.5.1 below).

MANDATORYSpecifications : SDF Comments : Note that this data item is usually also included in the standard timing view of the VC.

2.1.4.4. Transition windows for strong potential aggressors (for OTH signals) or failure/delay critical sensitive nets lying inside VC This data, coupled with physical and electrical data for sensitive or exceptionallystrong nets within the VC, will allow the integrator to avoid placing strongly switchingglobal wires in the immediate vicinity of sensitive VC wires as well as sensitive globalwires in the immediate vicinity of strong aggressors within the VC. Thus, this data alsoformalizes any assumptions about the lack of external aggressors that the VC authormight have made while designing sensitive interconnects within the VC. (Also see2.1.2.2, 2.1.2.4, 2.1.3.1 and 2.1.3.2 above).

MANDATORYSpecifications : SDF Comments : Note that this data item is usually also included in the standard timing view of the VC.Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.

2.1.5. Logical dataLogical relationships among the interface signals, where available, can help make the timing and noiseanalyses less conservative by allowing the use of mutually exclusive signals as relative shields, thusenabling easier convergence of the design. This allows MCFs of 1 to be used between the coupling


23/65



16

mutex signals (i.e. signals that are mutually exclusive logically, for example, phase separated signals),rather than the more conservative MCFs used for pairs of wires without guaranteed temporalseparation. In a similar vein, one-hot signals (i.e. sets of signals such as the outputs of decoders thatare guaranteed to have at most one signal switching at any time) can also be used to make the timingand noise analyses less conservative.

2.1.5.1. Mutex/One-hot relationships required between input signalsThese are logical and phase separation relationships among the input signals exploited by the VCdesigner that must be enforced by the VCs external environment. (Also see 2.1.4.3 above).

MANDATORYSpecifications : Document.Comments : Pathmill CFG files could also be used. Indicate None in the SI Requirements Document(Section 2.4) if no instances exist.

2.1.5.2. Mutex/One-hot relationships available between output signalsThese are logical and phase separation relationships available among the VC output signals that areavailable for the chip integrator to use as a substitute for explicit shielding or to enable tighter timinganalysis. (Also see 2.1.4.2 above).

MANDATORYSpecifications : Document.Comments : Pathmill CFG files could also be used. Indicate None in the SI Requirements Document(Section 2.4) if no instances exist.

2.2 Signal Electromigration

Overview

The specifications that follow are restricted to simple electromigration checks based

on current density limits. The approach is to determine the current densities acrosseach wire segment, and then to apply limit checks to determine if the segment fails forelectromigration. In order to perform electromigration checks, VC authors andintegrators need to have information on metal layers, wire segment size, and positions.Figure 3 shows a simplified model of the specifications required for signalelectromigration checks by the VC integrator. VC authors must provide driver and loadmodels along with the switching characteristics.


24/65



17

Figure 3: Simplified View of Model for Signal Electromigration

2.2.1 Electrical Data

Electromigration checks require the knowledge of complete circuit behavior. Apartfrom the general electrical parameters like drive impedance, receiver load, and wireparasitics, the following information must be specified.2.2.1.1.1 Current Density Limits on Metal and Via Layers

The unidirectional currents have non-zero DC currents causing electromigration dueto DC current stress. Hence, DC current limits need to be specified. Anelectromigration failure due to wire self-heating also happens, due to bi-directionalcurrents. These are mainly specified using the peak- and RMS AC-current limits.MANDATORYSpecifications : Document, describing Average, Peak, RMS, width-dependent AC-and DCcurrent density limits for each metal and via layer. Temperature dependency ofthese limits may be included as well.

Comments : Note that these current density limits are generally process-specific data.2.2.1.2 Maximum Load for Electromigration Limits on Outputs

The VC author must ensure that the wiring within the VC is sufficient for the maximumreceiver load. Alternatively, the VC author may specify the maximum load on the receiverto ensure electromigration checks by the integrator. In addition to specifying maximumload for individual outputs, it may be necessary to specify maximum total receiver load forthe VC. The latter is intended for the situations where individual output load are within thespecified limit but their total load is large enough to cause electromigration violations onsignal or supply wiring within the VC.MANDATORY

Driver ModelLoadSignal Net - varying

current densities

l

w

Wire Segment


25/65



18

Specifications : VC Hspice.2.2.1.3 Maximum Slew Rate for Electromigration Limits on InputsThe input slew rate defines the switching rate within I/O and cells. Limits must be defined,such as how fast an input signal can switch to avoid electromigration-related problems inVCs.

RECOMMENDEDSpecifications : Document.Comments : SDF (the maximum transition time specified) could also be used. For more accuratemodeling, a more sophisticated input waveform description could be considered.

2.2.1.4 Maximum Switching FactorThe switching factor defines how consistently the signal switches within a given clockcycle. The factor is defined as the average number of switches per clock. The currents inthe nets are dependent on the switching factor at both inputs and outputs. Note that therecould be multiple clocks within a given block, so it is necessary to specify a maximumswitching factor.

RECOMMENDEDSpecifications : VC Hspice.Comments : Specifying complete input waveforms can derive the switching factor (although this requiresmore sophisticated models).

2.2.1.5 Drive StrengthThe drive strength of the output drivers of an VC needs to be modeled. With thisinformation, the nets connected to the output pins can be verified in context. The drivestrength model could be a simple linear model, but more sophisticated descriptions areoften necessary and should be considered.

MANDATORYSpecifications : Document.Comments : Synopsys .lib could be used if input capacitance is not voltage-dependent. This informationshould be shared with the noise models.

2.2.1.6 Input LoadInput load is required to enable verification of the nets connected to the input pins of a VCin context. Typically, this information is already contained within the timing models.MANDATORYSpecifications : Document.Comments : Synopsys .lib could be used.

2.2.2 Physical Data

The required data includes all geometrical information for the signal nets, including netnames, wire segment positions, and layer information. In order to protect the VC physicaldata, information about the input and output nets of an VC, together with the load andinput slew rate information, should be sufficient to enable electromigration checking forthe integrated VC.

MANDATORY


26/65



19

Specifications : GDSII.Comments : The physical information required can be derived from GDS, but shouldbe preprocessed in order to enable a simple and consistent usage. It is recommendedto use extended Spice equivalent binary format containing connectivity informationand parasitic RC information, including layer and wire-segment size and position. No

standard exists for this format.

2.3 Supply and Ground Grid Noise and Electromigration

2.3.1 Overview In this section, specifications are provided for dealing with supply and ground gridnoise and electromigration. See Section 3.2 for a detailed discussion of these issues.

2.3.2 Electrical Data Specification

2.3.2.1 Specification Requirements for Static Power Model Internal supply and ground grid model. Only a resistance model is required. The model

can be simple and highly reduced, up to a complete R extract of the supply and groundgrid. The VC creator will supply the model or models. There could also be a series ofmodels with increasing complexity, allowing the integrator to select the most appropriateone for a given stage of the design cycle. The integrator will build an R network for thecomplete system power grid using these models and the supply and ground connectors,which determine the connection to the supply and ground grids. The resistance model willdefine the electrical behavior between the supply and ground connectors.Comments : A binary format compatible with an RLC model is required. The model mustcontain resistance data, connectivity, and geometrical data, including layer information.

There is currently no standard covering the proposed format. A commercial example is thepower grid libraries by vendors such as Cadence Design Systems (formerly SimplexSolutions).

Minimum and maximum voltages, which must be applied to supply and ground ports toensure correct internal operation. The minimum voltage should be defined for differentconditions. For example, there should be a minimum worst case DC voltage and aminimum average supply voltage. This information allows validation at VC boundaries.

Spatial distribution of the minimum voltages within a VC must be provided in order toensure proper operation. Define areas within the VC, where the VC requires a minimalvoltage. If it is allowed to collapse the area into a single point (a device contact), then theVC creator can decide which resolution is required. On the other extreme, the VC creatormay decide to provide only one value for the whole area of the VC. The information maybe used in early design stages such as floorplanning, but is required during physicalverification. This enables validation of the VC in design context. Spatial distributedmaximum voltages for ground nets must also be defined.Comments : In the future, a binary format is required, consistent with the internal supplyand ground grid model. Currently, no such standard exists.


27/65



20

Static spatial power consumption model. In order to consider the effect of the systempower distribution network on the behavior of a VC, the spatial distribution of the powerconsumption within a VC needs to be modeled. For standard cells, a uniform distributionmay be sufficient. However, for larger VCs, the distribution will affect the IR dropdistribution within the VC, depending on the resistive path from each supply and groundport (connector) to the supply and ground pads. The power consumption model mustinclude the information where the power sinks are connected to the supply and groundgrid. The power consumption model should also include the average device capacitanceexisting between supply and ground grids. (See Figure 4.) Several power consumptionmodels may be supplied with the VC, describing average- and peak-power consumption.Comments : The model will potentially contain a large amount of information, so a binaryfile format is preferable. Currently no standard exists.Note : It is assumed that power consumption is independent of voltage drop, in order tosimplify the modeling. For standard cells or other small VCs, the power consumptionmodel and the definition of spatial distribution of the minimum supply and ground noise (orminimum supply voltage) could be simplified.

MANDATORY

Specifications : Document. There could be a simple format defining current sourcesfor each consumer, but the file format would have to be upward-compatible with thedynamic spatial power consumption model.

2.3.2.2 Specification Requirements for Dynamic Power Model

For internal supply and ground grid models, the approach is equivalent to the static powermodel described in Section 2.2.2.1. However, an RLC model rather than an R model isrequired to model the dynamic behavior of the supply and ground grid. The RLC parasiticscan be derived from the layout data.

The minimum and maximum voltage supply are the same as in the static model.

The spatial minimum and maximum voltages are the same as in the static model.

The time-varying spatial power-consumption model includes time dependency. Ratherthan using a time-independent power model, this model has time-dependency, whichallows a more accurate representation of power consumption within the VC. The dynamicpower-consumption model captures effects such as simultaneous switching. Thegeneralized power-consumption model should also include the time-dependent devicecapacitance between supply and ground grids, as shown in Figure 4. The current source isused to model the power consumption of a device or cell, and can be constant or timevarying. The generalized model also contains a time-varying device capacitance in serieswith a resistance modeling of the shielded signal-line capacitance.

MANDATORYSpecifications : Document.


28/65



21

Figure 4: Generalized Power Consumption Model

2.3.3 Physical Data As described in Section 2.2.2.1, it is necessary to preserve the geometrical shapes ofthe power ports for a VC. For validation and inspection purposes, it is also necessary

to retain an abstraction of the layout information for the VC internal supply and groundgrid.

2.3.3.1 External Geometrical Data of the Supply and Ground Nets (Supply and Ground Ports)

The specification must contain information about the geometric shape and the locationand layer of all power ports to a VC. The VC author will assume that they connected tothe power grid when the VC is integrated into a system. The geometrical data must betaken into account when the system-level supply and ground-grid network arecreated.MANDATORYSpecifications: VC LEF.Comments : Annotated GDSII should be considered.

2.3.3.2 Internal Geometrical Data of the Supply and Ground Nets

The internal supply and ground grids are modeled internally as a RLC netlist or asimplification thereof. The electrical model must retain geometrical and layerinformation in order to enable electromigration checking within the VC. This validationis required for the VC within the design context.MANDATORYSpecifications : This information is specified in Section 2.2.2.2.The internal supply and ground grid models must contain the connectivity information

between the internal supply and ground grid with the supply and ground ports of theVC.

2.3.4 Timing Data This section discusses timing variation on the I/O of the VC caused by supply andground noise. Timing violations may be the cause of internal failures, but they are notseen as timing errors from the outside. Conversely the VC may be functionally correctinternally, but timing variation of the I/O could cause a failure in the system in which


29/65



22

the VC is placed.It is the responsibility of the VC creator to take into account the timing variation causedby internal activity within the VC. The effect could be caused by an IR drop in theinternal power grid, or by coupling between signal nets. Information may be providedabout the timing variance in the clock characteristics within the VC due to its internal

power and ground noise. Clock skew and jitter often result from these supply andground level variations.The VC creator must obtain worst-case numbers when characterizing the VC. Usuallyonly a large block has sufficient internal power routing for this to be an issue. Forstandard cells, the IR drop in the power grid is external to the VC.After integrating a VC into a system, the IR drop in the supply and ground grid to theVC will cause timing variation, such as increased cell delay. There are several optionsto model this.

First, the timing model can have a voltage input, such that the voltage suppliedto the VC is a variable in the timing arcs of the VC. This would be practical for

standard cells, where transistors are close to the supply and ground connectors.But for large VCs with a complex internal supply and ground grids, it is moredifficult to obtain a simple voltage relationship, and a different approach isrequired.

Second, the VC author can create a whole series of timing models at differentvoltages, such as the support supply range. The integrator will need tools toselect the closest timing model for a given voltage, or will have to extrapolatebetween two models.

Third, the VC author may provide the signal edge placement characteristics ortiming variation as a function of not just the inputs, but also as a function of thesupply and ground levels separately rather than just the difference.

2.3.4.1 Variation in Timing on Output Pins (Delay and Edge Rates) Due to IR Drop inPower Grid

For output pins (or I/O pins driving out), the variation in timing will affect output delay(CLK to output transition), as well as edge rate or slope of the transition.MANDATORYSpecifications: Document.Comments : Synopsys .lib could be used. Potentially, ALF should be considered.

2.3.4.2 Variation in Timing on Input Pins (Setup and Hold Time) Due to IR Drop in Power Grid

As with input signals there is variation for setup and hold time.

RECOMMENDEDSpecifications: Document.Comments : Synopsys .lib could be used. Potentially, ALF should be considered.

2.3.4.3 Variation in Timing due to inductive noise

Supply and ground noise can be caused by the lumped inductance and capacitanceassociated with the power grid. The voltage noise induced due to this effect can be


30/65



23

approximated by Delta-I * sqrt(L/C). Depending upon the inductance contributed bythe supply and ground pathways, this may appear as a supply droop, a ground bounce,or a combination of both. For high-performance VCs, this noise may result infunctional system errors.A high-performance VC author may thus choose to include a corner-case model for

comprehensive verification of the VC functionality in the presence of inductance noise.To this end, a time- and voltage-dependent power consumption model, the lumpedpower loop inductance in the supply and ground paths and the VC de-couplingcapacitance between supply and ground can be used to compute the resulting supplynoise. Timing models that capture the independent effects of varying the two supplynodes can be used to detect potential errors.CONDITIONALLY RECOMMENDEDSpecifications : Document describing model and its usage.Comments : .lib and ALF could potentially be used.

2.3.5 Multiple Power Supplies for Analog Blocks, Multi-Vt Circuits, andPads MANDATORYSpecifications : Document the proposed modeling approach, which can be appliedfor blocks with multiple power supplies, such as analog blocks, multi-Vt circuits, andpads.Comments : The model content must capture each supply and ground grid within theVC. It is assumed that multiple power supplies can be individually described andverified with the proposed approach.

2.3.6 Supply and Ground Electromigration Verification

The proposed modeling approach enables verification of IR drop and electromigration.When the VC is placed in a system, the geometry of the global supply and ground netcan be calculated. Together with the internal supply and ground grids of all VCs, thecurrent distribution in the supply network can be calculated. Based on the currentdistribution and physical information, the current densities can be derived andcompared to process limits. Unlike signal electromigration verification, where mostlyAC current density limits need to be considered, DC current density limits must beconsidered for supply and ground grid electromigration verification. Electromigrationverification should not only consider current density limits, but should allow forstatistical budgeting based on mean-time-to-failure (MTF).MANDATORYSpecifications : Document; the current density limits specifications must conform tothe current density limit specification for signal electromigration.Comments : Model parameters enabling the calculation of MTF, such as parametersused in Blacks equations should be specified. Simple text format can be used todefine the process-dependent electromigration parameters.

2.4 Substrate Noise and Coupling


31/65



24

2.4.1 Overview In this section, specifications are provided for dealing with substrate noise andcoupling. See Section 3.3 for a detailed discussion of the issues and designguidelines.

2.4.2 Electrical Data An impedance model connecting all noise sources with substrate access portsdescribes a blockelectrically. Either current or voltage in time or frequency domain can be used todescribe sources. If only a transient or harmonic model is available, it should beaccurate enough to allow for conversion with Fourier transform. On the one hand,transient information is necessary for mixed-signal applications. For example, whenintegrating an ADC in a noisy digital environment, the noise level just before andduring sampling of analog data is important. A small noise level during this time cansignificantly degrade performance. Outside this critical gap, noise immunity is muchgreater.On the other hand, it is sometimes more relevant to describe how noise varies withfrequency. This is typically the case when RF blocks are integrated in a SoC design. Inthe case of an LNA, a small noise falling in the frequency band can deteriorate thenoise figure dramatically, while twice this noise level is likely to have no impact outsidethis frequency band.

2.4.2.1 Block-level Impedance Model

A block-level impedance model should include impedances between substrate accessports and ground and noise sources. As an example, this model can be provided in theform of a Spice netlist. For a victim access port, this model can be as simple as asingle component. The componentresistor or capacitoris connected betweenaccess port and ground. In addition, for an aggressor access port, the model mustinclude the internal noise source.MANDATORYSpecification: VC Hspice.Comments : At the moment, the example proposed previously does not fit with thephysical description and the design guidelines for integration. The impedance modeldoes not describe the connection from access port to substrate. That is, an accessport is by definition directly connected to the substrate. A better example is beingdeveloped to explain how the impedance model is used to represent how the circuit(the device bulks and power supplies) is connected to the substrate.

2.4.2.2 Noise Sources for Aggressor Access Ports

Noise sources can be split into device and supply noise. On the one hand, devicenoise is produced inside the VC block by switching devicesthrough capacitivecoupling or impact ionization. On the other hand, supply noise is generated at thesystem level by the sum of currents flowing through the power supply grid (as dynamicIR drop) or through package inductances (power-supply bouncing). Power-supplynoise requires system-level modeling. Device noise sources are described as either


32/65



25

independent-voltage or current sources.For each source, one of the following items must be provided:

Static noise information. In this case, noise level is assumed constant and independent oftime or frequency.

Transient noise information. This could be provided as a PWL description using Spicesyntax. A timing reference must be provided to allow for correct summation of all accessport contributions. The time reference could be provided as a delay with respect to clockedges.

Harmonic content. This is difficult to describe using standard Spice syntax. Onesuggestion is to have the block author provide detailed Fourier data. A second propositionis to deliver a PWL representation with respect to frequency. For some simple cases, suchas a VCO, a single sinusoidal source or a set of sources can be used to represent noise. Inany case, noise is represented by either magnitude and phase, or by real and imaginaryparts.

MANDATORYSpecification: VC Hspice.

Comments : The choice of Spice format seems straightforward for the impedancemodel. It should also be sufficient to describe constant noise sources andtime-dependent sources. Nonetheless, there is no easy way to describe harmonicsources. Noise sensitivity on victim nodes can be provided as a Spice comment usinga specific format that is yet to be defined.

2.4.2.3 Maximum Allowed Noise for Each Victim Access Port

For each block model, the maximum allowed noise level can be specified in the form

of branch current or node potential. This data can be provided as a constant staticvalue, or as a dynamic representation using transient and frequency dependence.A constant value represents the maximum noise threshold that a victim port mightsustain. However, using a constant sensitivity threshold might be too conservative,and can lead to unfeasible designs. Dynamic sensitivity description should bepreferred for best integration flexibility.For specific victims, such as the sample-and-hold stage in an ADC, the maximumallowed noise varies with time. In such a case, the acceptable noise level should beprovided as a function of time, with respect to an author-specified clock edge. Somevictims are more sensitive at certain frequencies. This is typically the case for RFblocks. For such applications, a description of sensitivity as a function of frequency is

required.MANDATORYSpecification: VC Hspice.Comments : This choice seems straightforward for the impedance model. It shouldalso be sufficient to describe constant noise sources and time-dependent sources.Nonetheless, there is no easy way to describe harmonic sources. Noise sensitivity onvictim nodes can be provided as a Spice comment using a specific format that is yet to


33/65



26

be defined.

2.4.3 Physical Data Physical information is fully characterized by attaching connectivity informationsuchas net nametogether with geometrical shape and doping profile for each access port.

Depending on the hierarchical view (transistor, gate, or system level), a substrateaccess port can represent the bulk connection of either a single device, a logical gate,or a functional block.Access ports can also be placed in different substrate regions, such as defaultsubstrate, n-well, deep n-well, and triple-well. This requires specific data sets toconnect region geometries with doping information as well as biasing conditions.Figure 5 illustrates an example of physical data. Regions are labeled R1 through R4,and substrate access ports (SAP) are named SAP1 through SAP6. The lower-rightcorner holds analog functions protected by a triple-well (R3). SAP4 represents thebulk of a sensitive device. SAP3 contacts R3 to an analog power supply. R1corresponds to a guard band connected to ground through SAP5.The noisy section is made up of three areas. First, noise is injected through SAP1(such as a large MOS buffer) and SAP2 (such as ground bounce on a power supply).Second and third, R2 and R4 are floating wells protecting sensitive circuitry (such asswitched capacitors), while R4 includes important lateral resistivity variations that aremodeled by SAP6.

Figure 5: Physical Data Examples

SAP1

SAP2

SAP3

SAP6

SAP Doping Profile Net Name1 Diffusion N12 Contact N23 Contact G14 Diffusion S35 Contact G26 Contact --

SAP5

R1 SAP4

Region Doping Profile Bias1 N-Well 3.3V2 Deep N -Well 1.8V3 Triple -Well 0V, 1.8V4 N-Well 1.8V

R2 R3

R4

Region

Substrate Access

Block


34/65



27

Figure 5 shows how the combination of substrate regions and substrate access ports(SAP) describe the structure of the substrates. Shape geometries (coordinates) arenot included.

2.4.3.1 Regions

Regions are used to define global change in doping profiles. Typically, a regionindicates how many PN junctions are stacked vertically in specific locations of theblock. Vertical superposition of PN junctions identifies the types of wells, such as asingle well or triple well. A region characteristic is therefore the doping data. In addition,one needs to account for the actual PN junction biasing that affects substrateparasitics. One set of biasing information must be provided for each vertical stack ofPN junctions. Hence, a triple-well structure is described with two bias voltages.Region bias is provided with geometry information, although this information iselectrical in nature. This is because biasing does not inject noise, but it does impactthe RC substrate model similar to the way geometry does.MANDATORY

Specification: Document.Comments : Annotated-GDSII Format (AGF) can be used for geometry, along withcross-reference files for electrical and technology data.Although GDSII is a well-established format, there is no standard for the annotatedversion. It may be necessary to select the most popular version from among severaldifferent versions.One issue is cross-reference with technology data, as end users are unlikely to getdoping information from the foundry. Nevertheless, commercial solutions exist forextracting substrate parameters from doping profiles. Each profile is represented inthe substrate parameter file with a dedicated data subset and a specific identifier.

Cross-referencing technology data with AGF therefore attaches each region shapewith a profile identifier from the substrate parameter file.

2.4.3.2 Substrate Access Ports

This dataset provides geometrical shapes, a doping profile identifier, and a net namefor each access port.Geometry is used to localize the access port. It is described in a 3-D coordinatesystem. This is necessary when a VC abstraction includes a significant vertical portionof silicon. When this is the case, lateral sidewall noise transfer needs to be taken intoaccount.Sidewall access ports are necessary if the VC author needs to hide how technology

has been used, such as to implement proprietary substrate protection techniques.When process information must be hidden, a significant vertical portion of silicon isembedded inside the VC description. Moreover, doping profile information attached tosubstrate access ports starts several microns below the interface between oxide andsilicon. Therefore, significant current flows through the VC sidewalls, and specificaccess ports are required to capture this effect, as illustrated in Figure 6.


35/65



28

Figure 6: Using Sidewall Substrate Access Ports to Connect to VC Noise Model

Doping profile information identifies the substrate depth at which the VC is connectedto the system substrate. This also provides information about vertical dopingvariations, starting from the bottom access port. This is necessary to account forstrong resistivity gradients, for instance with surface and buried implants. Doping dataalso provides a clear description of PN junctions.Net name information makes the connection between geometrical and electrical datapossible. It is not necessary to have a net name associated with all access ports.Some access ports might only be provided to account for lateral doping variations,such as shown by access port SAP6 in Figure 5.MANDATORYSpecification: Document.Comments : See Section 2.3.2.1.

2.5 SI Requirements Document The SI Requirements document contains three sections that are equivalent tosections 2.1, 2.2, and 2.3 in this specification. These sections of the SI Requirementsdocument should contain suggested alternatives to the deliverables described insections 2.1, 2.2, and 2.3 of the SI specification. Every section and sub-section shouldexist, and if no documentation or data is available, the appropriate indication of None should be specified.MANDATORYSpecification: Document.

SAP1

SAP2 SAP3

SAP4

SAP1 SAP2 SAP3 SAP4

VDD VSSVN

Bulk substrate modeled at system -level by integrator

VC electrical model provided by author

Bottom access port

Sidewall access port


36/65



29

3. Design Guidelines

3.1 Interconnect Crosstalk (Voltage Noise and Delay Variance)

Interconnect crosstalk can be defined as any deviation from the ideal signal waveform propagating inan interconnect wire caused by signal transitions in other wires in the neighborhood. This influence iscurrently primarily due to the capacitive coupling between the victim net and one or more aggressornets, although inductive coupling is also beginning to show up as a problem in cutting edge customdesigns. Since ASIC and SoC designs tend to lag cutting edge custom designs by a generation or two,inductive noise is not yet a major problem for these designs. Therefore, this document focuses solely oncapacitive crosstalk, since it is felt that the detailed analysis of inductive noise in the context of SoCdesigns over the next few years will be important only for power grid and clock design, with inductivenoise in signals being adequately controllable by a fine-grained template power grid.

Capacitive crosstalk is manifested either as a degradation of interconnect delays resulting in a loweredoperating frequency for the chip, or in outright failure of the chip. When two neighboring signalstransition simultaneously, they can affect each others slew rate (and consequently, transition delay)depending upon their transition directions, relative driver strengths and wire parasitics. Thus, twosignals transitioning in the same direction will tend to speed each other up, whereas two signalstransitioning in opposite directions will slow each other down. Delay degradation on critical nets canlower the operating frequency of the chip appreciably. This is in contrast to the failure effect of crosstalkthat causes the chip to fail even at lowered frequencies. The failure effect is caused by the voltagepulse induced on a quiescent victim net due to one or more aggressor nets switching in itsneighborhood. This pulse can cause failure due to spurious transitions in non-restoring logic such asdomino circuits. Failure can also occur due to hold time violations in sequential elements caused bysignals being sped up due to crosstalk, or these accelerated signals racing through open latches orasynchronous interfaces. The delay degradation and failure impacts of crosstalk are depicted in Figure3.1.1.

Figure 3.1.1: Crosstalk due to a switching aggressor net on a neighboring (quiescent orswitching) victim net. (The signal transition in the aggressor is shown in red and labeled A, whereasthe (non-distorted) signal in the victim is shown in blue and labeled V.)

Noise pulse Coupling Delay

VV

V A A

A


37/65



30

The problem of interconnect crosstalk is getting worse with each process generation, mainly due to thenon-ideal scaling of wires. Since wires grow relatively narrower and taller with each generation (in orderto keep their resistance manageable), the ratio of the coupling capacitance of a wire to its totalcapacitance is increasing with each generation. Although the move from aluminum to copper can haltthis deterioration for a generation, successive generations will again have to tackle the same issues.Therefore, it is becoming increasingly important to account for coupling during timing and noiseanalyses. Besides forcing the timing analysis to deal with considerably more data (on neighboring nets),the unpredictability of the transition state of neighboring nets also has the secondary undesirable effectof widening the transition windows of the signals. Furthermore, the larger error margins required insuccessive generations because of larger fractions of the total capacitance being (unpredictable)coupling capacitance also makes the convergence of high performance designs more and more difficult.Unlike digital designers, analog designers have already been worrying about interconnect crosstalk foryears. The signal waveform distortion caused by crosstalk can often cause analog circuits to fail. Thisproblem is especially acute in symmetric analog circuits such as sense amplifiers and current mirrors.On the process technology front, the number of layers does not have much of an impact on thecapacitive aspects of crosstalk noise (because of the relative shielding provided to a layer by adjacentlayers). However, with increasing layer count, the analysis of current return paths and inductive noisebecomes more complicated.

Difficult as the crosstalk problem is for traditional ASIC and custom designs, it becomes even morecritical for SoC designs because of data hiding issues arising from VC protection concerns. As a result,much of the detailed data for signals within a VC desired by the chip integrator to analyze and optimizeOTH (over-the-hierarchy) global signals cannot be made available by the VC author, resulting inconservative design frequencies and increased challenges during design convergence. Indeed, thevisibility required into the VC by the integrator in order to create a noise-safe design would at timesinvolve a fine tradeoff with VC protection issues. However, fortunately, it is often possible to reveal theelectrical/physical/timing information for a wire and its driver and receiver(s) without divulging anylogical information about them. The goal here is to present a simplified yet reasonably accurate modelfor the VC while still preserving its gray/black box nature.

Another issue worth keeping in mind is that even approximate signal integrity analysis involves dealing with hugeamounts of data; therefore, it is important to strike a balance and specify parasitic and other data only for nets thatare truly at risk for noise-problems. Furthermore, it is desirable to communicate this data in the least amount of detail that can be effective; thus, for instance, the geometric view of a potential victim net in a VC should becommunicated through flylines corresponding to its major trunks, rather than through a complete list of polygonsthat constitute the routing of the net. At the same time, the VC author should identify and communicate any datawithin the VC that can be exploited by the chip integrator to make the global convergence easier.

The basic approaches to handling crosstalk noise are either by controlling the signal slew (bydriver/receiver sizing or repeater insertion), or by reducing the ratio of bad coupling capacitance of a netto its total capacitance (by wire engineering). The first approach is usually used for timing optimizationof the circuit, with its noise optimization being a secondary objective function, whereas the secondapproach is used specifically for noise optimization when the sizing and repeater insertion is insufficientby itself to overcome noise effects. Wire engineering can include techniques like the insertion ofadditional Vdd and/or Vss wires for use as shields, permutation of the order of the signals in a routingregion to exploit logically or temporally exclusive signals as relative shields, wire spacing, and, to asmaller effect, wire tapering. Since exact analysis and optimization of each wire is often too expensiveto be practical (and is often not possible across the boundary of the VC due to lack ofvisibility/information about neighboring wires), coarse level techniques like reserving an entire layer asa shielding layer around the VC, or identifying specific no-fly zones above the VC can be used.Furthermore, feedthroughs (due to OTH wiring) in layers that are also used by the VC may be restrictedto tracks that have been explicitly reserved for them and certified by the VC author as being safe (ratherthan being routed opportunistically wherever tracks are available). In general, since coupling is only


38/65



31

going to get worse with shrinking geometries, it is more important to have a correct-by-constructiondesign style that focuses on reducing coupling rather than relying on measuring it accurately and thenfixing problems as they occur. As mentioned earlier, capacitive crosstalk can be handled at each stagefrom pre-layout sizing to global routing to detailed routing. Generally, crosstalk problems are difficult toidentify but easy to fix early on. In contrast, they become much easier to identify as one moves down thephysical design flow; however, there is correspondingly less flexibility available to fix them at these laterstages.

3.2 Inductance EffectsIn addition to parasitic capacitance, interconnect inductance can impact signal integrity in high

performance custom designs. Although detailed analysis of inductive noise in the context of SoCdesigns over the next few years will be important only for power grid and clock design, fast inductanceanalysis of all signals can serve the same purpose as fast noise analysis (using filters).

Parasitic interconnect inductance tends to speedup signals, leading to faster slew rates, andalso introduces undershoots/overshoots which deteriorate monotonicity and integrity of the signals asshown below. Inductive crosstalk is a secondary effect, and usually affects signal integrity to a lesserdegree than capacitive crosstalk.

If the victim is silent, inductive crosstalk will add-on in magnitude to the capacitive crosstalk,while intially delaying the signal. This inductive behavior is depicted below. When both victim andagreesor signals are active, the inductive crosstalk will be either positively or negatively correlated withthe caapcitive crosstalk, depending on the relative switching directions of the two signals.

The inductance impact gets worse with the use of wider and longer metal interconnects,re

Vsia Signal Integrity

Documents

Transcript of Vsia Signal Integrity