Volume 6 – Issue 2 May 2020

Editor-in-Chief: Anirban Sengupta

IEEE VLSI Circuits and Systems Letter

Volume 6, Issue 2, May 2020

Editorial

Features

Shasanka Sekhar Rout and Rajesh Kumar Patjoshi, A Low Phase Noise Active-Q Enhanced

Voltage Controlled Oscillator

Dipanjan Roy, Design Process of Zero Area and Minimal Delay Overhead based IP

Watermarking during Scheduling for High-level Synthesis Tools

Updates

Funding and Job Opportunities

Industry Job and Funding Opportunities

Upcoming Conference and Workshop

Post Conference Report

CFP Special Issue TCAD on “Hardware Oriented Security and Trust: Threats, Countermeasures

and Design Tools”

IET Book– “IP Core Protection and Hardware-Assisted Security for Consumer Electronics”

IET Book– “Frontiers in Securing IP Cores: Forensic detective control and obfuscation

techniques”

IEEE TCVLSI Flyer

Call for Contributions for IEEE VCAL

https://tc.computer.org/tcvlsi/

From the Editor-in-Chief’s Desk - Editorial

The IEEE VLSI Circuits and Systems Letter (VCAL) is affiliated with the Technical Committee on VLSI (TCVLSI)

under the IEEE Computer Society. It aims to report recent advances in VLSI technology, education and opportunities

and, consequently, grow the research and education activities in the area. The letter, published quarterly (from 2018),

covers the design methodologies for advanced VLSI circuit and systems, including digital circuits and systems, hardware

security, design for protection, analog and radio-frequency circuits, as well as mixed-signal circuits and systems. The

emphasis of TCVLSI falls on integrating the design, secured computer-aided design, fabrication, application, and business

aspects of VLSI while encompassing both hardware and software.

IEEE TCVLSI sponsors a number of premium conferences and workshops, including, but not limited to, ASAP, ASYNC,

ISVLSI, IWLS, SLIP, and ARITH. Emerging research topics and state-of-the-art advances on VLSI circuits and systems

are reported at these events on a regular basis. Best paper awards are selected at these conferences to promote the high

quality research work each year. In addition to these research activities, TCVLSI also supports a variety of educational

activities related to TCVLSI. Several student travel grants are sponsored by TCVLSI in the following meetings: ASAP,

ISVLSI, IWLS, iSES (formerly iNIS) and SLIP. Funds are provided to compensate student travels to these meetings as

well as attract more student participation. The organizing committees of these meetings undertake the task of selecting

right candidates for these awards.

The current issue of VCAL showcases the state-of-the-art developments covering several important articles: ‘A Low

Phase Noise Active-Q Enhanced Voltage Controlled Oscillator’ and ‘Design Process of Zero Area and Minimal Delay

Overhead based IP Watermarking during Scheduling for High-level Synthesis Tools’. The peer-reviewed articles can be

found in the section of “Features Articles”. In the section of “Updates”, upcoming conferences/workshops, call for papers

and proposals, funding opportunities, job openings, conference report and Ph.D. fellowships are summarized.

I would also like to thank all editorial board members (Yiyu Shi, Jun Tao, Himanshu Thapliyal, Michael Hübner, Nicolas

Sklavos, Sergio Saponara, Shiyan Hu, Hideharu Amano, Mike Borowczak, Helen Li, Saket Srivastava, Yasuhiro

Takahashi, James Stine and Qi Zhu) for their dedicated effort and strong support in organizing this letter. The complete

editorial board information is available at: https://tc.computer.org/tcvlsi/vcal-editorial-board/.

We are thankful to our web chair James Stine and IEEE CS staffs, for their professional services to make the letter

publicly available. We wish to thank all authors who have contributed their professional articles to this issue. We hope

that you will have an enjoyable moment when reading the letter! The call for contributions for the next issue is available

at the end of this issue and we encourage you to submit articles, news, etc. to an associate editor covering that scope.

Anirban Sengupta, Ph.D., FIET, FBCS (UK), SMIEEE, P.Eng

IEEE Distinguished Visitor | IEEE Distinguished Lecturer

Chair, IEEE Computer Society TCVLSI

Editor-in-Chief of IEEE VCAL, TCVLSI

Associate Professor, Computer Science and Engineering

Indian Institute of Technology Indore

Web: http:// http://www.anirban-sengupta.com

IEEE CS-TCVLSI: https://www.computer.org/communities/technical-committees/tcvlsi

ieee-tcvlsi.org

Features

A Low Phase Noise Active-Q Enhanced Voltage Controlled Oscillator

Shasanka Sekhar Rout1*

and Rajesh Kumar Patjoshi2

1Department of Electronics and Communication Engineering, Gandhi Institute of Engineering and Technology University,

Gunupur, India 2Department of Electronics and Communication Engineering, National Institute of Science and Technology, Berhampur,

India

Abstract –This letter presents a low phase noise voltage controlled oscillator (VCO) design by using United

Microelectronics Corporation (UMC) 180 nm Complementary Metal Oxide Semiconductor (CMOS) Technology. Here,

one pair of pMOS cross-coupled transistors and one pair of nMOS cross-coupled transistors are connected parallely with

the original cross-coupled pairs, so that the effective transconductance (gm) is enhanced. As a result, higher value of

transconductance increases the quality factor (Q) and hence, lowers the phase noise. The proposed active-Q enhanced

VCO operates in 1.12 V supply voltage and consumes a dc power of 6.08 mW. It offers the tuning range of 1.85 to 1.89

GHz with control voltage variation from 0 to 1.8 V. This VCO circuit provides a lower phase noise of -115 dBc/Hz at

carrier offset of 1 MHz and -31 dBc/Hz at carrier offset of 1 KHz. So, this work can be a convenient building block for an

improvised mixer design in a standard receiver.

1. Introduction There is a demand of low cost, compact size and long battery life solution wireless system. The scaling of CMOS

technology impacts on radio frequency integrated circuits (RFICs) to improve the power consumption, operation speed

and area of the IC. The RF front end design is a surge of low noise amplifier (LNA), mixer, VCO and power amplifier

(PA) in a receiver design [1]. The blocks in the RF front end process the RF signal, before it is translated to a lower

intermediate frequency (IF). The linearity of receiver is dominated by the last stage, normally mixers and power

amplifiers, in which the local oscillator (LO) signal comes from VCO [2]. The VCO block is basic to all the synchronous

systems, which provides the reference signal. Also, VCOs are commonly a crucial part of PLLs [3] and frequency

synthesizers. The performance of an oscillator can be considered by several parameters, like the oscillation frequency

range, sensitivity, phase noise and power dissipation. It can be noted that the phase noise is the most disturbing parameter,

which alters the output a lot [4, 5].

2. Related Work In case of VCO to get required oscillation output, the contribution of phase noise must be reduced. Earlier research

associated to VCO design, various different topologies are implemented to diminish the flicker (1/f) noise involvement

towards the phase noise [4, 6]. In CMOS oscillators, since the flicker noise gets up transformed to the close-in phase noise

near to the carrier frequency, the performance of phase noise at lower offsets from the carrier frequency is conquered by

the flicker noise [5].The source degeneration resistors and drain resistors [7, 8] are used to limit the transconductance and

also disinfect the tank from smaller channel resistance. As these resistors are in series with the channel resistances, which

ultimately suppress the excess 1/f noise current. But these methods show poor 1/f2

performance due to thermal noise of

resistors and these drain resistances with parasitic capacitances at drain side create phase delay [9]. Two active resistors

(pMOS transistors), which are connected in between cross-coupled pairs exhibit small resistance when cross-coupled pairs

reside in saturation region and high resistance when cross-coupled pairs reside in linear region [10]. This change in

resistance in two different regions prevents small conducting resistances of cross-coupled pair in linear region to degrade

Q-factor. As a result, the performance of power consumption is poor due to the extra metal-oxide semiconductor field-

effect transistors (MOSFETS). For reduction of power consumption, normal MOSFETs are replaced by dynamic

threshold MOSFETs (DTMOSs) [11], which work on dynamic threshold voltage method [12]. Also, the performance of

phase noise depends proportionally on output swing’s amplitude [5], which can be controlled by changing threshold

voltage. The reducing of threshold voltage enhances the variation of output voltage primary to lower phase noise further.

In [13], the conventional DTMOS VCO is described without the concept of active resistors which does not consider the

linear region operation of cross-coupled pairs. In [14], there is a good oscillation frequency and moderate phase noise

performance by using the current mirror VCO with poor power consumption.

1

VLSI Circuits and Systems Letter Volume 6 – Issue 2 May 2020

2.1. Contribution of Proposed Work

In this letter, the low phase noise is focused with a moderate frequency value. Here, the effective transconductance

enhanced concept is used to reduce the phase noise by the incremental value of the quality factor due to increase in gm

value by the extra cross-coupled transistors.

3. Proposed VCO Design and Analysis The transconductance (gm) is one of the important contributing parameter for phase noise calculation. It indicates to

the negative conductance obtained by active core of VCO, where the inductor parasitic resistance is cancelled out. So it is

responsible for improving quality-factor (Q) of resonator [2]. Since higher Q value suggests lower phase noise, higher the

gm results higher the Q-factor and hence lower phase noise.

Here, one pair of pMOS cross-coupled transistors and one pair of nMOS cross-coupled transistors are linked

parallely with the original cross-coupled pairs, so that the effective transconductance will be enhanced.

Figure 1 shows Q-enhancement circuit using (a) only pMOS cross-coupled pair and (b) only nMOS cross-coupled

pairs respectively.

MPMP

VDD

MNMN

(a) (b)

Figure 1: Q-enhancement circuit employing (a) pMOS cross-coupled and (b) nMOS cross-coupled transistors

These circuits offer a transconductance of –gm/2 (gmp/2 (a), gmn/2 (b)) like the original cross-coupled pair. So if these

circuits will be connected to the traditional VCO circuit, then the overall (effective) transconductance will be increased as

these circuits will remain in parallel with the CMOS pairs (transconductances will be added).

Figure 2 represents the proposed VCO configuration consisting of two extra MOSFETs pairs (MP3&MP4 and

MN3&MN4), which are associated parallely to the original cross-coupled pairs (MP1&MP2 and MN1&MN2). Their gates are

also tied to the drain of the opposite cross-coupled transistor. The varactors CVAR1 and CVAR2 with the tank circuit

consisting of LTANK, CTANK and RTANK are used to increase the tuning range of VCO, where the varactors are controlled by

the control voltage Vcntr. Two pairs of C-R are used for better biasing of varactors with a biasing voltage Vb.

R Vb R

C C

VDD

MP1 MP2

MP3MP

4

MN3MN4

MN1 MN2

VDD

VcntrCVAR1 CVAR2

VOUT-VOUT+

RTANK

LTANKCTANK

Figure 2: Active Q-enhancement proposed VCO circuit

2

VLSI Circuits and Systems Letter Volume 6 – Issue 2 May 2020

Figure 3 presents the half-circuit small signal analysis of Figure 2 to find the relationship in between gm, Q and phase

noise. The negative conductance can reduce the total output conductance, therefore enlargement of the output swing and

enhancement of the quality factor, results in improvement of the phase noise performance of the VCO.

The voltage gain of the circuit is shown in equation (1).

GGA

T

meffv

1 (1)

where, Gmeff is the effective transconductance of the amplifier, GT is the total conductance at the drain of MN1 and

MN3, which is represented as GA and the equivalent parallel conductance of the inductor GL (has dominant effect in total

conductance).

gm3vgs gm1vgs

vgs

VOUT+

2C

TA

NK

CV

AR

RT

AN

K/2

LT

AN

K/2

Figure 3: Half-circuit small signal analysis of Figure 2

So, GT is given by as follows:

GGG ALT (2)

And GL is given by,

22 1

1

wL

R

QRG

S

s

L

(3)

where, RS and Q are the series equivalent resistance and the quality-factor of the inductor respectively and L=LTANK/2.

The loaded Q of the proposed circuit can be written as follows:

L

C

GQ

T

T

L

1 (4)

where is CT the total capacitance at the drain of MN1 and MN3. From Figure 3, the generated negative conductance can

be written as:

gggG mmmA 2

31 (5)

Finally, the equation (2) is changed to equation (6).

g

wL

RGGG m

SALT 2

2 (6)

From equations (1), (4) and (6), as GT is reduced, Av and Q are increased. So, the phase noise is enhanced proportionally

with the gain and Q.

4. Results and Comparison The proposed design is implemented with 180 nm CMOS technology in Cadence tool. The transient, pnoise and

periodic steady state (PSS) analysis are made to find out the power dissipation, oscillation frequency, phase noise, tuning

range etc. The parameters of the tank circuit are chosen to get 2.4 GHz frequency. Figure 4(a) presents the tuning range

with control voltage variation from 0 to 1.8 V. The frequency tuning range is obtained from 1.85 to 1.89 GHz (about 40

MHz) which can be increased by increasing the branches in tank circuit. Figure 4(b) shows frequency variation with the

change in power supply as called frequency pushing, which shows the efficiency of the design. The output power level

and power dissipation plots are displayed in Figure 5(a) and 5(b) respectively. This proposed VCO consumes 6.08 mW

from the supply voltage of 1.12 V.

3

VLSI Circuits and Systems Letter Volume 6 – Issue 2 May 2020

(a) (b)

Figure 4: (a) Tuning range and (b) Frequency pushing of the proposed VCO

(a) (b)

Figure 5: (a) Output power-level and (b) Power dissipation of the proposed VCO

The phase noise with relative frequency plot is drawn in Figure 6, which results phase noise of -115 dBc/Hz at 1

MHz offset frequency and -31 dBc/Hz at 1 KHz offset frequency. The phase noise plot represents exact value of -47

dBc/Hz at 4.56 KHz offset frequency. Here, the phase noise is reduced as compared to the previous reported results. The

layout of the proposed design is exposed in Figure 7, where it results the silicon area of 0.86 x 0.82 mm2.

Figure 6: Phase noise of graph of proposed VCO design

4

VLSI Circuits and Systems Letter Volume 6 – Issue 2 May 2020

Figure 7: Layout diagram of proposed VCO design

The result of proposed work is compared with the performance of VCOs available in literature, which is displayed in

TABLE 1. It is found that the proposed design results a phase noise of -115 dBc/Hz as superior to the comparison of [8,

10, 14]. It is due to the Q-enhancement by the incremental value of gm of the extra cross coupled transistor with core

transistor. Thus, the proposed VCO using Q-enhancement achieves better phase noise. The proposed design also operates

in low voltage and low power dissipation as compared to [14] with a good frequency range of oscillation.

TABLE 1

PERFORMANCE VALUATION OF VARIOUS VCOS Refs. CMOS Process

Frequency

(GHz)

Power

Supply

(v)

Power

Dissipation

(mW)

Phase noise in

dBc/Hz

(1 K offset)

Phase noise in

dBc/Hz

(1 M offset)

[8] 65 nm 3.3 1.2 0.72 -47 -110

[10] 65 nm 5.71 0.6 0.42 -43.3 -113.4

[14] 0.18 µm 2.23 1.2 6.71 -30 -112

This

work 0.18 µm 1.89 1.12 6.08 -31 -115

5. Conclusion The proposed work using active Q-enhanced concept is designed and implemented in 180 nm CMOS technology.

The proposed VCO design achieves a lower phase noise as compared to the previous reported results. It also has a good

frequency range of oscillation and low power consumption for certain application point of view. Hence, the proposed

work can be an operational block for the mixer design. The proposed design can be integrated with the LNA and mixer for

the superior receiver front end design.

Reference [1] B. Leung, VLSI for Wireless Communication, Pearson Education, Singapur, 2004.

[2] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University press, United

Kingdom, 2004.

[3] J. Korte and M. Hübner, “Reactive current compensation method for PFC applications based on SOGI-PLL,” VLSI

Circuits and Systems Letter, vol. 5, no. 2, pp. 1-10, 2019.

[4] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp.

331-343, 1996.

[5] A. Hajimiri and T. H. Lee, “Phase noise in CMOS differential LC oscillators,” In Symposium on VLSI Circuit, pp.

48-51, 1998.

5

VLSI Circuits and Systems Letter Volume 6 – Issue 2 May 2020

[6] E. Hegazi, H. Sjoland and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE Journal of

Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, 2001.

[7] S.-J. Yun, C.-Y. Cha, H.-C. Choi and S.-G. Lee, “RF CMOS LC-oscillator with source damping resistors,” IEEE

Microwave and Wireless Component Letters, vol. 16, no. 9, pp. 511–513, 2006.

[8] S. Levantino, M. Zanuso, C. Samori and A. Lacaita, “Suppression of flicker noise upconversion in a 65 nm CMOS

VCO in the 3.0-to-3.6 GHz band,” In IEEE International Solid-State Circuits Conference, pp. 50-51, 2010.

[9] F. Pepe, A. Bonfanti, S. Levantino, C. Samori and A. L. Lacaita, “Suppression of flicker noise up-conversion in a 65

nm CMOS VCO in the 3.0-to-3.6 GHz band,” IEEE Journal Solid-State Circuits, vol. 48, no. 10, pp. 2375–2389,

2013.

[10] J. Sun, C. C. Boon, X. Zhu, X. Yi, K. Devrishi and F. Meng, “A low-power low-phase-noise VCO with self-adjusted

active resistor,” IEEE Microwave and Wireless Component Letters, vol. 26, no. 3, pp. 201-203, 2016.

[11] S.-L. Jang and C.-F Lee, “A low voltage and power LC VCO implemented with dynamic threshold voltage

MOSFETS,” IEEE Microwave and Wireless Component Letters, vol.17, no. 5, pp. 376-378, 2007.

[12] S. S. Rout, S. Acharya and K. Sethi, “A low phase noise gm-boosted DTMOS VCO design in 180 nm CMOS

technology,” Karbala International Journal of Modern Science, vol. 4, no. 2, pp. 228-236, 2018.

[13] S. L. Jang, C. J. Huang, C. W. Hsue and C. W. Chang, “A 0.3 V cross-coupled VCO using dynamic threshold

MOSFET,” IEEE Microwave and Wireless Component Letters, vol. 20, no. 3, pp. 166-168, 2010.

[14] S. S. Rout, S. Acharya and K. Sethi, “Design of a good oscillation frequency and moderate phase noise current mirror

VCO,” Third International Conference on Computing and Network Communications (CoCoNet’19), 2019. (In Press)

About the Authors Dr. Shasanka Sekhar Rout (ssrout1988@gmail.com) completed his Ph.D. at VSS University of Technology

(VSSUT), Burla, India in 2019. He received his M.Tech degree in VLSI signal processing from VSSUT, Burla, India

in 2014. He is currently working as Assistant Professor in GIET University, Gunupur, India. He has more than 20

publications in his research domain. His research area focuses on VLSI signal processing, analog and RF CMOS

circuit design, digital VLSI design and low power design.

Dr. Rajesh Kumar Patjoshi (rajeshpatjoshi1@gmail.com) completed his Ph.D. at National Institute of Technology

(NIT), Rourkela, India in 2015. He received his M.Tech degree in VLSI and embedded systems from NIT, Rourkela,

India in 2010. He is currently working as Associate Professor in NIST, Berhampur, India. He has more than 25

publications in his research domain. His research interest includes power quality enhancement, analog and mixed

signal VLSI design and grid integrated of renewable energy network control.

ieee-tcvlsi.org

Features

Design Process of Zero Area and Minimal Delay Overhead based IP

Watermarking during Scheduling for High-level Synthesis Tools Dipanjan Roy

Center of Excellence in Cyber Security, Institute for Development and Research in Banking Technology, Hyderabad,

India

Abstract – This letter presents the designing and embedding process of a low-cost intellectual property (IP) core

watermarking methodology during the scheduling phase of high-level synthesis (HLS). The target hardware of this

approach is digital signal processor (DSP) IP cores and it protects the IP core vendors from unauthorized ownership and

IP piracy. The watermarking constraints are consist of two encoded variables, where each variable conveys a hidden

meaning. The encoding rules are designed in such a way that the embedded watermark incurs zero area and minimal delay

overhead. Comparative analysis of embedding cost shows significant savings than other similar approaches.

1. Introduction

The design supply chain of the modern system-on-chip industry is not only distributed throughout the world but also,

the design process is segregated in multiple abstraction levels. Each vendor of each abstraction level present in this chain

is heavily reliant on automated CAD tools. This invites several IP infringements, mainly ownership and piracy threats in

these CAD tools. Embedding vendor’s watermark in the form of additional design constraints can protect a reusable IP

core from these threats. However, during embedding additional constrains as IP watermarks, the overall design overhead

after embedding the watermark should be as low as possible. There are few techniques, such as [1-3], which protects the

IP core at the higher abstraction level. Authors in [1] propose watermarking during the register allocation phase of HLS,

and [2] proposed a more robust vendor watermarking using multi-variable encoding. In [3], the watermarks are embedded

during the scheduling phase of HLS, which induces zero area and negligible execution time overhead, thus resulting into

trivial embedding cost. However, non-watermarked such as computational forensic engineering (CFE) inspired IP core

protection mechanism is also available in the literature [4]. This letter discusses the designing process of [3].

2. Designing of Watermarked IP Core

As mentioned earlier, [3] embeds low-cost, multi-variable encoding watermark covertly during the scheduling phase

in HLS. This is achieved by employing some local scheduling rules as additional constraints. More explicitly, instead of

employing priority resolver functions or random break during operation scheduling conflict, a watermark encoding based

scheduling rule is employed to select which operation to assign in which control step (CS). In other words, watermarking

constraints are embedded in the scheduling phase by an IP vendor by forcing specific operations to specific control steps

while resolving the scheduling conflict.

Figure: 1. (a) Original Data Flow Graph of MESA Horner Figure: 1. (b) Watermark embedded scheduling with 2 adders and 3 multipliers

1

VLSI Circuits and Systems Letter Volume 6 – Issue 2 May 2020

A. Watermark Algorithm

The vendor watermark consists of two unique encoding variables (‘X’, ‘Y’) which is defined as follows:

X = Force even operation in odd control step while resolving scheduling conflict in scheduling phase.

Y = Force odd operation in even control step while resolving scheduling conflict in scheduling phase.

In the watermark embedding process, the module library, application and user-provided resource constraints are

accepted as input. Further, the IP vendor provides his/her desired signature as any arrangement of ‘X’ and ‘Y’ digits. The

signature is then transformed into its corresponding watermarking constraints using the aforementioned decoding rules.

During performing scheduling, these additional constraints are used in case of operation conflict to resolve and generate a

valid schedule.

B. Motivational Example

The MESA Honor benchmark in the form of an unscheduled DFG is used for demonstration (shown in Fig. 1(a)). A

6 digit encoded vendor’s watermark is selected as: “XXYYXY” which should be converted into decoded watermarking

constraints before embedding. The user resource constraints for scheduling the DFG are 2 adders and 3 multipliers. The

signature, with its decoded meaning, is shown in Table 1. For scheduling in the first CS (i.e. CS1), there are four ready

operations viz. opn 1, opn 2, opn 3 and opn 4, however only 3 multipliers are available. This indicates operation conflicts

scenario during scheduling in CS1. As per the signature decoding, the first digit ‘X’ assign opn 2 (i.e. even) into CS 1 (i.e.

odd) while the second digit ‘X’ assign opn 4 (i.e. even) into CS 1 (i.e. odd). Further, the third digit ‘Y’ assigns opn 3 (i.e.

odd) into CS 2 (i.e. even), thus resolves the conflict in CS 1. Moreover, this does not violate the resource constraints and

the data dependency. Similarly, all the 6 digits are embedded in the design. Fig. 1 (b) shows the watermarked MESA

Horner benchmark based on user resource constraints (2 adders, and 3 multipliers). As evident, there is absolutely ZERO

area and delay overhead.

3. Result and Analysis

This watermarking approach is designed and embedded in several benchmarks. The comparison of design cost with

[1] and [2] is shown in Fig. 2 for a 60 digit watermark. The improvement in the average cost compared to [1] and [2] is

6.14% and 5.82%, respectively.

4. Conclusion

This letter presents the designing and embedding process of an IP watermarking methodology that incurs almost zero

(or minimum) design overhead while providing strong user protection.

Reference

[1] Koushanfar, F., Hong, I., and Potkonjak, M.: ‘Behavioral synthesis techniques for intellectual property protection’, ACM Trans. Des. Autom. Electron. Syst., 2005, 10, (3), pp. 523–545.

[2] A. Sengupta, S. Bhadauria, and S. Mohanty, "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", IEEE Int'l Symposium on Circuits & Systems, 2016, pp. 974 – 977.

[3] A. Sengupta, and D. Roy, “Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools,” in Advances in Engineering Software, 2017, vol. 110, pp. 26-33.

[4] A. Sengupta, D. Kachave, “Applying digital forensic for hardware protection : resolving false claim of IP ownership,” IEEE VLSI Circuits & Systems Letter, Feb 2018,vol. 4 (1), pp. 10 – 13.

About the Author

Dipanjan Roy (droy@idrbt.ac.in) is an Assistant Professor in Center of Excellent in Cyber Security at Institute

for Development and Research in Banking Technology. His research interest includes Hardware Security and

Trust during High Level Synthesis, Protection of DSP IP Core, IP Watermarking.

TABLE 1

SIGNATURE AND ITS DECODED MEANING

Desired Watermark (6-digit)

Corresponding operation assigned in control step based on watermark

X assign operation 2 (even)in CS1(odd) X assign operation 4 (even)in CS1(odd) Y assign operation 3 (odd)in CS2 (even) Y assign operation 5 (odd) in CS2 (even) X assign operation 6 (even) in CS3 (odd) Y assign operation 7 (odd) in CS2 (even)

Cost of [3] Cost of [2] Cost of [1]

Diff eq. 0.6679 0.7066 0.7113

FIR 0.4413 0.4870 0.4870

FFT 0.5065 0.5362 0.5399

ARF 0.8305 0.8644 0.8644

MESA 0.8501 0.8814 0.8875

IIRB 0.7808 0.8399 0.8399

0.00000.10000.20000.30000.40000.50000.60000.70000.80000.90001.0000

Diff eq. FIR FFT ARF MESA IIRB

Cost of [3] Cost of [2] Cost of [1]

Figure: 2. Comparison of cost between [3], [2] and [1]

Title Program Guidelines Due Dates

Principles and Practice of Scalable Systems

(PPoSS)

20-534 Full Proposal:April 6, 2020

International Research and education

Network Connections (IRNC)

20-535 Full Proposal:April 8, 2020

Future Manufacturing (FM) 20-552 Letter of Intent:April 10, 2020

Spectrum and Wireless Innovation enabled

by Future Technologies (SWIFT) CCrosscutti ng

20-537 Full Proposal:April 10, 2020

Computer Science for All (CSforAll:

Research and RPPs) CCrosscutting

20-539 Full Proposal:April 27, 2020

NSF-Simons Research Collaborations on

the Mathematical and Scientific Foundations

of Deep Learning (MoDL)

20-540 Full Proposal:April 30, 2020

EPSCoR Research Infrastructure

Improvement Track 4: EPSCoR Research

Fellows (RII Track-4) NNSF-wide

20-543 Full Proposal:May 12, 2020

Signals in the Soil CCrosscutti ng 20-548 Full Proposal:May 20, 2020

Small Business Innovation Research

Program Phase I (SBIR) NNSF-wide

20-527 Full Proposal:June 4, 2020

Small Business Innovation Research

Program Phase II NNSF-wide

20-545 Full Proposal:June 4, 2020

Small Business Technology Transfer

Program Phase I (STTR) NNSF-wide

20-528 Full Proposal:June 4, 2020

Small Business Technology Transfer

Program Phase II NNSF-wide

20-546 Full Proposal:June 4, 2020

Future Manufacturing (FM) 20-552 Full Proposal:June 5, 2020

Multimodal Sensor Systems for Precision 20-556 Full Proposal:June 8, 2020

Title Program Guidelines Due Dates

Health Enabled by Data Harnessing,

Artificial Intelligence, and Learning (SenSE)

Navigating the New Arctic Community

Office (NNA-CO) NNSF-wide

20-549 Full Proposal:June 10, 2020

Spectrum Innovation Initiative: National

Center for Wireless Spectrum Research

(SII-Center) CCrosscutting

20-557 Full Proposal:June 12, 2020

Expeditions in Computing (Expeditions) 20-544 Preliminary Proposal:June 16, 2020

Partnerships for Innovation (PFI) NNSF-wide 19-506 Full Proposal:July 8, 2020

Inclusion Across the Nation of Communities

of Learners of Underrepresented

Discoverers in Engineering and Science

(NSF INCLUDES) NNSF-wide

19-600 Full Proposal:July 13, 2020

Historically Black Colleges and Universities

- Excellence in Research (HBCU - EiR) NNSF-wide

20-542 Letter of Intent:July 23, 2020

Faculty Early Career Development Program

(CAREER) NNSF-wide

20-525 Full Proposal:July 27, 2020

ADVANCE: Organizational Change for

Gender Equity in STEM Academic

Professions (ADVANCE) NNSF-wide

20-554 Letter of Intent:August 3, 2020

Quantum Leap Challenge Institutes

(QLCI) NNSF-wide

19-559 Letter of Intent:August 3, 2020

ADVANCE: Organizational Change for

Gender Equity in STEM Academic

Professions (ADVANCE) NNSF-wide

20-554 Full Proposal:August 7, 2020

Computer and Information Science and

Engineering (CISE) Research Initiation

Initiative (CRII)

19-579 Full Proposal:August 12, 2020

Title Program Guidelines Due Dates

NSF Innovation Corps Hubs Program (I-

CorpsTM Hubs) NNSF-wide

20-529 Full Proposal:August 13, 2020

Research Experiences for Undergraduates

(REU) NNSF-wide

19-582 Full Proposal:August 26, 2020

Quantum Leap Challenge Institutes

(QLCI) NNSF-wide

19-559 Preliminary Proposal:September 1, 2020

Small Business Innovation Research

Program Phase I (SBIR) NNSF-wide

20-527 Full Proposal:September 3, 2020

Small Business Innovation Research

Program Phase II NNSF-wide

20-545 Full Proposal:September 3, 2020

Small Business Technology Transfer

Program Phase I (STTR) NNSF-wide

20-528 Full Proposal:September 3, 2020

Small Business Technology Transfer

Program Phase II NNSF-wide

20-546 Full Proposal:September 3, 2020

Computer and Information Science and

Engineering (CISE): Core Programs

19-589 Full Proposal:September 14, 2020

Computational and Data-Enabled Science

and Engineering (CDS&E)

Full Proposal:September 15, 2020

Computational and Data-Enabled Science

and Engineering in Mathematical and

Statistical Sciences (CDS&E-MSS)

Full Proposal:September 15, 2020

NSF Dynamic Language Infrastructure -

NEH Documenting Endangered Languages

(DLI-DEL)

19-606 Full Proposal:September 15, 2020

Computer and Information Science and

Engineering (CISE): Core Programs

19-589 Full Proposal:September 23, 2020

Computational and Data-Enabled Science

and Engineering (CDS&E)

Full Proposal:September 30, 2020

Title Program Guidelines Due Dates

Historically Black Colleges and Universities

- Excellence in Research (HBCU - EiR) NNSF-wide

20-542 Full Proposal:October 6, 2020

Computational and Data-Enabled Science

and Engineering (CDS&E)

Full Proposal:October 15, 2020

Graduate Research Fellowship Program

(GRFP) NNSF-wide

19-590 Full Proposal:October 19, 2020Full

Proposal:October 20, 2020Full

Proposal:October 22, 2020Full

Proposal:October 23, 2020

Computational and Data-Enabled Science

and Engineering (CDS&E)

Full Proposal:November 2, 2020

ADVANCE: Organizational Change for

Gender Equity in STEM Academic

Professions (ADVANCE) NNSF-wide

20-554 Full Proposal:November 4, 2020

CISE Community Research Infrastructure

(CCRI)

19-512 Letter of Intent:November 11, 2020

Computer and Information Science and

Engineering (CISE): Core Programs

19-589 Full Proposal:November 12, 2020

Computational and Data-Enabled Science

and Engineering (CDS&E)

Full Proposal:November 16, 2020Full

Proposal:December 3, 2020

Small Business Innovation Research

Program Phase I (SBIR) NNSF-wide

20-527 Full Proposal:December 3, 2020

Small Business Innovation Research

Program Phase II NNSF-wide

20-545 Full Proposal:December 3, 2020

Small Business Technology Transfer

Program Phase I (STTR) NNSF-wide

20-528 Full Proposal:December 3, 2020

Small Business Technology Transfer

Program Phase II NNSF-wide

20-546 Full Proposal:December 3, 2020

Cyberlearning for Work at the Human- 17-598 Full Proposal:January 11, 2021

Title Program Guidelines Due Dates

Technology Frontier

Partnerships for Innovation (PFI) NNSF-wide 19-506 Full Proposal:January 13, 2021

CISE Community Research Infrastructure

(CCRI)

19-512 Full Proposal:January 14, 2021

Major Research Instrumentation Program:

(MRI) NNSF-wide

18-513 Full Proposal:January 19, 2021

Training-based Workforce Development for

Advanced Cyberinfrastructure

(CyberTraining) CCrosscutting

19-524 Full Proposal:January 20, 2021

Principles and Practice of Scalable Systems

(PPoSS)

20-534 Full Proposal:January 25, 2021

Quantum Leap Challenge Institutes

(QLCI) NNSF-wide

19-559 Full Proposal:February 1, 2021

Spectrum Innovation Initiative: National

Center for Wireless Spectrum Research

(SII-Center) CCrosscutting

20-557 Letter of Intent:February 1, 2021

Computer Science for All (CSforAll:

Research and RPPs) CCrosscutting

20-539 Full Proposal:February 10, 2021

Expeditions in Computing (Expeditions) 20-544 Full Proposal:February 16, 2021

Ethical and Responsible Research (ER2) 19-609 Full Proposal:February 22, 2021

Cyberinfrastructure Centers of Excellence

(CI CoE)

Full Proposal:Accepted Anytime

Cyberinfrastructure for Emerging Science

and Engineering Research (CESER)

Full Proposal:Accepted Anytime

Established Program to Stimulate

Competitive Research: Workshop

19-588 Full Proposal:Accepted Anytime

Title Program Guidelines Due Dates

Opportunities (EPS-WO) (EPS-WO) NNSF-wide

Facilitating Research at Primarily

Undergraduate Institutions: NNSF-wi de

14-579 Full Proposal:Accepted Anytime

Foundational Research in Robotics

(Robotics) CCrosscutti ng

Full Proposal:Accepted Anytime

Innovation Corps - National Innovation

Network Teams Program (I-CorpsTM

Teams) NNSF-wide

18-515 Full Proposal:Accepted Anytime

NSF/FDA SCHOLAR-IN-RESIDENCE AT

FDA

18-556 Full Proposal:Accepted Anytime

Research Coordination Networks CCrosscutti ng 17-594 Full Proposal:Accepted Anytime

Secure and Trustworthy Cyberspace

(SaTC)

19-603 Full Proposal:Accepted Anytime

Announcements for Academic, Postdoctoral and PhD Positions AcademicKeys

http://www.academickeys.com/

HigherEdJobs

https://www.higheredjobs.com/

IEEE Job Site

http://jobs.ieee.org/

IEEE Computer Society | Jobs

https://www.computer.org/web/jobs

Computing Job Announcements – CRA

https://cra.org/ads/

PolytechnicPositions www.polytechnicpositions.com/

Funding Opportunities

Title

Organization yProgram Guidelines yDue Dates

Research Funding

Towards On-Device AI Facebook Weblink Monday, February 3, 2020 at

11:59 pm PST

Qualcomm Innovation Fellowship

(India)

Qualcomm Weblink February 28, 2020

Qualcomm Innovation Fellowship

(Europe)

Qualcomm Weblink February 14, 2020

ISPD2020: Wafer-Scale Deep

Learning Accelerator Placement

Cerebras Systems Weblink March 20, 2020

PhD/Post-Doc and Residency Programs

Artificial Intelligence (AI) Residency

Program

Facebook Weblink Friday, January 31, 2020 at 5:00

p.m. PST

IBM PhD Fellowship IBM Weblink September to November

The Link Foundation PhD fellowship Link foundation Weblink January 15, 2020 (11:59 pm EST)

MSFT AI Residency Program Microsoft Weblink January 31, 2020

MSR Research Fellowship (India) Microsoft Weblink February 21, 2020

Google India PhD Fellowship

program

Google Weblink January to April 2020

ACM SIGHPC/Intel Computational &

Data Science Fellowships

ACM / Intel Weblink March to April 2020

Funding Opportunities

Title

Organization yProgram Guidelines yDue Dates

Western Digital Scholarship Program

**

Qualcomm Weblink April 3, 2020

Internship Opportunities

Title

Organization Location yProgram Guidelines

Hardware Engineering Intern,

Summer 2020

Google Inc.

USA Weblink

Research Intern, 2020 Google Inc. USA Weblink

Software Engineering Intern, PhD,

Summer 2020

Google Inc. USA Weblink

Physical Design and Timing Intern NVIDIA Inc. USA Weblink

Computer Architecture Intern (CPU) NVIDIA Inc. USA Weblink

Power Analysis Intern - Hardware NVIDIA Inc. China Weblink

Deep Learning Security Software

Engineer Intern

NVIDIA Inc. USA Weblink

Digital/Mixed Signal Design

Engineering Intern

Texas Instruments USA Weblink

Digital Design Engineering Intern -

MS/PhD

Texas Instruments USA Weblink

Internship Opportunities

Title

Organization Location yProgram Guidelines

Analog Design Engineering Intern -

MS/PHD

Texas Instruments USA Weblink

AI/ML Research Co-Op/Intern AMD USA Weblink

R&D Intern KLA Tencor Singapore Weblink

Electrical Engineering Intern KLA Tencor USA Weblink

Algorithm Intern KLA Tencor India Weblink

Research Intern - Security of

Machine Learning Systems

Microsoft USA Weblink

Research Intern - Image

Understanding

Microsoft Canada Weblink

Research Intern - Privacy-Preserving

Machine Learning

Microsoft USA Weblink

Garage Intern – Software Engineer Microsoft USA Weblink

High School Internship Microsoft USA Weblink

Security Research Software Engineer

Summer internship- PHD

Microsoft Israel Weblink

Data & Applied Scientist Summer

Internship

Microsoft Israel Weblink

RAMP Engineering Intern Program –

PhD, MS, BS

Western Digital USA Weblink

Internship Opportunities

Title

Organization Location yProgram Guidelines

Engineering Intern Western Digital Malaysia Weblink

Full-time Opportunities

Title

Organization Location yProgram Guidelines

Audio Hardware Systems Engineer Google Inc. USA Weblink

Hardware Reliability Engineer,

Devices and Services

Google Inc. USA Weblink

Software Engineer Google Inc. USA Weblink

Deep Learning Library Performance

Software Engineer - New College

Grad

NVIDIA Inc. USA Weblink

Deep Learning Library Software

Engineer, AI - New College Grad

NVIDIA Inc. USA Weblink

Software Engineer - Computer Vision

and Deep Learning - New College

Grad

NVIDIA Inc. USA Weblink

Systems Software Engineer -

Robotics (New College Grad)

NVIDIA Inc. USA Weblink

Analog, Digital or Verification Design

Engineer

Texas Instruments USA Weblink

Software Rotation Program Texas Instruments USA Weblink

Full-time Opportunities

Title

Organization Location yProgram Guidelines

Analog Design Engineer Texas Instruments Germany Weblink

Photophysics Research Engineer KLA Tencor Singapore Weblink

AI Engineer (New Grad) KLA Tencor USA Weblink

Full Stack Software Development

Engineer

KLA Tencor India Weblink

Algorithm Software Engineer KLA Tencor USA Weblink

Software Engineering, Recent

Graduates

Microsoft Israel Weblink

Microsoft AI Development

Acceleration Program (MAIDAP),

Software Engineer

Microsoft USA Weblink

Software Engineering Microsoft Japan Weblink

Staff Engineer, Hardware

Development Engineering

Western Digital India Weblink

Signal Integrity Engineer Western Digital Israel Weblink

Reliability Engineer, R&D Engineering Western Digital USA Weblink

Funding Opportunities

Title

Organization yProgram Guidelines yDue Dates

Research Funding

NSF-Simons Research Collaborations on the

Mathematical and Scientific Foundations of

Deep Learning (MoDL)

NSF Weblink April 30, 2020

Multimodal Sensor Systems for Precision

Health Enabled by Data Harnessing, Artificial

Intelligence, and Learning (SenSE)

NSF Weblink June 8, 2020

Spectrum Innovation Initiative: National Center

for Wireless Spectrum Research (SII-Center)

NSF Weblink June 12, 2020

Microsoft Security AI RFP Microsoft Weblink April 20, 2020

Facebook AI Systems Hardware/Software Co-

Design

Facebook Weblink April 30, 2020

Facebook 2020 Networking Facebook Weblink April 20, 2020

CISCO Machine Learning and Artificial

Intelligence (ML/AI) for Networking and

Beyond

CISCO Weblink

PhD/Post-Doc and Residency Programs

MSFT Dissertation Grant Microsoft Weblink April 6, 2020

Full-time Opportunities

Title

Organization Location yProgram Guidelines

NVIDIA Enterprise Virtual GPU

Software Solutions Engineer

NVIDIA US, CA, Santa Clara Weblink

Solutions Architect - WWFO NVIDIA US, CA, Santa Clara Weblink

Developer Technology Engineer,

Public Sector

NVIDIA US, CA, Santa Clara Weblink

Software Engineer, File Systems -

GPU

NVIDIA US, CA, Santa Clara Weblink

Deep Learning Library Performance

Software Engineer

NVIDIA US, CA, Santa Clara Weblink

Front End Engineer (GeForce) NVIDIA Pune, India Weblink

Software Engineer Microsoft Austin, US Weblink

Graduates UG Software Engineer Microsoft Taipei, Taiwan Weblink

Data and Applied Science Microsoft Atlanta, US Weblink

IEEE European Test Symposium (ETS), partly virtual (not

determined), 2020; web: http://ets2020.taltech.ee/

Symposia on VLSI Technology and Circuits (VLSI), Honolulu, HI,

USA, June 14-19, 2020; web: http://vlsisymposium.org

IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Los

Angeles, California, USA, June 21-23, 2020; web: https://rfic-ieee.org/

International Forum on MPSoC for Software-Defined Hardware

(MPSoC), Les Fermes de Marie, France, June 28 - July 3, 2020; web:

http://www.mpsoc-forum.org/

Design Automation Conference (DAC), San Francisco, CA, USA, July

19-23, 2020; web: https://dac.com/

The Annual International Conference on RFID (RFID), Orlando, FL,

USA, September 9-11, 2020; web: http://2020.ieee-rfid.org/

European Solid-State Device Research Conference (ESSDERC) and

European Solid-State Circuits Conference (ESSCIRC), Grenoble,

France, September 14-18, 2020; web:

https://www.esscirc-essderc2020.org/

Embedded Systems Week (ESWEEK), Hamburg, Germany,

September 20-25, 2020; web: https://www.esweek.org/

The IEEE International Symposium on Circuits and Systems (ISCAS),

Seville, Spain, October 12-14, 2020; web: https://www.iscas2020.org

1. IEEE International Symposium on Smart Electronic Systems (IEEE-iSES, formerly

IEEE-iNIS), December 16-18, 2019, Rourkela, India:

IEEE-iSES 2019 invited 3 keynote talks, i.e., (1) “Power supplies for consumer

electronic devices” given by Santanu Mishra from Indian Institute of Technology,

Kanpur, India, (2) “Edge-AI: rise of the neural accelerators” given by Peter Corcoran

from National University of Ireland, Galway & National University of Ireland Galway,

Ireland, and (3) “Smart light-weight body worn sensors for health analytics” given by

Gaurav Sharma from University of Rochester, USA. It organized 5 sessions, i.e., (1) SIP:

Hardware for Secure Information Processing, (2) ERS: Energy-Efficient, Reliable VLSI

Systems, (3) CSN: Cyber Physical Systems and Social Networks, (3) IoT:

Hardware/Software for Internet of Things and Consumer Electronics, (4) SBD:

Hardware/Software Solutions for Big Data, (5) NVS: Nanoelectronic VLSI and Sensor

Systems (NVS), and 4 special sessions, i.e., (1) Technologies for Smart Agriculture, (2)

Technologies for Smart Healthcare, (3) Circuits and Systems for IoT Applications and (4)

Technologies for Smart Cities. It also held a research demo session and two plenaries, i.e.,

(1) Energy and Cybersecurity Constraints in Smart Electronic Systems and (2) Building

Super Intelligence through "Transfer Learning".

The General Chairs of IEEE-iSES 2019 were K.K.Mahapatra from NIT Rourkela, India

and Srinivas Katkoori from University of South Florida, USA. The Program Chairs

were Leonel Sousa from INESC-ID, IST, Universidade de Lisboa, Portugal, Saket

Srivastava from University of Lincoln, UK, and Kailash Chandra Ray from IIT Patna,

India.

2. International Conference on VLSI Design (VLSID), January 4-8, 2020, Bengaluru,

India:

VLSID 2020 organized 6 tutorials, i.e., (1) “Open-Source EDA and Machine Learning

for IC Design – A Live Update” given by Andrew B. Kahng from University of

California, San Diego and Abdelrahman Hosny from Brown University, (2) “Hardware

Platforms for Artificial Intelligence” given by Yu Wang from Tsinghua University,

Manish Pandey from Synopsys and Swagath Venkataramani from IBM, (3) “Advances

in Power Management for Secure IoT and Efficient Mobile Applications” given by

Shreyas Sen from Purdue University and Qadeer Khan from IIT Madras, (4) “Embedded

Systems: Invisible Computing” given by Luca Carloni from Columbia University,

Andreas Gerstlauer from University of Texas at Austin, Tulika Mitra from National

University of Singapore and Sri Parameswaran from University of New South Wales, (5)

“Secure Circuits and Systems” given by Makoto Ikeda from University of Tokyo,

Makoto Nagata from Kobe University, Shivam Bhasin from Nanyang Technical

Post-Conference

Report

- TCVLSI Technically

Co-Sponsored

Conferences

(Nov. 2019 to Mar. 2020)

University and Simha Sethumadhavan from Columbia University, (6) “Resiliency and

Testability: Key Drivers for Self-Driving Vehicles” given by J. A. Abraham from

University of Texas, Austin, Shawn Blanton from Carnegie Mellon University, Abhijit

Chatterjee from Georgia Tech University and Nirmal Saxena from NVidia , USA, It

invited 5 keynote talks, i.e., (1) “5G shaping future VLSI technologies” given by Baaziz

Achour, SVP of Engineering, Qualcomm Technologies Inc., (2) “VLSI – Turbocharging

the AI revolution” given by Nivruti Rai, Country Head, Intel India & Vice President –

DPG India, (3) “Technology directions for a bright semiconductor future” given by Suk

Lee, TSMC, (4) “Transforming Ideas to Reality: Emerging Nanotechnologies from the

“Lab” to the “Fab”” given by Max Shulaker, MIT, (5) “Towards a Scalable Silicon

Quantum Computer” given by Yvain Thonnert, CEA LETI.

It also held 3 plenaries, i.e., (1) AI VLSI, (2) Fireside chat: VLSI in India, (3) Startup

Panel on “Opportunities and Challenges for Semicon Startups in India”, and organized

23 sessions, i.e., (1) Codesign for Neural Network Systems, (2) Test and Verification:

Digital, Beyond Digital, (3) Architecture: Accelerators, Resilience, Security, (4)

5G/Communication, (5) Digital Systems Security, (6) Computing for EDA and EDA for

Computing, (7) Precision AMS and Bio Applications, (8) User Design Track, (9)

Biomedical and wearable systems, (10) Non-conventional electronics, (11) Architectural

advances: Processors, GPUs, Minibots, (12) Optimized Secure Systems, (13) New

Computing Enabled by Non-volatile Memories, (14) AMS Modeling and Design, (15)

AI/ML/Computing, (16) Brain-inspired Computing Hardware , (17) Design for

Resilience, (18) Arithmetic Units Revisited, (19) Analog Circuits, (20) Approximation

Techniques for Efficient Hardware, (21) Clock and Memory Circuits, (22) Thermal and

Energy Management for Multi-core, (23) IOT/Automation.

The General Chairs of VLSID 2020 were Veeresh Shetty from Mentor, A Siemens

Business and Sumit Goswami from Qualcomm. The Technical Program Chairs were

Dr. Subhasish Mitra from Stanford University, Dr. David Atienza from Swiss Federal

Institute of Technology Lausanne (EPFL) and Dr. Manan Suri form Indian Institute of

Technology.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Special Issue on

Hardware Oriented Security and Trust: Threats, Countermeasures and Design Tools

Call for Papers

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

(TCAD) is announcing a special issue on “Hardware Oriented Security and Trust: Threats,

Countermeasures and Design Tools”, which invites top papers accepted to the 2019 Asian

Hardware Oriented Security and Trust Symposium (AsianHOST 2019,

http://asianhost.org/2019/) for extension and also calls for original research papers through

public contributions.

The purpose of this special issue is to provide the targeted readers with the new advances and

challenges in hardware security research and development. Topics of interest include

discoveries of emerging security threats that are encountered by the hardware design and

supply chain, demonstration of the most recent hardware security attacks and mitigations, as

well as new security protection techniques and design methodologies that help to thwart these

threats. Relevant topics include, but are not limited to, the following:

• Architectural and micro-architectural attacks and defenses

• Secure system-on-chip (SoC) architectures

• Side-channel attacks and countermeasures

• Hardware Trojan attacks and detection techniques

• IP core protection for consumer electronics systems and IoT

• Security and trust of machine learning and artificial intelligence

• Automobile, self-drive and autonomous vehicle security

• 5G, physical layer and wireless security

• Hardware-assisted cross-layer security

• Cyber-physical system (CPS) security

• Metrics, policies, and standards related to hardware security

• Security verification at IP, IC, and system levels

• Hardware IP trust (watermarking, fingerprinting, metering, trust verification)

• Reverse engineering and hardware obfuscation

• Supply chain risks mitigation including counterfeit detection & avoidance

• Trusted manufacturing including split manufacturing, 2.5D, and 3D ICs

• Emerging nanoscale technologies in hardware security applications

• Emerging nanoscale technologies in hardware security applications

• Hardware-intrinsic security primitives (Physical unclonable functions, true random number

generator, etc.)

• Trusted platform modules and hardware virtualization

Paper Submission

All submissions must be made through the IEEE TCAD online paper submission system at

https://mc.manuscriptcentral.com/tcad. Detailed submission instructions can be found at

https://ieee-ceda.org/publication/tcad-publication/tcad-paper-submission

Submission Deadline: March 1st, 2020

Important Dates of AsianHOST 2019:

Paper Registration: 06/28/2019

Submission of Paper: 07/05/2019

Notification of Acceptance: 09/15/2019

Camera-ready Version: 10/15/2019

Guest Editors

Chip Hong Chang, School of Electrical & Electronic Engineering, Nanyang Technological

University, Singapore (Email: ECHChang@ntu.edu.sg)

Swarup Bhunia, Department of Electrical & Computer Engineering, University of Florida,

USA (Email: swarup@ece.ufl.edu)

Ryan Kastner, Department of Computer Science and Engineering, University of California

San Diego, USA (Email: kastner@ucsd.edu)

Hai Li, Electrical and Computer Engineering, Duke University, USA (Email:

hai.li@duke.edu)

Anirban Sengupta, Computer Science & Engineering, Indian Institute of Technology

Indore, India (Email: asengupt@iiti.ac.in)

Wei Hu, School of Automation, Northwestern Polytechnical University, China (Email:

weihu@nwpu.edu.cn)

Editor in Chief

Rajesh Gupta, Department of Computer Science and Engineering, University of California

San Diego, USA (Email: gupta@eng.ucsd.edu)

Deputy Editor in Chief

Xin Li, Electrical and Computer Engineering, Duke University, USA (Email:

hai.li@duke.edu) (Email: xinli.ece@duke.edu)

IP Core Protection and H

ardware-Assisted Security

for Consumer Electronics

Materials, Circuits & Devices Security

The Institution of Engineering and Technology • www.theiet.org978-1-78561-799-7

IP Core Protection and Hardware-Assisted Security for Consumer ElectronicsAnirban Sengupta and Saraju P. Mohanty

Sengupta and M

ohanty

IP Core Protection and Hardware-Assisted Security for Consumer Electronics

IP Core Protection and Hardware-Assisted Security for Consumer Electronics presents established and novel solutions for security and protection problems related to IP cores (especially those based on DSP/multimedia applications) in consumer electronics. The topic is important to researchers in various areas of specialization, encompassing overlapping topics such as EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and application specific processor/hardware accelerator design.

The book begins by introducing the concepts of security, privacy and IP protection in information systems. Later chapters focus specifically on hardware-assisted IP security in consumer electronics, with coverage including essential topics such as hardware Trojan security, robust watermarking, fingerprinting, structural and functional obfuscation, encryption, IoT security, forensic engineering based protection, JPEG obfuscation design, hardware assisted media protection, PUF and side-channel attack resistance.

About the Authors

Anirban Sengupta is an Associate Professor in the Discipline of Computer Science and Engineering at Indian Institute of Technology (IIT) Indore. He has authored more than 182 publications and patents. His is recipient of several awards/honors such as IEEE Distinguished Lecturer, Outstanding Editor Award, IEEE CESoc Best Research Award from CEM, Best Research paper Award in IEEE ICCE 2019, IEEE Computer Society TCVLSI Outstanding Editor Award in 2017 and IEEE TCVLSI Best Paper Award in IEEE iNIS 2017. He holds 12 Editorial positions in Journals. He is the Editor-in-Chief of IEEE VCAL (Computer Society TCVLSI), and General Chair of 37th IEEE Int’l Conference on Consumer Electronics (ICCE) 2019, Las Vegas.

Saraju P. Mohanty is a tenured full Professor at the University of North Texas (UNT) where he directs the “Smart Electronic Systems (SESL)”. He has authored 280 research articles, 3 books, and invented 4 US patents. He has received various awards and honors, including IEEE-CS-TCVLSI Distinguished Leadership Award in 2018, IEEE Distinguished Lecturer by the Consumer Electronics Society (CESoc) in 2017, PROSE Award for best Textbook in Physical Sciences & Mathematics in 2016, and 2016-17 UNT Toulouse Scholars award. He is the Editor-in-Chief of the IEEE Consumer Electronics Magazine (CEM). He serves as the Chair of Technical Committee on VLSI, IEEE Computer Society. He has received 4 best paper awards and has delivered multiple keynote talks at various International Conferences.

IP Core Protection and Hardware-Assisted Security for Consumer Electronics.indd 1 04/01/2019 11:18

Frontiers in Securing IP CoresForensic detective control and obfuscation techniques

Anirban Sengupta

Frontiers in Securing IP CoresForensic detective control and obfuscation techniques

Frontiers in Securing IP CoresForensic detective control and obfuscation techniques

This book presents advanced forensic detective control and obfuscation techniques for securing hardware IP cores by exploring beyond conventional technologies. The theme is important to researchers in various areas of specialization, because it encompasses the overlapping topics of EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and finally application specific processor/hardware accelerator design for consumer electronics applications.

The book begins by introducing forensic detective control and obfuscation mechanisms for hardware and IP core security. Further chapters cover hardware stenography, digital signature driven hardware authentication, fault-secured IP cores using digital signature-based watermarks, multi-level watermarking, cryptosystem-based multi-variable fingerprinting, multi-phase and hologram-based obfuscation, and security of functionally obfuscated DSP cores.

About the Author

Anirban Sengupta (PhD, FIET, FBCS) is an Associate Professor in Computer Science and Engineering at the Indian Institute of Technology (I.I.T) Indore. He has over 205 publications, 3 Books and 11 Patents and is an IEEE Distinguished Visitor of the IEEE Computer Society as well as an IEEE Distinguished Lecturer at the IEEE Consumer Electronics Society. He is an elected Fellow of the IET and Fellow of the British Computer Society. He is also the Deputy EiC of IET Computers and Digital Techniques and Chair, EiC of the IEEE Computer Society Technical Committee on VLSI as well as holding Editorial positions in more than a dozen IEEE Transactions/Journals/Magazines. He has held many Chair positions in major IEEE flagship conferences and is recipient of several IEEE Honors such as IEEE Editor Awards and Best Paper Awards from Journals/Magazines and Conferences.

Sengupta

Materials, Circuits & DevicesSecurity

The Institution of Engineering and Technology • www.theiet.org978-1-83953-031-9

1

What is TC-VLSI?

A technical committee of IEEE-CS serves as the focal point of the various technical activities within a technical discipline.

TCVLSI is a constituency of the IEEE-CS that oversees various technical

activities related to VLSI.

Join TCVLSI

It’s free to join @ bit.ly/join-tcvlsi

Technical Scope Various aspects of

VLSI design including design of system-level, logic-level, and circuit-

level, and semiconductor processes

TCVLSI Offers ‣ Student travel grants ‣ Best paper awards ‣ Timely CFP info ‣ Free membership ‣ Venue to contribute to

VLSI ‣ Circuits & Systems

Letter ‣ News & View to VLSI

Community

NEWSLETTER It’s free, 4 Issues/Year

bit.ly/vcal-news

1

STARTING A

CONFERENCE? Get in touch & Let us know!

2

LOOKING FOR

CO-

SPONSORSHIP? We want to hear from you!

3

CONTACT: TCVLSI CHAIR | ASENGUPT@IITI.AC.IN 2020

Technical Committee on VLSI (TCVLSI), IEEE-CS

http://www.ieee-tcvlsi.org

Key People

TCVLSI Chair

Anirban Sengupta, Indian Institute of Technology Indore

Newsletter EiC –

Anirban Sengupta, Indian Institute of Technology Indore

Vice Chair for Conferences –

Jia Di, University of Arkansas

Treasurer –

Hai (Helen) Li, Duke University

Vice Chair for Membership and Co-Webmaster – –

Dhruva Ghai, Oriental University Indore, India

Vice Chair for Liaison –

Nagi Naganathan, Avago Technologies

Vice Chair Outreach and Webmaster – –

Mike Borowczak, University of Wyoming

Past Chair –

Saraju Mohanty, University of North Texas, USA

TCVLSI Sister Conferences

Sponsored

ARITH: www.arithsymposium.org

ASAP: http://www.asapconference.org/

ASYNC: http://asyncsymposium.org/

iSES: http://www.ieee-ises.org (formerly iNIS)

ISVLSI: http://www.isvlsi.org

IWLS: http://www.iwls.org

MSE: http://www.mseconference.org

SLIP: http://www.sliponline.org

ECMSM: http://ecmsm2017.mondragon.edu/en

Technically Co-Sponsored

ACSD: http://pn2017.unizar.es/

VLSID: http://vlsidesignconference.org

ieee-tcvlsi.org

IEEE VCAL – TCVLSI Newsletter: Call for Contributions

The VLSI Circuits and Systems Letter aims to provide timely updates on technologies, educations and opportunities

related to VLSI circuits and systems for TCVLSI members. The letter will be published quarterly a year (containing peer-

reviewed papers) and it contains the following sections:

Features: Selective short papers within the technical scope of TCVLSI. This section introduces interesting topics

related to TCVLSI, and short review/survey papers on emerging topics in the areas of VLSI circuits and systems.

Opinions: Discussions and book reviews on recent VLSI/nanoelectronic/emerging circuits and systems for nano

computing, and “Expert Talks” to include the interviews of eminent experts for their concerns and predictions on

cutting-edge technologies.

Updates: Upcoming conferences/workshops of interest to TCVLSI members, call for papers of conferences and

journals for TCVLSI members, funding opportunities and job openings in academia or industry relevant to TCVLSI

members, and TCVLSI member news.

Outreach and Community: The “Outreach K20” section highlights integrating VLSI computing concepts with

activities for K-4, 4-8, 9-12 and/or undergraduate students.

We are soliciting contributions to all these four sections. Please directly contact the editors and/or associate editors.

Submission Deadline:

All contributions must be submitted by June 15, 2020 in order to be included in the August issue of the letter.

Editor-in-Chief:

Anirban Sengupta, Indian Institute of Technology Indore, asengupt@iiti.ac.in

Deputy Editor-in-Chief:

Yiyu Shi, University of Notre Dame, USA, yshi4@nd.edu

Associate Editors:

Features: Nicolas Sklavos, University of Patras, Greece, nsklavos@ieee.org

Features: Hideharu Amano, Keio University, Japan, hunga@am.ics.keio.ac.jp

Features: Shiyan Hu, Michigan Technological University, USA, shiyan@mtu.edu

Features: Saket Srivastava, University of Lincoln, United Kingdom, ssrivastava@lincoln.ac.uk

Features: Qi Zhu, University of California, Riverside, USA, qzhu@ece.ucr.edu

Opinions: Michael Hübner, Ruhr-University of Bochum, Germany, Michael.Huebner@ruhr-uni-bochum.de

Opinions: Yasuhiro Takahashi, Gifu University, Japan, yasut@gifu-u.ac.jp

Opinions: Sergio Saponara, University of Pisa, sergio.saponara@iet.unipi.it

Updates: Helen Li, University of Pittsburg, USA, hal66@pitt.edu (featured member story)

Updates: Jun Tao, Fudan University, China, taojun@fudan.edu.cn (upcoming conferences, symposia, and

workshops, and funding opportunities)

Updates: Amey Kulkarni, NVIDIA, USA, amey@ieee.org (Industry funding and job opportunities)

Updates: Himanshu Thapliyal, University of Kentucky, USA, hthapliyal@uky.edu (call for papers and proposals,

job openings and Ph.D. fellowships)

Outreach and Community: Mike Borowczak, University of Wyoming, USA, mike.borowczak@uwyo.edu

Emeritus Editor-in-Chief:

Saraju Mohanty, University of North Texas, USA, saraju.mohanty@unt.edu Xin Li, Duke University, USA, xinli.ece@duke.edu