Voltagestorm

VoltageStorm® Transistor-Level Rail Analysis User Guide

Product Version 10.1

December 2010

© 2009–2010 Cadence Design Systems, Inc. All rights reserved.Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA

Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission.

Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. All other trademarks are the property of their respective holders.

All other trademarks are the property of their respective holders.

Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions:

1. the publication may be used only in accordance with a written agreement between Cadence and its customer;

2. the publication may not be modified in any way;3. any authorized copy of the publication or portion thereof must include all original copyright,

trademark, and other proprietary notices and this permission statement;4. the information contained in this document cannot be used in the development of like products or

software, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration

Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

VoltageStorm Transistor-Level Rail Analysis User Guide

Contents

About This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

How This Manual Is Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Conventions Used in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Transistor-Level Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Thunder, UltraSim, and Lightning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Static and Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2Issues in Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

IR Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Symptoms of IR Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Electromigration (EM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Wearout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Joule Heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Fusing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Symptoms of Electromigration Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Advanced Processing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Evaluating Electromigration Risk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Modeling Electromigration Risk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Why Are Power-Grid Failures More Common Today? . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Advances in Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

December 2010 3 Product Version 10.1


Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Conservative Design for Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Location and Design of I/O Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Isolation of Block Power Grids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Low-Power Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Errors in Connecting Global and Block Power Grids . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Architecture of VoltageStorm Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 32Tap Currents in Decoupled Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Static and Dynamic Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Static Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Basic Dynamic Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . 47Advanced Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Correcting IR Drop and Electromigration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3Preparing to Use VoltageStorm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Required Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Transistor Circuit File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Power-Grid Resistance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Transistor Model Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Preparing to Run Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Setting Up the XTC Command File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Generating Basic Static Analysis Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Creating Model Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Creating the Circuit File for Static Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Adding Capacitance Data to the Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Creating the Circuit File for Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Backannotating Net and Device Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Updating the Circuit File for Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71



4Using VoltageStorm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Circuit Netlist File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Power-Grid Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Tutorial Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Static Ipeak Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Performing Ipeak Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Viewing Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80VoltageStorm Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Applying Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Saving Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Recommended Analysis Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Recommendations for Using Lightning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Static Activity-Based Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Using Activity Data to Compute Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Performing Activity-Based Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Static Vector-Based Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Vectors Input to Thunder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Performing Vector-Based Netlist Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Performing Vector-Based Static Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . 117

Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Vector Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Dynamic Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Performing Dynamic Netlist Analysis with Thunder . . . . . . . . . . . . . . . . . . . . . . . . . 125Performing Dynamic Netlist Analysis with UltraSim . . . . . . . . . . . . . . . . . . . . . . . . . 127Performing Dynamic Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Viewing Dynamic Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140When to Use PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140How to Use PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Static PGS for Mixed-Signal Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147



Performing Static PGS for Mixed-Signal Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

AStormCenter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Starting StormCenter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Viewing a Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Adding Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Editing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Resizing Plot Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

BPreparing to Use VoltageStorm Using QRC . . . . . . . . . . . . . . . . . 167

Required Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168PowerGrid Analysis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172Flows to prepare data for input to QRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173QRC Parasitic Extraction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Transistor Model Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Creating Model Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Running Static and Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189



About This Manual

This manual describes how to use VoltageStorm Transistor-Level PGS, the Cadence tool that analyzes your chip’s power distribution network for IR voltage drop and metal electromigration failure.

How This Manual Is Organized

This manual covers the following topics:

■ Chapter 1, “Introduction,” describes the purpose, features, inputs, outputs, and design flow involved in using VoltageStorm Transistor-Level PGS.

■ Chapter 2, “Issues in Power-Grid Analysis,” explains the potential sources of power-grid design problems related to IR drop and electromigration, as well as methodologies to detect them.

■ Chapter 3, “Preparing to Use VoltageStorm,” describes how to generate the data required to run VoltageStorm Transistor-Level PGS.

■ Chapter 4, “Using VoltageStorm,” is a guide that steps through the basic procedures involved in using VoltageStorm Transistor-Level PGS to analyze your power distribution network.

■ Appendix A, “StormCenter,” describes StormCenterTM, Cadence’s interactive waveform viewer.

■ Appendix B, “Preparing to Use VoltageStorm Using QRC,” describes StormCenterTM, Cadence’s interactive waveform viewer.

■ Glossary defines the terms and concepts that you should understand to use VoltageStorm Transistor-Level PGS effectively.

Conventions Used in This Manual

This document uses the following syntactical conventions:

■ Commands and parameters used on the command line are given in Courier font:

command_name


VoltageStorm Transistor-Level Rail Analysis User GuideAbout This Manual

■ Menu commands and the fields in dialog boxes in the graphical user interface are given in Helvetica italic font:

File – Save

An en dash (–) separates the menu name and the command name.

■ Variables for which you are to substitute a value are given in Courier italic font:

filename, cellname, layer_name

■ File names are given in Courier font:

library.lib

■ Angle brackets enclose optional parameters:

<options>

■ Vertical bars (|) in commands indicate choices.

■ Square brackets indicate that you must select one of the choices:

[a|b|c]

■ Square brackets followed by a plus sign mean that you can choose more than one of the choices, but you must select at least one:

[a|b|c]+

■ Use white space (tabs or spaces) to separate a command and its arguments.



1Introduction

The VoltageStorm product includes two separate and distinct flows that perform power-grid analysis (PGS).

The first flow, called VoltageStorm Professional Edition, analyzes and macromodels sub-blocks and cells at the top level of a design. It is designed to support efficient PGS analysis of embedded ASIC and system-on-a-chip (SoC) design styles. It has the ability to invoke PowerMeter to perform instance-based power calculation. This flow is described in the VoltageStorm Cell-Level Rail Analysis User Guide.

This manual focuses on the second flow, called VoltageStorm Transistor-Level Rail Analysis, which performs PGS down to the transistor level. For brevity, the tool is called VoltageStorm in this manual.

This chapter discusses the chip design problems addressed by VoltageStorm. It explains the potential sources of power-grid design problems related to IR drop and electromigration, as well as the methodologies to detect them.

Features

VoltageStorm is designed to help you verify that the power network on your chip does not suffer from IR drop or electromigration failure as you sign off your design. The occurrence of these types of failures experienced an upsurge as integrated circuits designs transitioned to 0.35-μm processes and continued to grow in 0.25-μm processes and below. An indication of these failures is the declining rate of first-time silicon success and the increasing number of design iterations required in manufacturing ASICs and other standard-cell designs. As a result, the application of tools such as VoltageStorm is becoming a signoff requirement in many design methodologies.

Silicon foundries do not commonly discuss these failure mechanisms as reasons for chip failure, because IR drop failures may create an appearance of poor methodology on their part. Similarly, electromigration failures may create an appearance of poor process control on the part of the foundry. In reality, most failures are a consequence of today’s increasing chip design complexity. What was once taken for granted or visually checked is now much too


../vstormpe_ug/titlecopy.html#firstpage

VoltageStorm Transistor-Level Rail Analysis User GuideIntroduction

complex, so power-grid verification tools are increasingly becoming an integral part of design flows for power-grid signoff (PGS). Foundries are endorsing power-grid signoff as a way to eliminate design surprises before designs reach the foundry. High-speed microprocessor designers were the first to adopt extended verification methodologies, and ASSP and high-end ASIC designers are adopting them today.

Approaches

VoltageStorm is designed to help you find weak spots in the implementation of your power grid at the block and full-chip stages of design. Weak spots are implementation characteristics that result in excessive IR drop, electromigration stress, or pin currents during the operation of the chip. VoltageStorm not only finds weak spots but helps you understand what implementation decisions created the weak spot.

Finding weak spots can be divided into three approaches:

■ The first is finding weaknesses in your power grid that are likely to impact the proper functioning of your chip, regardless of the magnitude of the impact. This approach is quite common and best addressed by static analysis. It is strongly recommended that you apply static analysis before dynamic analysis, because static analysis can find problems quickly. Also, static analysis can find problems that even thorough dynamic analyses can miss because of insufficient vector coverage.

■ The second approach to finding weak spots is to predict a worst-case IR drop vector on the basis of the limited coverage of the vectors for analysis. Vector compression predicts this test vector on the basis of the vectors that you have.

■ The third approach to finding weak spots is to assess the precise voltage drop on the grid for a specific test vector. This approach is common in memory design or when the cost of changing a design is high, and you want to determine the exact magnitude of the IR drop.

VoltageStorm supports all three approaches.

Transistor-Level Analysis

VoltageStorm Transistor-Level PGS performs a flat, transistor-level analysis of the power grid of true full-custom digital designs and IP blocks. If you are not using easily identifiable library elements, you may require transistor-level recognition. It is intended for those using an SoC design methodology or an ASIC methodology and who want accuracy down to the transistor level.



Thunder, UltraSim, and Lightning

VoltageStorm uses Thunder or UltraSim™, which are netlist analysis tools, and Lightning, which is a power-grid analysis tool, to perform these analyses. Thunder performs a transistor-level analysis of your design. It analyzes the entire transistor netlist by using the voltage sources, transistor model data, and vectors that you provide. A power grid in Thunder is modeled as a single node.

Lightning performs a detailed analysis of that power-grid node when the node is represented by its actual resistor, inductor, and capacitor components. It only processes the devices connected directly to the power grid of interest. The power grid is modeled as a linear circuit with voltage sources representing the power pins and current sources representing the transistor taps on the grid. Power current flows from the voltage sources, through the grid, and out the current taps. Proper analysis requires all three components: the voltage sources, the resistor-inductor-capacitor grid, and the tap current sinks. If the design contains no tap current sink, the entire grid is at the voltage of the sources (assuming that they are at the same voltage). You must add voltage sources in Lightning. If the design contains no voltage sources, the power grid cannot be analyzed. Without a power grid, there is nothing to analyze.

Thunder calculates current information for each device connected to the power grid (VDD or VSS) and passes these currents (plus device capacitances for dynamic power-grid signoff) to Lightning. The interface between the tools is based on the names of the devices (almost always transistors) connected to the power node. Thunder passes current and capacitance data to Lightning for each transistor. Lightning passes IR drop data to Thunder for each transistor. Itaputil either reports the characteristics of tap current files or extracts portions of the data and places them into a new tap current file.

As an alternative to Thunder in the dynamic analysis, you can use Cadence’s UltraSim simulator. UltraSim is a fast, multi-purpose, single-engine, hierarchical simulator, designed for the verification of analog, mixed-signal, and digital circuits. UltraSim provides accurate, vector-based dynamic circuit simulation and high-performance hierarchical circuit simulation and rail analysis while greatly improving the performance and capacity of the dynamic analysis.

The UltraSim dynamic analysis offers two flows:

■ It can use lumped capacitance for the signal nets for higher performance in the actual circuit simulation.

■ It can use distributed resistance and capacitance for signal nets for greater accuracy in signal timing.

See “Performing Dynamic Netlist Analysis with UltraSim” on page 127 for detailed information about these two flows.



Thunder differs from UltraSim in the following ways:

■ Thunder requires you to run Tablegen for MOS devices before using Thunder. UltraSim reads in the models directly without requiring you to use Tablegen.

■ Thunder requires the .simplexlib command in the circuit file to specify the table models. UltraSim requires the .lib command in the circuit file to specify the SPICE model file.

■ Thunder directly reads the capacitance database output by Ice when you use the .capdb command in the circuit file. It can also read the DSPF file output by Rain. In contrast, UltraSim reads the output of the capdbutil utility, which processes the Ice capacitance database, when you use the .usim_opt capfile command in the circuit file.

Static and Dynamic Analysis

VoltageStorm supports both static and dynamic analysis.

For static analysis, you can use these methodologies:

■ Accura, an algorithm embedded in LibGen that performs activity-based static analysis

■ Maximum saturation currents

■ Net activity data

■ Vector-based netlist analysis

These methodologies are described in detail in “Static Power-Grid Analysis Methodologies” on page 42.

For dynamic analysis, you can use these methodologies:

■ Single-vector analysis

■ Vector compression

These methodologies are described in detail in “Basic Dynamic Power-Grid Analysis Methodologies” on page 47.

In addition to these, VoltageStorm offers advanced methodologies for both static and dynamic analysis. These are described in “Advanced Power-Grid Analysis Methodologies” on page 52.



PGS Exploration

PGS Exploration enables you to perform power-grid ECOs within VoltageStorm. Before PGS Exploration, engineering change orders (ECOs) that addressed power-grid problems identified by VoltageStorm required you to complete a lengthy and complex ECO loop, as shown in Figure 1-1 on page 13.

Figure 1-1 ECO Loop Before PGS Exploration

Because of the complexity and number of steps involved, performing and validating the effects of such an ECO was both time-consuming and resource-intensive.

Since PGS Exploration enables you to perform power-grid ECOs within VoltageStorm, you can remove all power-grid problems from a design in a single ECO pass. Once the power grid is clean in VoltageStorm, you then create a single ECO list, called a change report, which guides the implementation of the layout modifications necessary to create the clean power-grid design, as shown in Figure 1-2 on page 14.

ECO loop

Edit the power-grid layout

Re-extract the power grid

Re-load power grid into VoltageStorm Transistor-Level PGS

Perform power-grid solve

Layout environment

Fire & Ice

VoltageStorm Transistor-Level PGS



Figure 1-2 ECO Loop Using PGS Exploration

PGS Exploration enables you to quickly experiment with power-grid changes, then use VoltageStorm’s static power-grid analysis to show the effects of these modifications on the performance of the power grid. Because all this ECO functionality is available within VoltageStorm, you do not need to re-extract and re-load the power-grid network with each ECO, so the turnaround time is extremely fast.

Note: Because PGS Exploration is based on modifications to the resistive network of the power grid, use it only with static power-grid analysis. Using PGS Exploration with dynamic power-grid analysis is not recommended.

Design Flow

A detailed view of the design flow involved in using Thunder in VoltageStorm is shown in Figure 1-3 on page 15. The design flow involved in using UltraSim in VoltageStorm is shown in Figure 1-4 on page 16.

See Appendix B, “Preparing to Use VoltageStorm Using QRC” for a flow using QRC rather than Fire & Ice. The QRC interface provides the ability to model small geometries (90nm, 65 nm ...) accurately.

Change power grid in VoltageStorm

Perform power-grid solve

ECO loop

Back to layout to implement changes

Create ECO change report

All within VoltageStorm



Figure 1-3 VoltageStorm Static and Dynamic Design Flow with Thunder

Resistanc

GDSII

Hierarchical Calibre

Connectivity

XTC

Annotat

SPICE Stripe

Capacitan

DistR

MergeNet RC

Power-

Ice Fire

Lightning

or

Thunde

Tap current data

(*.ptiavg,

Transistor

Pass/fail Voltage source

Rain Interconnect

Tablege

Activit

Model

Comma

VCD file

Vector

Circuit



Figure 1-4 VoltageStorm Dynamic Design Flow with UltraSim

Resistanc

GDSII


Connectivity

XTC

Annotat

SPICE Stripe

Capacitan

DistR

MergeNet

RC

Power-

Ice Fire

Lightning

or

capdbut Circuit

UltraSi

Tap current data

(*.ptiavg,

Transistor




Inputs

The input to VoltageStorm is a GDSII file output by a place-and-route tool.

Outputs

As output, VoltageStorm produces plots of power-grid IR drop, resistor current flow, and electromigration analysis. In addition, it can produce these outputs:

■ Filtered plots, which are plots of your design with filters applied to data values. The filters determine the subset of data that you view and how each subset should be colored to make the plot meaningful. These plots can be stored in GIF format.

■ Text reports, which contain the subset of the data in which you are interested. The specific data reported is controlled by the filters just described. Although text reports are easy to pass to other tools, they can be very large if you do not filter carefully.

■ Sorted text reports, which can rank your data in worst-case order. You can print this data or access it interactively to take you to the worst errors on your chip.

■ GDSII overlays of filtered data, which enable you to overlay the results of your analysis filtering directly on top of the design in the layout editor.

■ Saved states of your power grid, which you can reload at a later time. This option makes it more efficient to perform data filtering because you do not need to perform the solve again.

■ Movies, which are a unique feature of dynamic analysis in VoltageStorm. Plots of individual time steps are created in the same form as in static analysis but can be placed together to form an animated sequence of your power grid’s behavior.



2Issues in Power-Grid Analysis

This chapter discusses the chip design problems addressed by VoltageStorm. It explains the potential sources of power-grid design problems related to IR drop and electromigration, as well as the methodologies to detect them.

IR Drop

IR drop is a reduction in voltage that occurs on both power and ground networks in integrated circuits. Integrated-circuit design usually assumes an ideal power supply that can instantly deliver any amount of current to maintain the specified voltage throughout the chip. In reality, however, narrower metal line widths cause an increase in the resistance and therefore in the amount of voltage drop in the chip. The amount of voltage drop depends on the effective resistance from the pad to the gates.

Figure 2-1 on page 19 illustrates the concept of IR drop.

Figure 2-1 Typical Power-Grid Structure

This figure shows a power supply connected to the chip pads. The power distribution system (generally a grid) is illustrated by the R11-R14 resistors for VDD and R21-R24 resistors for VSS. G1-G4 are the connections between logic gates on the power distribution system. Typically, when you perform transistor-level simulation, these voltages (V1- V4) are assumed to be equal. In other words, all R11-R14 and R21-R24 resistances would be 0.0 ohms, so all G1-G4 gates would have ideal power supply voltages, VDD and VSS.

+-

Vpower

VSS

VDD

Pad

Pad R11

R21 R22

R12

R23

R13

R24

R14

G1 G2 G3

I3I2I1 I4

G4

V1 V2 V3 V4


VoltageStorm Transistor-Level Rail Analysis User GuideIssues in Power-Grid Analysis

In reality, the power-grid resistances of a chip are non-zero. For example, gate G4 never has an ideal VDD voltage at its power pin when it is active; it has a lower voltage. The current flowing from the power supply to G4 must flow through the power distribution network. A current, I, flowing through an effective resistance, R, introduces a voltage drop, V = IR. (The term “IR drop” is derived from IR.) IR drop or ground bounce on the VSS power-grid distribution network is an increase in the VSS voltage at gates G1-G4.

Figure 2-1 also illustrates the complexity of power grids and IR drop. Assume that gate G4 has a VDD power-grid current of I4 amperes. No other gate has current. The I4 current flows from the power supply through the power grid to G4. The IR drop at gate G4 is then I4(R11+R12+R13+R14). In addition, because of the I4 current at gate G4, gate G2 does not have an ideal power supply. It has an IR drop of I4(R11+R12). Therefore, the current of each gate in a design causes some type of IR drop for all other gates in the design. If the gates along the metal line switch together, the IR drop can be large. Given simultaneous currents I1-I4 for the G1-G4 gates, respectively, in Figure 2-1 on page 19, the IR drop at gate G4 would be the following:

I1(R11)+I2(R11+R12)+I3(R11+R12+R13)+I4(R11+R12+R13+R14)

IR drop can be either a local or global phenomenon.

■ IR drop is a local phenomenon when a number of gates in close proximity switch at once, causing IR drop in that proximity. Local IR drop can also be caused by a higher resistance to a specific portion of the grid, such as R14 being much larger than expected.

■ IR drop is also a global phenomenon when activity in one region of a chip causes IR drop in other regions. In a well-meshed power grid with equally distributed current, the power grid typically has a set of equipotential IR drop surfaces that form concentric circles centered in the middle of the chip, which has the largest IR drop. Large gate currents throughout the chip increase the magnitude of these equipotential IR drop surfaces.

The IR drop formulations illustrate why it is important for the gates in a design to switch at different times. If they all switched at once, the local or global IR drop on a chip would be extremely large. For some portions of a design, however, it is important for the gates to switch together. The clock and the latches that it drives must switch together in a synchronous digital system, so some amount of IR drop is inevitable in a chip.

Figure 2-1 on page 19 also illustrates the difference between average and peak IR drop. If all four gates switched at once, the IR drop at gate G4 is that shown by the calculation given earlier in this section. If this peak current occurred over one fourth of the clock cycle, the average IR drop at gate G4 over the entire clock cycle would be one quarter of that value. The peak IR drop at any location in a chip can therefore be much larger than the IR drop averaged over a clock cycle. As the size of a block increases, the ratio of the peak IR drop to the average decreases towards 1.0, because the probability of many gates switching at once decreases significantly. The primary causes of simultaneously switching IR drop (noise) is the switching



of the clock, a bus, or signal pads. These problems are due to many large gates switching synchronously in one area. You can easily recognize these situations and verify them.

Symptoms of IR Drop

Because the number of failures resulting from IR drop has become significant only recently, many designers do not look at power distribution as a potential source of chip failure. The symptoms of IR drop problems can frequently resemble timing or even signal integrity problems. Symptoms of IR drop problems include the following:

■ Non-functional chips. If the global IR drop is too high when a chip operates, logic gates malfunction. The failure resembles a logical functional failure or manufacturing problem, although logic simulation indicates that the design is correct. One way of diagnosing this symptom is to increase the power supply voltage and see if the chip works.

■ Intermittent or data-dependent functional failures. Local IR drop problems are sensitized, or forced to occur, by specific operations in close proximity, such as all bits of a bus switching at once. In normal operation, the specific sensitization might not occur. However, a specific data input activates the problem. The symptom appears as a logic functional failure of that portion of the chip.

■ Timing failure. When the global IR drop is high, but not high enough to cause complete logic failure, the symptom is a timing failure of the chip. In this case, the IR drop slows down the speed of the gate operation. Experiments have shown that a 5 percent IR drop on a gate can slow down its speed by up to 15 percent. The reduction in speed is due to two mechanisms, as shown in Figure 2-2 on page 22. First, the IR drop on the power input of gate G1 slows the charging speed of the output of that gate. Explained simply, the output voltage of gate G1 rises only up to VDD minus the IR drop. In turn, this drop reduces the logical high input voltage to gate G2, reducing its switching speed as well.



Figure 2-2 Impact of IR Drop on Gate Speed

■ Intermittent or data-dependent timing failures. Like intermittent functional failures, specific data inputs can cause IR drop that appears to be a timing failure. An intermittent timing failure of this type is also symptomatic of a signal net cross-coupling capacitance problem. One way of diagnosing this symptom is to decrease the clock frequency and see if the chip works.

Electromigration (EM)

Electromigration is used as a general term to describe failure mechanisms in the metal wires of a computer chip caused by the movement of metal atoms in a wire because of high current stress. As electrons move through a metal wire, they collide with the atoms in that wire. These collisions cause wires to become heated, and If enough electrons collide with a metal atom over a period of time, the metal atom may move in the direction of the electron flow, causing two problems.

■ First, if enough atoms are moved, the wire effectively breaks and becomes an open circuit.

■ Second, if enough atoms move to the same location, a short to an adjacent metal wire can be created. This phenomenon is commonly known as fusing.

Either of these mechanisms changes the functionality of the chip.

Two distinct physical phenomena cause electromigration: wearout and Joule heating.

+-

VDD VDD-IR drop

Gate G1 Gate G2

VIH

I



Wearout

Electromigration in a specific sense is a long-term wearout mechanism of chip interconnect wires.

As metal atoms are moved and the wire becomes narrower (in the location from which the atoms are moving), the resistance of the wire increases. If atom movement continues, the wire eventually breaks.

Because wearout can take a significant amount of time to be observed, failure due to wearout is measured as a statistical process and is characterized by a wire’s mean time to failure (MTTF).

To reduce the impact of electromigration, chip interconnect wires on a given metal layer are built from several metal materials in a sandwich fashion. The extra metal layers in the wire, generally the top and the bottom layers in the sandwich structure, are more resistant to electromigration, so they help prevent total wire failure because of breaks. Electromigration failures are therefore defined as an unacceptable increase in the resistance of the wire rather than an outright break in the wire. Because electromigration is the result of long-term wearout, the risk to a wire is measured in terms of the long-term average current flowing through the wire.

There remains some debate in the reliability community about the proper model for wires exposed to alternating current flow. One approach indicates that when the average current is 0 A, no electromigration occurs. Another approach says that the recovery from the reversed current is not full, so the average should be the peak in one direction minus a recovery factor times the reverse current. A recovery factor of 0.0 indicates no recovery, and a factor of 1.0 indicates full recovery.

Joule Heating

Joule heating refers to the excessive heating of a specific segment of a wire because of high alternating currents. Wires are heated as alternating current moves through them. This heating occurs regardless of the direction of the current. If the heating of the wire becomes significant, thermal expansion and temperature-induced electromigration occurs. Since the risk of Joule heating increases with temperature, and increasing frequency increases heating effects, electromigration due to Joule heating is associated with high-frequency wires.

Because the root cause of Joule heating failure is different from electromigration, different measures are applied in verification.



Fusing

Fusing is a specific failure mechanism related to electromigration. It refers to the instant failure of a wire segment because of excessive instantaneous current. To address this failure mechanism, different measures are applied in verification. Some reliability researchers classify this failure mechanism as a subset of Joule heating.

Symptoms of Electromigration Problems

Because electromigration is a wearout phenomenon, its symptoms are primarily a change in either the timing or functionality of a chip over time. Wires that provide unique connectivity in the circuit cause total functional failure if they break because of electromigration. Wires that are inherently redundant, such as a meshed power grid, exhibit symptoms of high IR drop after electromigration failure results in disconnected sections of the power grid. If electromigration causes a short between wires on a chip, total functional failure occurs.

Advanced Processing Techniques

Using metals such as titanium nitride and copper in chips can also contribute to electromigration failure.

Titanium Nitride

To reduce the impact of electromigration, chip interconnect wires on a given metal layer are built from several metal materials in a sandwich fashion, as shown in Figure 2-3 on page 24.

Figure 2-3 Multiple Materials Used to Build a Single Wire

Generally the top and the bottom layers in the sandwich structure are constructed from titanium nitride (TiN), which is more resistant to electromigration. This structure helps to prevent total open circuit failures; however, because the resistivity of the TiN layer is greater

AluminumTitanium nitride



than aluminum, electromigration failures are defined as an unacceptable increase in the resistance of the wire rather than an outright break in the wire.

Copper Interconnect

State-of-the-art process technologies use copper as chip interconnect material because copper offers not only lower resistivity but also higher resistance to electromigration wearout. However, copper interconnect structures are not as deep as aluminium structures, so the cross-section area is smaller and therefore the current densities are higher. As a result, electromigration-based failures still occur in copper structures.

In contrast to aluminum-based processes, vias built with copper increase the likelihood of electromigration wearout and require more detailed verification.

Evaluating Electromigration Risk

Electromigration occurs in metal wires that conduct high current densities. Conducting electrons collide with diffusing metal atoms and impel the atoms in the direction of electron flow. This collision produces a mass flux opposite to that of the current. Divergences in this mass flux can result in damage to the conductor in the form of voids or hillocks. You can minimize this problem by limiting the current density in metal conductor lines, vias, and contacts.

Electromigration resistance is primarily a function of processing parameters. Many of the variations observed in the lifetime behavior of conductors because of electromigration cannot be attributed to a specific cause. In addition, material contains significant lot-to-lot variations. To fully understand electromigration within the chip, you must be familiar with the specific properties of your own material and process.

In some cases, complete data is not available. The following suggestions may help you in making an evaluation. The figures quoted here are from relevant literature over the past 25 years; you should consider them non-definitive values and not necessarily representative of your material or process. Cadence provides these figures only as background information.

In recent evaluations of electromigration performance in the industry, it has become commonplace to observe that failures in lines connected to bond pads obey 1/j2 kinetics and that lines connected to vias and contacts usually obey 1/j kinetics. Therefore, these are the default values used in this simulation. If you have evidence that your process provides other kinetics, you can make suitable changes in the modeling.

The following table shows the pre-exponential, A, and activation energy for line and via electromigration failure for wide and narrow lines for a variety of alloys. The values chosen are conservative and represent the latest data available from leading industrial laboratories.



Al/Si figures are estimated from the expectation that lifetimes without Cu alloying are about 10 percent of those with Cu. No recent data on this assumption is available, and earlier data is questionable in view of recent advances in electromigration testing procedures.

Note: These values are not independent. If you choose a different value for the activation energy, it is necessary to determine another value for A.

Table 2-1 Pre-Exponential, A, and Activation Energy for Line and Via Electromigration Failure

The units of A are the following:

■ Amp-hours per cm2 degree for n=1

■ Amp2-hours per cm4 degrees for n=2

For vias, the current density is defined as the current density in the wire immediately contacting the via or the contact to silicon. This density is assumed to be for a line with a width equal to the via. Al and Al/Si are assumed to be equivalent, and all Al/Cu alloys are assumed to be created equal.

1. Anthony S. Oates, Proc. 34th Ann. IRPS, 164 (1996)

Metal Configuration n A Ea

Al/Si wide line 2 130 to 20,000 0.5 eV

Al/Si narrow line or Al/Cu wide line, with or without barrier shunt layer

2 1,300 to 80,000 0.6 eV

Al/Cu narrow line without barrier shunt layer

2 1,300 to 200,000 0.8 eV

Al/Cu narrow line with barrier shunt layer 2 13,000 to 800,000 0.8 eV

Al/Si via 1 .00001 0.8 eV

Al/Si via 2 7.5 0.5 eV

Al/Cu via without barrier 1 .0001 0.8 eV

Al/Cu via without barrier 2 75 0.8 eV

Al/Cu via with barrier 1 .0004 to .008 0.8 eV

Al/Cu via with barrier 2 300 to 16,000 0.8 eV



2. Carole D. Graas, Huy A. Le, Joe W. McPherson, and Robert H. Havemann, Proc 32nd Ann. IRPS (1994)

3. Keiichi Hashimoto, Kenshin Touchi, and Hiroshi Onoda, Proc. 32nd An. IRPS, 18 (1994)

An additional source that you may wish to check is Bill Baerg, Rob Crandall, and Ken Wu, 32nd Ann. IRPS, 195 (1994).

Refer to the VoltageStorm Transistor-Level Rail Analysis User Guide or the VoltageStorm Cell-Level Rail Analysis Users Guide for information on power-grid analysis. Refer to the ElectronStorm Manual for information on signal electromigration analysis.

Modeling Electromigration Risk

Electromigration risk analysis requires the use of failure models. The choice of failure model depends on the particular manufacturing process and design rules. The failure kinetics vary according to the metal line width. They must be determined from the test structures. Model parameters such as A_n, A_w, and n (the current density coefficient) are used to describe the predominant failure kinetics.

On the basis of the calculated average current density, Cadence analysis tools use Black’s Equation to determine the mean time to failure (MTTF):

■ n is either 2 for nucleation-dominated failure or 1 for growth-dominated failure.

■ A is the technology and structure dependent pre-factor.

■ T is the temperature.

■ m is the temperature coefficient.

■ j is the average current density.

■ Ea is the activation energy for the electromigration mechanism.

■ k is Boltzmann’s constant.

The MTTF is then used to calculate the probability of failure for a line segment:

t50ATm

jn-------------exp Ea

kT--------⎝ ⎠

⎛ ⎞=


../voltagestorm/titlecopy.html#firstpage

../vstormpe_ug/titlecopy.html#firstpage


■ t is the expected lifetime of the design, which you can specify by using the Lifetime environment variable.

■ σ is the lognormal standard deviation. It is process-dependent and must be determined by using test structures. It is a model parameter that you can specify layer by layer.

After Cadence analysis tools calculate the failure probability for each wire segment, they use the following calculation to determine the failure probability for the full chip:

This approach assumes a lognormal failure distribution, which is analogous to the weakest link in a chain.

Cadence analysis tools report the overall probability of failure after they finish the analysis. They report the inverse of the failure probability for each wire segment as electromigration risk.

You must specify several processing parameters for each layer to obtain good results from electromigration risk analysis. See “model” in the Lightning Manual for these parameters and their default values; these defaults assume Al/Cu metal layers. In addition, you should set the Default_Temp and Lifetime .simplexrc environment variables.

Cadence analysis tools can include temperature effects on resistance. The model parameters for each layer now include fields for TC1, TC2, and TREF. The resistance of a resistor is calculated by using the following formula:

Reffective=R*(1+TC1 * delta_t + TC2 * delta_t2)

Pfi t( ) σ2π ln t50 t⁄( )

-------------------------------------expt50 t⁄( )ln

2σ----------------------------

⎝ ⎠⎜ ⎟⎛ ⎞ 2

–=

pf n t,( ) 1 1 Pfi t( )–( )i 1=

n

∏–=


../lightning/titlecopy.html#firstpage


where delta_t is defined as the default temperature minus TREF.

Lifetime is defined as the probable time, in years, until failure because of electromigration. You use a lifetime calculation during electromigration risk analysis. Cadence analysis tools calculate the probability of the chip failing by the time specified by the Lifetime global environment variable.

The probability of failure ranges between 0 and 1, although a probability of 1 indicates that assumptions were violated in the calculations. If the reported probability of failure is high, it means that there are components in the design with relatively short mean times to failure. Examine these components, and make modifications to lower the probability of failure.

Why Are Power-Grid Failures More Common Today?

A combination of factors causes the increase in IR drop and electromigration failures. In the past, designers of low-frequency circuits implementing 0.35-μm three-layer metal processes rarely encountered IR drop or electromigration issues. However, designs with frequencies above 100 MHz, 0.25-μm processes, or four or more layers of metal increase the risk of problems.

Advances in Processing

The first set of causes is related to advancements in processing. Most chip feature sizes are decreasing in accordance with Moore’s Law. Transistor sizes are decreasing, permitting a higher density of design. New, more powerful transistors require a lower-power supply voltage to avoid device failures. A lower supply voltage means lower noise margins (IR drops permitted) on power grids. On the other hand, the ability to design increasingly complex chips leads to increases in overall size and power dissipation. To design the larger chips, more metal layers are being used to implement longer signal and power routing. Narrower wires have higher resistance than previous technologies. These higher-resistance wires and the higher overall power currents naturally lead to increases in IR drop or power-grid noise. The conflicting design trend toward lower noise margins means that you must seek a balance between inherent power-grid noise and power supply noise margins to achieve a successful design. As your design increases in frequency or size, the design space in which you have to balance decreases in area.

The natural response to balancing the technology trends is to be more conservative in power-grid design. But more conservative power-grid design means sacrificing chip area—a potentially high cost.

Other trends in processing present additional problems. Via and contact resistances are not scaling in accordance with Moore’s Law. The trend is to remain the same or increase in



resistance. Skin effects limit the effective width of power wires. The higher currents flowing through narrower power grids also increase the current density in power-grid wires, increasing the risk of electromigration.

Design Tools

A second set of causes of IR drop is the design tools that you use to create power grids on chips. Placement and routing tools today cannot assess the impact of design decisions on IR drop. As a result, these tools introduce the following problems:

■ The parallel nature of data, such as a 64-bit-wide bus, means that placement tools naturally place drivers of each bit of the bus near each other. Large drivers in a local area are a common cause of local IR drop problems. When all bits of the bus switch at once, a local brownout may result.

■ As mentioned earlier, clocks in chips must operate synchronously. Simultaneous clock switching introduces a large, instantaneous IR drop on your power grid. The clocks on some chips today consume up to 40 percent of the chip’s total power. More sophisticated manual clock design purposely skews various clock drivers to reduce IR drop noise as well as radio frequency interference.

■ In addition to clocks, a general trend in design tools is to minimize the delay of switching signals over the clock cycle to minimize the delay of timing-critical paths. As a result, most circuit activity in a design occurs just after the edge of the clock, creating a high instantaneous power demand just after the demand due to the clock itself.

■ Power routing causes problems such as the creation of a via cluster between two large power buses on different metal layers with a single via rather than with an array of 25 or more vias. A single via can be the source of serious IR drop problems and electromigration risk on a chip.

For example, via array-filling procedures cannot determine if the via array is large enough for the buses involved. In addition, power-planning techniques in place-and-route tools are too primitive to prevent these problems.

Hierarchical Design

Hierarchical design is a common practice today, leading to the third common cause of IR drop and electromigration problems. In creating large designs, it is natural to design functional blocks separately and combine them in the final design. However, power grids of blocks are designed to route power only for the block. When blocks are assembled in the design, the union of their individual power grids creates the full-chip power grid. The flow of current through the resulting power grid is usually different from what you expect. You may observe



power current flowing through blocks rather than in the guard bands around them. An effective power grid for the block also creates a low-resistance power bus for neighboring blocks. This increase in current through the block creates a potential for electromigration or IR drop problems. Avoiding this problem requires some knowledge of the floorplan and power routing of the chip to account for feedthrough currents in the block design.

Conservative Design for Timing

The fourth common cause of IR drop and electromigration problems is over-conservative design for timing. For example, suppose that a chip exhibits intermittent timing problems after first fabrication. Increasing the buffer size on the assumption that the problem was due to path delays results in the complete functional failure of the chip during second fabrication. The source of the failure, in reality, is IR drop rather than timing. Increasing buffer sizes worsens the problem rather than corrects it. Conservative design for timing must now be balanced with power-grid design.

Location and Design of I/O Pads

The location and design of I/O pads is the fifth source of IR drop and electromigration problems. Simultaneously switching output pads, which always have a large load, creates a strong demand for power current and causes IR drop. The placement of I/O pads and power pins is a difficult design challenge. I/O rings normally have independent power rings and pads to prevent I/O ring IR drops from affecting the internal chip power.

Isolation of Block Power Grids

Another common source of IR drop problems is the isolation of block power grids. It is common to isolate the power grids for sensitive blocks in a design, such as phase-lock loops and memories. However, power-grid problems can result from excessive isolation or insufficient isolation.

■ Excessive isolation occurs when the block’s power grid is so well isolated that the resistance from the power pad to the block is excessive, causing IR drop.

■ Insufficient isolation occurs when neighboring blocks create IR drop that seeps into a sensitive block. IR drop in sense amplifiers is a particular concern for memory designers.

Low-Power Design

The seventh source of IR drop problems is low-power design because of the difference between average and peak power consumption of blocks. The goal of the power grid of a



block is to distribute the block power current among a number of connections to a global power grid. The global power grid then distributes that current among the power pins. If the current is not distributed well, large IR drops may occur.

Many low-power design methodologies apply techniques to reduce the average power dissipation of a block. Techniques such as gated clocking isolate power demands to times of block activity. Power consumption of the block is normal when activated. By gating the clock, you reduce the average power, but the peak power remains as before, creating a potential source of problems. Low power consumption does not necessarily mean low IR drop. If you design the block power grid on the basis of average power consumption, undersized power buses will create IR drop problems.

Errors in Connecting Global and Block Power Grids

The last source of IR drop problems is errors in connecting global power grids to block power grids. It is common to design global and block power grids separately. In these cases, the global grid is designed to be simply attached to the block power grid at a large number of points after the block is finally placed. Either manual or automatic techniques are used to insert the vias in the design where the grids are to be connected. This attachment of grids is prone to error. Attachment points are often missed, resulting in large IR drops to portions of the chip. Because there is always at least one attachment point, the chips are free of design-rule errors. The problems are only discovered when power-grid analysis is applied.

Power-Grid Analysis

Power-grid analysis is designed to help identify weak spots in the power network. Weak spots are implementation characteristics that result in excessive IR drop, ground bounce, or electromigration stress of the power grid under operating conditions. A good power-grid analysis tool not only helps you find such weak spots but also helps you understand what you must change to improve the weak spots. You can use many different approaches to identify and correct weak spots in a power grid, including static, activity-based, and dynamic analyses. The value of each of these different approaches is discussed later in this manual.

Power-Grid Analysis Methodologies

VoltageStorm is referred to as an analysis tool here rather than as a simulator, because it performs more analysis than just simulation. This section describes the power-grid analysis methodologies available in VoltageStorm. They are presented here at a high level. Chapter 3, “Preparing to Use VoltageStorm,” explains the data preparation required for VoltageStorm. Chapter 4, “Using VoltageStorm,” examines these flows in detail.



Architecture of VoltageStorm Power-Grid Analysis

Power-grid analysis involves the extraction of power grid and netlist data from your chip layout, followed by analysis of the power grid and netlist. The architecture of the analysis portion of the system can take two forms:

■ Integration of netlist and power-grid simulation

■ Decoupled netlist and power-grid simulation

Integrated Netlist-Power-Grid Simulation

Figure 2-4 on page 33 shows the high-level flow for integrated analysis.

Figure 2-4 Integrated Netlist-Power-Grid Simulation Flow

While this flow has the advantage of simulating the netlist and the power-grid together so that there is a tight coupling between the simulations, integrated simulation has a high price in terms of capacity and solution performance. Simulating the transistor-level netlist alone can be overwhelming for most simulators. Simulating the power grid can also be overwhelming. Competing for the same resources limits the size of the design that you can consider. Capacity and performance limitations make this flow best suited to block analysis. Because many IR drop problems are due to block interactions at the full-chip level, this approach can leave you stranded when you need it most.



Decoupled Netlist-Power-Grid Simulation

Figure 2-5 on page 34 shows the high-level flow for decoupled analysis.

Figure 2-5 Decoupled Netlist-Power-Grid Simulation Flow

This flow has the advantage of maximizing the capacity of each component of the system, yielding a much higher capacity than integrated analysis. In addition, this flow has greater flexibility than integrated methods for computing or importing tap current information. On the other hand, this flow does not instantly evaluate the impact of IR drop on netlist simulation. Fortunately, this feedback is not required to solve the real problem in power-grid analysis—finding weak spots in the power grid. Therefore, VoltageStorm is designed in accordance with the flow shown in Figure 2-5 on page 34. Feedback is required if your objective is to perform an accurate simulation of the netlist in the presence of IR drop. This feedback is provided by VoltageStorm, but it is especially important in ClockStorm, the clock analysis tool.

This feedback is not required for finding power-grid problems, because the objective of finding weak spots in the power grid is achieved in the first pass from netlist analysis to power-grid analysis. This first pass finds worst-case (conservative) IR drops. The feedback only serves to refine the accuracy of netlist analysis. The impact is small when the IR drop is small. The



feedback from power-grid analysis to netlist analysis does not improve VoltageStorm’ ability to find power-grid problems. The timing at which dynamic problems arise may change slightly, but the problems are still present in the power grid.

Tap Currents in Decoupled Analysis

The interface between netlist analysis and power-grid analysis in Figure 2-5 on page 34 is implemented by using tap currents. In most cases, each tap current is a transistor current, but it could be from a variety of elements. This decoupled interface permits a wide variety of methodologies to be applied, depending on how tap currents are computed, represented, or imported from other sources. As you will learn in “Advanced Power-Grid Analysis Methodologies” on page 52, VoltageStorm can accept different tap current files computed from netlist analysis of different blocks and effectively merge the data into a full-chip power-grid analysis.

What Are Tap Currents?

Tap currents are currents arising from the connection of transistors to the power grid. Figure 2-6 on page 35 shows a typical netlist analysis view of transistors connected to a power grid.

Figure 2-6 Transistor Simulation Model of Transistors on the Power Grid

Netlist analysis treats the power grid—in this case, VDD—as an ideal wire, that is, a wire with no resistance. The netlist analysis tool analyzes the entire transistor netlist. It monitors the currents in the VDD wire originating from each individual transistor—M1, M2, and so forth. It then passes the monitored transistor currents to the power-grid analysis, as shown in Figure 2-7 on page 36. If the netlist has 1 million transistors connected to the VDD wire, data for 1 million transistors is passed to the power-grid analysis.

M1 M2

VDD



Figure 2-7 Modeling of Transistors on the Power Grid

Power-grid analysis includes no information about any transistors other than those connected to the specific power grid being analyzed. In a typical digital design, one third of the total number of transistors is connected to VDD, one third is connected to VSS, and the rest are connected to internal nodes in logic gates. Because the primary elements in common between netlist analysis and power-grid analysis are the transistors connected to the power grid, those transistor names—for example, M1—are used as the identification for passing data from one tool to the other. Power-grid analysis models transistor currents as current sources attached to the power grid. The tap current data file provides the details for each current source. Tap current files can be static, where only a single current value is provided for each transistor, or dynamic, where a sequence of data points is provided for each transistor. These currents are used to perform either a simple steady-state analysis or a dynamic analysis of the power grid.

How Does VoltageStorm Compute Tap Currents?

Transistors have four terminals: drain (D), gate (G), source (S), and bulk (B). A typical p-type representation is shown in Figure 2-8 on page 37.

M1 M2

VDD grid



Figure 2-8 Transistor Currents on VDD

The dominant current in a transistor is IDS, the current flowing into the drain through the transistor and out the source. In a p-type transistor, this current is typically negative. A number of other currents are present in transistor operation as well. In power-grid analysis, you are interested not only in IDS but also in the total currents flowing from and to the power grid: IS and IB. The total power current is the sum of these currents over all transistors:

The negative sign in the equation is a sign convention on element currents.

■ IS is the sum of several currents in the transistor: IS = -IDS + ICSG + ISB. IS is normally positive but can be negative under certain operating conditions.

❑ ICSG is the current charging the transistor capacitance, CSG.

❑ ISB is the junction current (including capacitive) between the source and the bulk.

ICSG might be significant in transient analysis, but ISB is negligible compared to IDS and ICSG.

■ IB is also the sum of several currents: IB = -ISB -IDB + ICBG. IB is several orders of magnitude less than the peak IS current.

❑ ICBG is the current charging the transistor capacitance, CBG.

❑ ISB and IDB are junction currents.

IB contributes to the total power dissipation for chips over a million transistors in size, but it is not a primary cause of IR drop. In addition, the bulk current flows into either a well or the substrate of the chip and therefore usually introduces its load to the power grid in a location away from the transistor. For these reasons, VoltageStorm considers only IS in power-grid analysis, although it also computes IB during netlist simulation.

+-B

D

G

S

VDD

IB

IDS

IS IVDD

VVDD

IVDD IS IB+( )∑–=

Transistors



Validation of VoltageStorm Currents

If you want to validate currents computed in Thunder, the netlist analysis tool used in VoltageStorm, you must remember that Thunder passes IS currents to power-grid analysis but also includes IB currents in IVDD reports. If you want the sum of the IS currents to match IVDD, you can modify the netlist to connect all transistor bulk nodes to a voltage source other than VDD, as illustrated in Figure 2-9 on page 38. In this case, a new power source called VDD2 is created, and a simple edit of the transistor cards in the netlist completes the modification. The resulting netlist is suitable for validating currents by using tools such as HSPICE.

Figure 2-9 Removing Transistor Bulk Currents from VDD

Static and Dynamic Power-Grid Analysis

This section compares static and dynamic analysis in VoltageStorm and shows you how static analysis can find problems in the power grid. When used effectively and interpreted properly, static analysis in VoltageStorm can find even data-dependent power-grid problems.

Static Analysis

You perform static power-grid analysis when the analysis of a power grid is based on steady-state current modeling of the tap currents. It is easiest to view these currents as average current for each transistor obtained over a long simulation run. If you simulate your chip with thousands of test vectors and track the average current through each transistor connected to VDD, you obtain a long-term average behavior of the VDD distribution network in power-grid analysis. This method is an excellent qualitative analysis of the power grid for IR drop and the best way to perform electromigration analysis.

The challenge in static power-grid analysis is obtaining sufficiently representative tap currents in minimal processing time. An important lesson learned through experience is that

+-

+-

B

D

G

S

VVDD

VDD

VDD2

VVDD2

IS

IB



meaningful results are obtained in static analysis, even if the currents applied are not precise. The goal of static power-grid analysis is to find weak spots in the power distribution network, not necessarily to compute the exact IR drop to the nearest millivolt. The most common significant power-grid problems stand out in static analysis, even if the tap currents applied are rough guesses of actual average currents. Knowing the chip well reduces the probability of missing problems. But you do not need to know how the chip operates; in many cases, you may actually learn the behavior of the chip’s power grid from the power-grid analysis.

To illustrate, consider a chip in which one row of cells is only connected on one end when it should be connected on both. The result is that the IR drop at one end of the row is much larger than in all other rows in the chip. Even if the total power distribution of the chip is unknown, a specific row standing out above the others is a strong indication of a weak spot.

As another example, consider a set of drivers of a long bus, all powered from a specific location on the power grid. In this case, an IR drop failure may be data dependent. However, in static power-grid analysis, each driver is modeled by a larger current because of either the larger loading on the driver or the larger transistors in the driver. These larger currents in static analysis highlight the weak spot without requiring you to simulate the specific vector to activate all drivers at once. You can still find problems without performing a significant amount of simulation.

VoltageStorm enables you to provide current scaling information to static analysis when you have it or when it is easily derived from the circuit. For example, memory cells have substantially lower activity levels than other circuitry. Mechanisms are therefore available to make sure these regions have very low average current values. These mechanisms are discussed in Chapter 4, “Using VoltageStorm.”

Static analysis is the standard method used to perform electromigration analysis on power grids, because power grids generally have unidirectional current flow, and electromigration is a function of average current. Electromigration analysis prohibits the application of power-grid reduction in extraction. Reduction techniques mathematically remove the physical characteristics of wires. This physical data is an input requirement for electromigration analysis.

Average currents assume equal amounts of rising and falling transitions on nets, so you can ignore currents due to Miller capacitances in transistors. These currents are considered, however, in dynamic analysis.

The most significant advantage of static power-grid analysis is that the requirements for extraction and netlist analysis are much lower, so you can rapidly perform static power-grid analysis. As a result, many design methodologies today require a chip to pass static power-grid analysis before tapeout, a process called power-grid signoff (PGS). You can apply more extensive dynamic analysis while waiting for the chip to return if your schedule does not



permit it before tapeout. Cadence recommends that you always begin with static analysis before proceeding to dynamic analysis.

Dynamic Analysis

Dynamic power-grid analysis uses simulation vectors to stimulate your chip to obtain a finer resolution of your chip’s behavior. While static analysis is quite effective in finding weak spots in the power grid, you may want to go to the next level of depth in analyzing your grid. Dynamic analysis helps differentiate between false warnings caused by the temporal variation of currents. If the weak spots identified in static analysis do not have an obvious power-grid implementation cause, dynamic analysis can help you understand your chip’s behavior better.

A difference that static analysis cannot distinguish is shown in Figure 2-10 on page 40 and Figure 2-11 on page 41.

Figure 2-10 Synchronized Transistor Currents

Transistor current

TimeClock cycle

M1

M2

M3

M4

M5

M6

0



Figure 2-11 Asynchronized Transistor Currents

Each figure shows current waveforms for transistors M1-M6 over a clock cycle. Each transistor has the same current pulse. The difference between Figure 2-10 on page 40 and Figure 2-11 on page 41 is in the timing of the pulses. In Figure 2-10 on page 40, all pulses occur at once, and in Figure 2-11 on page 41, they are spread out over the clock cycle. Both sets of current waveforms yield the same average currents for all transistors. Depending on the specific characteristics of your chip design, the case shown in Figure 2-10 on page 40 could yield a false pass in static analysis but show excessive IR drop in dynamic analysis.

You are likely to use dynamic analysis for one or more of four specific purposes:

■ To simulate a specific test vector

■ To identify which specific test vector activated an implementation weakness

■ To examine the time correlation of tap currents

■ To obtain a better estimate of the realistic magnitude of IR drop

TimeClock cycle

0

Transistor current

M1

M2

M3

M4

M5

M6



The simulation of a specific test vector is common in memory design to test power-grid behavior under specific corner cases. It is also used when worst-case IR drop test vectors are known before analysis. Simulation to identify which specific test vector activates a weakness is useful when you cannot change your power grid, but you can change your power profile by changing the vectors using microcode. Examining time correlation of tap currents is a valuable check to avoid the static averaging issue just discussed. A better estimate of the magnitude of IR drop is used when the cost of fixing a weak spot is high and you want a more precise analysis before making the decision to fix the problem or not.

Note: Cadence recommends that you always begin with static analysis before proceeding to dynamic analysis—it can be a fast path to finding problems. In addition, if you have little experience with power-grid analysis, static analysis is the better platform for learning the value that can be obtained from power-grid analysis.

Dynamic power-grid analysis is a type of transient analysis. Transient analysis assumes the application of automatic time-step control. However, performing full-chip netlist and power-grid analysis requires many resources. Automatic time-step control tends to create time steps too small for practical use in power-grid analysis. It is used in netlist analysis, but not in power-grid analysis. You can manually control the step size used in power-grid analysis by setting parameters in the command files.

Static Power-Grid Analysis Methodologies

You can perform static power-grid analysis in a variety of ways. The way that you choose depends on the amount of information that you have about the operation of your design and the amount of time that you are willing to take. This section introduces the types of data that may be required in static analysis and surveys several basic methodologies. Advanced methodologies are discussed in “Advanced Power-Grid Analysis Methodologies” on page 52.

Minimum Static Power-Grid Requirements

Static power-grid analysis requires a minimum of three pieces of information: a netlist of your chip, transistor modeling information, and a power grid of your chip. It is assumed that you know the name of the power wires extracted from your chip. These are often labeled VDD and VSS, but if you use different names, substitute VDD and VSS for those names in the discussion here.

Your chip netlist must be a transistor netlist. Chapter 3, “Preparing to Use VoltageStorm,” shows you how to obtain this netlist from Fire & Ice, a Cadence extraction product. See Appendix B, “Preparing to Use VoltageStorm Using QRC” for a flow using QRC rather than Fire & Ice. The QRC interface provides the ability to model small geometries (90nm, 65 nm ...) accurately. To create a complete input circuit netlist for VoltageStorm, combine the transistor netlist with voltage source definitions for at least VDD and VSS. If you do not identify



the power supplies, the tap current data cannot be created. You must define additional voltage sources if your chip has additional power inputs. In addition to the voltage sources, you must include data for transistor modeling in the circuit netlist. You should also create voltage sources for the signal inputs to your chip in the circuit netlist. Do not define them as DC sources; it is best to define them as piecewise linear input sources with a single initial voltage. If you are going to apply vector-based simulation, the data in the vector file overrides the piecewise linear data.

For static power-grid analysis, the power grid extracted from the chip must only contain resistances. In steady-state analysis, inductances and capacitances are treated as shorts and opens, respectively, so extraction time is reduced by extracting only resistances for the power grids being analyzed. If you intend to analyze both VDD and VSS, extract them individually; do not extract both into a single power-grid database.

It is assumed that you know where the power pins are located on the power grid. Voltage sources are defined in the power-grid analysis tool at these locations. A different voltage source is defined for each pad and can include a series resistance and inductance. Different sources are used because each has different behavior resulting from the characteristics of the power grid in operation.

As mentioned earlier, the passing of tap current data from netlist analysis to power-grid analysis uses transistor names as the identification. It is therefore critical that transistor names be consistent between the netlist and the power grid. If the netlist is extracted from the same extractor that extracts the power grid, the correlation should already be in place.

For minimal power-grid analysis, neither net names nor transistor names need to match any schematic that you may have. Schematic net names are only required if you supply activity data or vectors.

Accura Static Analysis Technology

One of the challenges in static power-grid analysis is to obtain an estimate of the distribution of the power consumption in the chip. The Accura static analysis technology is a new approach based on transistor sizes and activity rates that uses circuit recognition, analysis techniques, and any additional information available to estimate the distribution of power consumption in the chip. The techniques applied in Accura are proprietary, but they use various forms of data to derive the distribution of power consumption of the chip.

The input to Accura requires a default chip frequency and the following optional information:

■ Specific clock inputs and the clock frequency. This information is used to trace the clock domains in the design. Any portion of the design not assigned to a specific domain is assigned the default chip frequency. The gates on the clock distribution network are



modeled as operating at the specified clock frequency. Accura derives an activity rate for logic not on the clock tree but in the clock domain.

■ Specific activity rates or frequencies of specific nets in the design. This information is used to set known activity rates of specific nets in the design. It is propagated forward and backward, considering the logic functionality to improve estimations of activity rates of nearby logic.

■ Power consumption of specific blocks in the design. When the actual power consumption of a specific block is known, this number is used to automatically scale the distribution of currents in the block so that the total estimate power consumption of the block is as specified.

■ Power consumption of the entire design. Once various portions of the design are processed to estimate their power distribution, this value is used to scale the currents in the design to the specified level.

The information provided guides the Accura technology in estimating the power consumption of the gates in the design. Accura’s output is a distribution of currents for the transistors in the design. It is a good prediction of power distribution in the design; however, it should not be used for power consumption analysis.

Static Power-Grid Analysis Using Maximum Saturation Currents

This high-level flow is shown in Figure 2-5 on page 34. It is the fastest way to observe power-grid behavior. No capacitance or vectors are required, so the turnaround time is that of connectivity and resistance extraction. To use this flow, you should have an estimate of total power dissipation of the design in the form of average current. Additional information about block power consumption also improves the quality of the analysis.

A simple command computes the peak saturation current, IDS, for each transistor connected to the power grid, where IS in Figure 2-8 on page 37 is -IDS. This current is placed in the tap current file. Of course, parameters to scale the VGS and VDS voltages are applied to compute the saturation current, as well as a variable to scale the resulting current. In addition, certain transistor configurations result in no IDS current because transistors with shorted source and drain or gates turned off have no current.

As mentioned earlier, although saturation currents may seem to be an inaccurate method for deriving average currents, they have been quite successful in finding weaknesses in power grids. Scaling saturation currents by 0.01 for digital logic is a good approximation of averaging the transistor current. Because you can perform this scaling in either netlist analysis or power-grid analysis, there is no harm in generating the tap currents without scaling. In addition, power-grid analysis permits additional scaling by geometric region, so you can scale



memories further in power-grid analysis. If you know the specific power dissipation of your blocks or chip, you can scale the currents accordingly.

Static Power-Grid Analysis Using Net Activity Data

The flow for static power-grid analysis using net activity data is illustrated in Figure 2-12 on page 45. Use this flow when the gate-level simulator reports relative gate activities that you want to use in static analysis. The clock is defined as having an activity ratio of 1.0. This data is used in conjunction with net capacitance, VDD voltage, and chip frequency (F) to derive the average currents of transistors connected to the power grid.

Figure 2-12 Static Power-Grid Analysis Using Net Activity Data

Given these parameters, the average current consumed by a gate is derived from the following equation:

where A is the activity ratio of the gate, and CGATE is the total capacitance of the nets in the gate, including loading.

IAVG A CGATE× VDD× F×=



This equation for average current is derived simply by considering the charge, Q, required to charge the outputs of the gate in a clock cycle interval (1/AF). If a gate has multiple transistors connected to VDD, the average current is split evenly among the transistors. This derivation of average current is not a function of transistor size.

Computing tap current on the basis of activity introduces two additional requirements for extraction: parasitic capacitances must now be computed for signal nets, and backannotation of net names is required.

Static Power-Grid Analysis Using Vector-Based Netlist Analysis

You can also derive average transistor currents by performing vector-based simulation in netlist analysis, as shown in Figure 2-13 on page 46. Use this flow when you want to obtain more accurate average power-grid currents by using the transistor-level simulation of several vectors. This approach is most commonly used at the block level for electromigration analysis. You can tally the average currents at the same time as dynamic analysis, as described in “Basic Dynamic Power-Grid Analysis Methodologies” on page 47.

Figure 2-13 Static Power-Grid Analysis Using Average Currents Tallied in Vector Netlist Analysis



VoltageStorm accepts VCD input vectors as well as several other formats. It performs simulation over the vectors provided and tracks the tap currents. It tracks average, peak, and RMS currents at once and reports them in three separate tap current files. Each type of tap current data provides a different perspective of simulation behavior, allowing you to select which form best suits your needs.

Computing the average tap current on the basis of vector simulation introduces one additional requirement for extraction: parasitic capacitances should now be computed for signal nets.

If the vector input signals are not labeled in the GDSII input, you must backannotate signal names to the netlist in the extraction portion of the flow.

Basic Dynamic Power-Grid Analysis Methodologies

Dynamic analysis is the next step up in complexity from static analysis using vector-based analysis. The flow diagram in Figure 2-14 on page 48 shows its similarity to vector-based static analysis. The difference appears to be only in the tap currents, but there are other differences. Use this flow when you want to introduce the time variation of currents into your analysis, as discussed in “Dynamic Analysis” on page 40. Rather than averaging currents, this flow enables you to see the finer time variation of currents over a clock cycle.



Figure 2-14 Dynamic Power-Grid Analysis

The challenge in dynamic power-grid analysis is to find the weaknesses in the power grid by using the minimal amount of computation time. To this end, dynamic analysis also includes capabilities for a form of vector compression in the creation of the dynamic tap current data. The vector compression is intended to create an effective worst-case IR drop test vector by merging the behavior of many vectors into a single equivalent. This process is further described in “Vector Compression” on page 49.

Dynamic Power-Grid Analysis Requirements

Dynamic power-grid analysis introduces two additional requirements for extraction beyond those of static analysis: parasitic capacitances must be computed for both signal nets and power nets, then merged into the power grid for analysis. In addition, if the vector input signals are not labeled in the GDSII input, you must backannotate signal names to the netlist in the extraction portion of the flow.

Because dynamic analysis is applied to the power grid, VoltageStorm automatically accounts for a portion of the algorithm. Capacitance on the power grid is due to two sources: parasitic capacitances and transistor capacitances. Parasitic capacitances are provided in the extraction step. Transistor capacitances are automatically encoded in the dynamic tap current



files. These transistor capacitances include transistors that implement decoupling capacitances, as shown in Figure 2-15 on page 49.

Figure 2-15 Mapping of Decoupling Capacitances

Dynamic Power-Grid Analysis

The flow diagram in Figure 2-14 on page 48 shows the dynamic analysis flow. Power-grid analysis processes the dynamic current data as piecewise constant current sources. The step size is determined by the commands in the netlist analysis step. The recommended step size is about a single gate delay. Many designers use one tenth of the clock cycle as their step, so if your clock cycle is 10 ns, use 1 ns as your step size. If you intend to model pin inductance, a smaller step size is required, such as one twentieth of the clock cycle.

Power-grid solutions are performed by constructing and solving matrix problems. The size of the matrix describing the resistive connectivity of a chip’s VDD can be very large. In a three-metal layer process, the number of resistors in VDD may be one to two times the number of transistors in the circuit. In a four- to five-metal layer process, the ratio increases to four to five. A 2-million-transistor chip normally has about 4 million resistors in VDD. An 8-million-transistor chip may have 50 million resistors in VDD. The matrix to solve in power-grid analysis is therefore very large.

Cadence strongly recommends using vector compression, if possible, because the time to solve a large matrix for each of a large number of time points can be very long.

Vector Compression

The vector compression available in VoltageStorm is a complex process that was developed in conjunction with microprocessor designers to optimize the number of power-grid matrix solves required in full-chip dynamic analysis. If you simulate your chip for 100 vectors and select 10 steps per clock cycle in dynamic analysis, you will perform 1,000 solves of the power grid, which might not be practical. Vector compression reduces the number of solves to 10. Use it if your objective is to resolve the temporal issues of static analysis or to estimate the

VDDVDD

VSS

VSS



magnitude of worst-case IR drop more precisely. You should not use vector compression if your objective is to simulate a specific vector or to find the specific vector with the worst-case IR drop.

Two concepts form the basis of vector compression.

■ First, dynamic analysis introduces time correlation to the analysis data. Chips are synchronous in their behavior, with the clock being the synchronization signal. Introducing temporal correlation in dynamic analysis splits activity occurring at different portions in the clock cycle rather than modeling the clock cycle as a single time-averaged value. The key is to improve resolution within a clock cycle, not across many clock cycles (vectors).

For example, assume that you split a 10-ns clock cycle into 10 buckets of 1 ns each, B1-B10. B1 corresponds to the interval 0.0–1.0 ns into the clock cycle, B2 to the interval 1.0 ns–2.0 ns, and so on. If gate G1 can only switch in the time interval corresponding to bucket B2, in dynamic analysis the current value for gate G1 in buckets B1and B3–B10 should be 0.0 A in all clock cycles. The current value in bucket B2 may be 0.0 A in some clock cycles and non-zero in others. Figure 2-16 on page 50 illustrates the current for gate G1 over a clock cycle.

Figure 2-16 Current Waveform in 10 Buckets of a Single Vector for Gate G1

Over 100 vectors, 1,000 total buckets correspond to gate G1. The 1,000 buckets correspond to 100 vectors and B1–B10 offsets into each vector. The following table shows the breakdown of sample average currents in gate G1 for each of the 1,000 buckets over 100 vectors.

Vector B1 B2 B3 B4 B5 B6 ... B10

Gate G1 power current

Clock cycle

TimeB1 B2 B3 B4 B5 B6 B7 B8 B9 B10

G1



1 0 1.0 mA 0 0

2 0 0 0 0

3 0 2.1 mA 0 0

4 0 0.1 mA 0 0

5 0 0 0 0

6 0 0 0 0

.....

.....

.....

100 0 1.0 mA 0 0

■ The second concept in vector compression is that of peak analysis, with a goal of finding the worst-case current. When simulating to determine the peak current of a transistor, you examine the transistor current at each time point and take the maximum value found.

Merging the two concepts, you want to find the worst-case set of current buckets for gate G1 to create a current waveform for a single worst-case clock cycle. You want to find the peak over many vectors, but you want to preserve the time offsets, or buckets, in clock cycles. To do this, you merge, or compress, the data in the table down the columns to create a single row of buckets that contain the peak value of the 100 values in that column. The worst case in this peak-of-average compression is 0.0 A in buckets B1 and B3-B10 and 2.1 μA in bucket B2. In this case, the worst-case current in bucket B2 occurs in vector 3. If gate G1 were to have activity in any other bucket for any vector, the corresponding bucket in the compressed vector would be non-zero.

This technique derives a worst-case current waveform for each tap current as assembled over many vectors. The resulting current waveform may be unrealistic, but you can use it to meet the goal of finding weak spots in the power grid that might be sensitized in dynamic simulation. The dynamic power-grid analysis now uses 10 matrix solves on the compressed vector rather than 1,000 on the entire data set. These 10 matrix solves are 10 potential worst-case or overly pessimistic situations that might occur in your power grid.

The total current over all taps in the compressed vector is greater than the overall total VDD current in Figure 2-9 on page 38 because of the application of peak operation during compression. VoltageStorm supports a variety of compressions. When tallying currents into buckets, you can compute the current in each bucket as either the average, peak, or RMS current of the waveform that the tap exhibits over the time interval corresponding to the bucket. In addition, when performing the compression, you can either take the peak over the vectors or average the measures over the vectors. If you tally the average current in each bucket for gate G1, and you compress the vectors using the average operation (average-of-average compression), the result should be the overall average current of gate G1 in transient simulation.



This processing independently takes place for each tap on the power grid. So if your VDD power grid has 1 million transistors, you will have 1 million sets of buckets. Each bucket set is the compression over all your test vectors.

Exercise care when performing vector compression on certain mutually exclusive circuits, such as memories, multiplexers, shifters, and register banks. Word select lines, which are a standard type of signal in memory designs, are designed to operate exclusively; only one ever operates at a time. By its nature, vector compression using the peak over all vectors causes all word lines to be activated at once, resulting in false warnings. For these circuits, you should use the average method to compress the vectors.

Vector compression tries to synthesize a worst-case IR drop test vector. How many vectors are required to obtain a sufficient amount of data? The answer is a function of your chip and the vectors that you apply. You can obtain high-quality results from as few as one vector, because the clock is a primary source of power consumption and IR drop, and simulating a single vector gives you insight into the performance of your power grid.

If you are concerned that vector compression significantly overestimates the power-grid currents, remember that you can use either peak or average currents within each bucket or in the compression across vectors. If you want to compress vectors by using the peak operation, you can increase the number of buckets per clock cycle from 10 to 20 to further increase the time quantization and to minimize overestimation.

Advanced Power-Grid Analysis Methodologies

The following methodologies are classified here as advanced because they increase the complexity of those discussed previously. You should attempt them only after successfully implementing earlier methodologies.

Static Power-Grid Analysis with Feedback

As noted earlier, VoltageStorm can feed back the results of power-grid analysis to the netlist analysis, as shown for vector-based static analysis in Figure 2-17 on page 53. Use this flow in vector-based netlist analysis when you want to examine the worst-case impact of IR drop on the performance of the transistors.



Figure 2-17 Static Power-Grid Analysis with Feedback to Netlist Analysis

Power-grid analysis creates an IR drop report that contains the voltage computed after static power-grid analysis. As with the tap current file, the identification used to pass data back is the name of the transistor tap. You can repeat the netlist analysis by using the unique voltage for each transistor connected to the power grid.

The impact of this feedback is that tap currents computed again will have a smaller magnitude than in the first pass, because the lower power-grid voltages reduce the voltage swing of the gates. The gate speed should also be slower, but the gate speed should not have much impact on average currents unless the functionality is altered.

In examining the results of two passes through the loop, you observe both the worst-case and best-case IR drop results. In the first pass, you observe the worst-case IR drop, because the interaction of the netlist and the power grid has not reduced the currents. In the second pass, you observe the optimistic IR drop, because the worst-case IR drop feedback to netlist analysis has reduced all tap currents by the maximum amount.



Dynamic Power-Grid Analysis with Feedback

The next progression after static analysis with feedback is dynamic analysis with feedback, as shown in Figure 2-18 on page 54. Use this flow to examine the dynamic behavior of the power grid in netlist analysis. Time-varying power-grid voltages alter the speed of transistors to obtain the most accurate performance estimate of your design.

Figure 2-18 Dynamic Power-Grid Analysis with Feedback to Netlist Analysis

In this methodology, dynamic IR drop data is fed back to the netlist analysis. The waveforms applied to each tap transistor are now dynamic rather than static. Once again, although this feedback can be used in power-grid analysis, its value is highest when used in conjunction with ClockStorm, where the objective of the analysis is circuit performance.



Dynamic Power-Grid Analysis Without Vector Compression

In some situations, you may want to perform power-grid analysis for each clock cycle, avoiding vector compression altogether. In addition, you may want to perform power-grid analysis on a single vector in isolation. This cycle-by-cycle flow is sometimes used in mutually exclusive circuits such as memories. This flow is useful when you have many VoltageStorm licenses and want to split the power-grid analysis into several pieces so that you can use a number of machines to simulate in parallel. This method is based on the assumption that the power-grid IR drops of the different vectors do not interact.

As shown in Figure 2-19 on page 56, a set of currents is generated for each cycle and independently analyzed on the power grid. Simulate only a small number of cycles to avoid a large number of time points to be solved over a potentially large matrix.



Figure 2-19 Dynamic Cycle-by-Cycle Power-Grid Analysis

Block-by-Block Power-Grid Macromodels Feeding Full-Chip Power-Grid Analysis

The final advanced flow is used by microprocessor designers seeking to optimize the performance of full-chip power-grid analysis after performing power-grid analysis on each block in the design. This flow is based on certain assumptions that you must validate before analyzing your design. This flow assumes that you have at least five metal layers in your design and that the lowest-level power grid (metal1 and metal2) is contained in a block; adjacent block power grids do not connect in metal1 or metal2. In this flow, a macromodel of a block is created by monitoring the currents at a via layer— VIA1, for example—in the design. These currents are used as a macromodel for the block in full-chip analysis.



At the full-chip level, the power grid is extracted only down to the via layer used to create the macromodels (VIA1). Full-chip analysis is then performed on the metal layers above the macromodel layer (VIA1). The smaller full-chip power grid makes solves faster and, ultimately, dynamic analysis of the full chip more practical. This flow is shown in Figure 2-20 on page 57.

Figure 2-20 Hierarchical Power-Grid Analysis Using Macromodels

This flow has more flexibility than the block-by-block analysis previously described, because you can move and reuse block macromodels. If a megacell occurs twice in the design, you can create the macromodel once and use that data twice.



If you use dynamic analysis in this flow, the step size used in each block in dynamic analysis must be the same. A limitation of this flow is that IR drop feedback is no longer possible. Cadence recommends that you work closely with its applications engineers if you plan to use this flow.

Correcting IR Drop and Electromigration

The best solution to a given IR drop problem depends on the type of IR drop, the chip architecture, the chip layout, and the functionality. The following approaches have been used successfully:

■ Widen metal lines.

■ Add or remove straps to redirect the current.

■ Stagger the switching of large devices.

■ Reduce the number of buffer sites.

■ Add decoupling capacitors to the design.

■ Use solder-bump technology.

■ Add more VDD pads to the design.

■ Connect buffers to different power buses.



3Preparing to Use VoltageStorm

This chapter describes how to generate the data required to run VoltageStorm. It uses a SPARC processor core design in GDSII format to illustrate the data preparation. This design is located in the tutorial/release_version/sparcdsp directory of the Cadence installation.

Note: The tutorial in this chapter does not include the dynamic analysis flow using UltraSim. However, you can adapt the steps given here by referring to “Performing Dynamic Netlist Analysis with UltraSim” on page 127.

Required Data

Because VoltageStorm offers a variety of power-grid analysis methodologies, the exact list of inputs required depends on the specific methodology that you use. If you are a beginner, start with the simplest method to become familiar with VoltageStorm’s operation. As you learn more about its capabilities and the ways that it can help you find power-grid problems, you can venture into the more sophisticated methodologies.

All power-grid analysis methodologies require three specific data sets:

■ A design circuit file—for example, sparcdsp.ckt—that defines the input sources to be used for the analysis

■ The extracted power-grid resistance network to be analyzed

■ Model data with which to compute transistor currents

These three data sets are shown in Figure 3-1 on page 60.

More advanced flows require the computation of signal and power-grid capacitances. Some flows also require the creation of node name match files or transistor name match files. The most complex preparation flow for VoltageStorm is shown in Figure 3-2 on page 61.


VoltageStorm Transistor-Level Rail Analysis User GuidePreparing to Use VoltageStorm

Figure 3-1 Minimum Extraction Required for Static Power-Grid Analysis



Figure 3-2 Maximum Extraction Required for Dynamic Power-Grid Analysis

Dracula/Calibre/

other



In this chapter, you step through the flow shown in Figure 3-1 on page 60, followed by the addition of capacitance computation for dynamic analysis, and completed by following the flow shown in Figure 3-3 on page 63. The results of this data preparation are used in Chapter 4, “Using VoltageStorm.” In addition to the tutorial data provided for this exercise, the Cadence installation also includes some flow scripts to help in the extraction portion of the flows. These scripts are used primarily in extraction-for-timing analysis flows, but you can use them here as well.

Transistor Circuit File

The transistor circuit file is a SPICE-like netlist consisting mostly of the transistor netlist created by XTC. The XTC transistor netlist is in SPICE format, so you can submit it to several simulators. Ideally, this netlist is in hierarchical form, although you can also use a flat netlist. For more information on XTC, see the Data Preparation Manual. In addition to the transistors extracted by XTC, the circuit file contains voltage source definitions for power sources and primary circuit inputs, as well as lines pointing to transistor modeling information. Tools such as SPICE also require this information, although in a format different from that required by Cadence analysis. The exact contents of the circuit file vary, depending on the specific flow that you are executing. As you move to more complex flows, add additional lines to the circuit file, or change the names of files. When the netlist is analyzed, an output file is created that uses the transistor name to identify the tap current sources in a power-grid analysis.

Power-Grid Resistance Network

The power-grid resistance network is the R or RC power-grid database output of Fire and MergeNet. The netlist is in binary form to minimize disk usage and to improve the efficiency of the data parsing. Power grid capacitance data is added to the database only if you need it for dynamic power-grid analysis. If the database contains power grid capacitance data, this data is ignored during static power-grid analysis.

Ice computes the capacitance data for both power and signal nets. DistRC merges this data into the Fire database. Because power grids span the entire chip, capacitance extraction for the purpose of analyzing power grids effectively performs extraction of the entire chip. Capacitance data is required only if you request dynamic analysis for either netlist analysis or power-grid analysis. If capacitance data is not required, avoid performing this step, because it is the most resource-consuming step in the flow.


../dataprep/titlecopy.html#firstpage


Transistor Model Data

Transistor model data is output by Tablegen. It consists of tabular data of transistor currents and capacitances for many bias conditions. VoltageStorm uses this data to compute transistor currents in transistor netlist analysis and simulation.

Directory Structure

Cadence recommends that you use a common directory structure when you use its extraction and analysis tools to run different flows. This directory structure, used by the Cadence flow scripts, prevents any confusion that may arise from running several tools in a single directory. Figure 3-3 shows the recommended directory structure for the sample sparcdp design used in this chapter.

Figure 3-3 Typical Design Directory Structure in Using VoltageStorm

In this directory structure, the directories perform the following functions:

■ The data directory stores the source data for the design being run.

top level

datasimp_template SPARCDSP

flat

thunder lightningicexticm firePOWER

stripes

tablemodels static staticdynamic dynamic

moviedir



■ The simp_template directory contains the template for the directory structure, as well as files used to run the flow scripts. Flow scripts use this template area for details on how tools should be applied to designs.

■ The SPARCDSP and flat subdirectories store the specific data created in the execution of the flows in this chapter as well as those in Chapter 4, “Using VoltageStorm.”

■ The icm directory stores the technology files used by Fire and Ice.

■ The xt directory is where XTC processes the GDSII layout to produce stripes and the transistor netlist.

■ The stripes subdirectory stores the partitioned data for Fire and Ice.

■ The firePOWER directory is where Fire extracts the power-grid resistance, whether using a single processor or parallel processors.

■ The ice directory is where Ice extracts the capacitance, whether using a single processor or parallel processors.

■ The thunder directory is where Thunder or UltraSim analyzes the transistor netlist. The static and dynamic subdirectories separate the runs for different flows because the circuit files are different for each case.

■ The tablemodels directory is where Tablegen stores tabular data for device models.

■ The lightning directory is where Lightning analyzes the power grid. The static and dynamic subdirectories separate the different data between static and dynamic flows because static flows do not require capacitance data in the power grid. If you create a power grid for dynamic analysis, this grid can also be used for static analysis.

Preparing to Run Flows

You must perform a number of steps, including defining the environment variables and creating the technology files for flows, before running the flows in this chapter and those in Chapter 4, “Using VoltageStorm.” However, you must only perform them once.

The steps begin with the tutorial directory shown at the top of the directory structure described in Figure 3-3 on page 63. This procedure assumes that you have already added the location of the Cadence bin directory to your path variable.

1. Create two environment variables: one to identify the location of the Cadence toolbox and one to identify the version of the flow scripts that you want to run. Next, you must add the toolbox bin directory to your path.

Note: These instructions assume that the Cadence installation is in /users/simplex;



if you use another directory, make the appropriate changes.

Type the following:

shell> setenv SIMPLEX_TOOLBOX_H /users/simplex/toolbox

shell> setenv SIMPLEX_TOOLBOX_V 3.1.0

shell> set path = ($path $SIMPLEX_TOOLBOX_H/bin)

You may want to add these settings to your shell .cshrc file.

2. Change to a suitable directory, and create a subdirectory named data to hold the tutorial design data:

shell> mkdir data

3. Copy the tutorial data files to this data directory:

shell> cp $SIMPLEX_HOME/tutorial/3.1.1/sparcdsp/* data

4. Run a flow script to create the simp_template directory structure:

shell> genSIMP_TEMPLATE

This sequence of steps generates the simp_template directory and a number of subdirectories. The data in this directory tree is used as templates for flow scripts. Initializing the appropriate files makes running flow scripts for extraction easier.

5. Create the technology files in the template directories. You can find instructions for creating the technology files in the Data Preparation Manual. Once you have created technology files for your process, use them until your process changes. Sample files are provided for the tutorial. Type the following:

shell> cp data/icecaps.tch simp_template/icm

6. Now you must set up the hosts file to permit the flows to use multiple processors in case your installation does not use LSF for parallel processing. Enter the following:

shell> cd simp_template/ice

shell> cp samplehosts hosts

shell> vi hosts

Place the names of several of the machines that you want to use in parallel processing in the hosts file and then exit the editor.

7. Return to the top-level tutorial directory:

shell> cd ../../

Setting Up the XTC Command File

The next step is to set up the XTC command file templates for the flow scripts. The simp_template/xt directory includes several sample templates for various types of flows.




The template that applies to this tutorial is SAMPLE_xt.cmd_flat_gds_analysis. You would normally copy this file to the xt.cmd file and edit it. The most important fields are the settings of the GDS layer maps, which tell XTC how to map data from your GDSII file to the layers of the design. The tutorial includes the edited XTC command file for the sparcdsp design. You can find additional information on the XTC command files in the Data Preparation Manual.

Type this command:

shell> cp data/xt.cmd simp_template/xt

You are now ready to extract the data for the flows in the next section.

Generating Basic Static Analysis Data

This section takes you through the generation of data for static analysis in VoltageStorm, as shown in Figure 3-1 on page 60. It assumes that you have completed the steps in “Preparing to Run Flows” on page 64. After you have completed the instructions in this section, you can begin the tutorial in Chapter 4, “Using VoltageStorm.” You can also continue to the next section to create capacitance data for static or dynamic analysis.

1. To begin the extraction flow, you must first run XTC to extract connectivity in the netlist and generate stripes for resistance and capacitance extraction. You should be in the tutorial directory of the structure shown in Figure 3-3 on page 63. Type the following:

shell> genXT -src gds -g data/sparcdsp.sf -l data/SPARCDSP.labels SPARCDSP

This command tells the script where the input file is located, where the label file is located, and that the source of the design is GDSII. It also gives instructions to perform the processing in a directory called SPARCDSP, which is created in your current directory. The flow script accesses data in the simp_template directory to run the flow. At the end of the extraction, XTC creates both the flat transistor netlist file called SPARCDSP.net and a directory called stripes in the SPARCDSP/flat/xt directory. The stripe files are inputs to Fire and Ice.

2. Now you run the flow script to have Fire extract the power-grid resistances from the stripe database. The flow script is recommended so you can use several machines for extraction. After extracting the power grid, you can convert the data into the format required by Lightning. Type this command:

shell> genFIRE_EXT -P -n VDD SPARCDSP

The -P option tells the script that a power grid is being extracted, so the results should be placed in the firePOWER directory. The -n VDD option identifies the power grid, VDD, to be extracted. The last option identifies the design to use, SPARCDSP.




3. Because the flow scripts are intended for extraction-for-timing flows, the following tasks are performed without flow scripts. You must create directories for Thunder and Lightning, link to the model tables, and complete the creation of the power-grid database.

To create the directories for Thunder and Lightning, enter these commands:

shell> cd SPARCDSP/flat

shell> mkdir -p thunder/static thunder/dynamic

shell> mkdir -p lightning/static lightning/dynamic

4. Link to the model tables:

shell> cd thunder

shell> ln -s ../../../simp_template/models/thunder tablemodels

The model tables that will be used are generated in “Creating Model Tables” on page 68.

5. Create the power-grid database:

shell> cd ../lightning/static

shell> mergenet -o SPARCDSP_VDD ../../firePOWER/SPARCDSP_VDD_*.hdr

MergeNet converts the Fire database to the power-grid database. All you provide is the desired output base name and the list of Fire header files. The creation of the power-grid database is now complete.

The only additional piece of information that you need is the location of the power pins for power-grid analysis. These locations are required in Chapter 4, “Using VoltageStorm,” when you run Lightning. In Lightning, voltage sources are used to represent the power pins for the grid to be analyzed.

6. Create a command file called vsrc.cmd that contains the Lightning commands used to place voltage sources:

shell> vi vsrc.cmd

7. Add the following lines to the command file:

putvsrc METAL_3 Vsrc1 3.3 24200 1706100




For additional information on the putvsrc command, refer to “putvsrc” in the “Commands” chapter of the Lightning Manual.

8. Return to the top-level tutorial directory:

cd ../../../..


../lightning/text_commands.html#firstpage


../lightning/text_commands.html#putvsrc


Creating Model Tables

Next, you must create the model tables that Thunder uses for analysis. Once you have created the model tables for your process, they are used until your model cards change. The tutorial provides a sample model card file. This procedure assumes that HSPICE is available and in your path. See the Data Preparation Manual for more information about running Tablegen.

1. Type these commands:

shell> cp data/mymodels.models simp_template/models/thunder

shell> cp data/tablegen.cmd simp_template/models/thunder

shell> cd simp_template/models/thunder

shell> tablegen tablegen.cmd

The tablegen.cmd file shows you the typical commands for running Tablegen. It identifies the name of the model card file, how to run HSPICE, and the default VDD voltage for your technology. The generate commands instruct Tablegen to create a number of tables for each model card in the model card file—in this case, N and P. These are the model names created by XTC in this tutorial. Tablegen runs for up to an hour and creates the model tables.

2. Return to the tutorial directory before proceeding:

shell> cd ../../../

Creating the Circuit File for Static Analysis

Next, you complete the creation of the circuit file for Thunder or UltraSim. The circuit file defines power voltage sources. A sample circuit file is included in the data directory for you to copy and use.

Type these commands:

shell> cd SPARCDSP/flat/thunder/static

shell> cp ../../../../data/sparcdsp.ckt .

shell> cp ../../../../data/*.inc .

Input sources and output loads are included. The link to the table models is provided. The circuit file includes three forms of a set of three lines, including the netlist and parasitic capacitance data.

■ The first of these forms is for this static flow.

■ The second form includes capacitances, which are computed in the next section.




■ The third form is for name-backannotated flows, discussed in “Backannotating Net and Device Names” on page 70.

The .coordinate command provides geometric data to Thunder for display.

Return to the tutorial directory:

shell> cd ../../../../

You are now ready to either proceed to Chapter 4, “Using VoltageStorm,” to begin static analysis or continue here to add capacitance data to your flow.

Adding Capacitance Data to the Flow

Note: Follow the steps in this section only if you need capacitance data for static or dynamic analysis. In this tutorial, you should follow them because dynamic analysis will be applied in Chapter 4, “Using VoltageStorm.”

The next step in preparing your circuit for dynamic power-grid analysis is to use Ice to extract the signal nets and power-grid capacitance data using the stripes created by XTC.

1. To run Ice, make sure you are in the tutorial directory where you ran genXT and genFIRE_EXT, and type the following:

shell> genICE SPARCDSP

This command creates the capacitance database in the SPARCDSP/flat/ice directory. The file names of the database begin with SPARCDSP_ and should be numbered from 000 to 068. On many machines, the script uses the hosts file or LSF to extract the capacitance.

2. The next step is to distribute those capacitances on the power grid and to create the final power-grid database with both resistance and capacitance data. To run DistRC, provide the Ice data directory along with the base name of the files. Also, provide the names of all Fire header files. DistRC creates new files with .dist extensions. They annotate the capacitances on power-grid subnodes. Enter the following commands:

shell> cd SPARCDSP/flat/firePOWER

shell> distrc -d ../ice -b SPARCDSP SPARCDSP_VDD_*.hdr

3. Now you run MergeNet to convert the RC data to the power-grid database in the lightning/dynamic directory. Enter these commands:

shell> cd ../lightning/dynamic

shell> mergenet -o SPARCDSP_VDD ../../firePOWER/SPARCDSP_VDD_*.hdr.dist



Creating the Circuit File for Dynamic Analysis

Now you create a file for dynamic analysis. This capacitance data is loaded directly into Thunder. You include this data in the netlist referred to in “Creating the Circuit File for Static Analysis” on page 68 by using the .capdb statement in the circuit file, as shown in the sample file from the tutorial.

1. To create a file for dynamic analysis, type the following commands:

shell> cd ../../thunder/dynamic

shell> cp ../../../../data/sparcdsp.ckt .

shell> cp ../../../../data/*.inc .

shell> vi sparcdsp.ckt

2. Edit the circuit file, commenting out the lines for flows without capacitance and removing the comments from the three lines for flows with capacitance. Thunder is now ready for dynamic analysis.

You are now ready to either proceed to Chapter 4, “Using VoltageStorm,” to begin dynamic analysis or continue here to backannotate the net and device names to your flow.

Return to the tutorial directory:

shell> cd ../../../../

Backannotating Net and Device Names

Note: Follow the steps in this section only if you need backannotated names for static or dynamic analysis. The results require a minor change in the Thunder circuit file, discussed in “Creating the Circuit File for Dynamic Analysis” on page 70.

If the GDSII input file contains text labels for all the power and signal nodes that you need to reference (that is, if the GDSII file is annotated), you are ready to go to the next step in Chapter 4, “Using VoltageStorm.” However, if XTC generated the net names and you plan to perform static activity-based netlist analysis or dynamic analysis, you must at least backannotate the schematic node names to the transistor netlist. To do this, you must create a net name match file that cross-references XTC net names and schematic net names. The match files are used in conjunction with Rain to backannotate schematic names onto the resistance and capacitance databases, as well as onto the transistor netlist.

You can create name match files in a number of ways, including using Dracula® or Calibre®.

For this tutorial, you will need to backannotate the net names.

1. Perform the backannotation by typing the following:

shell> cd SPARCDSP/flat/firePOWER



shell> cp ../../../data/design.nmat .

2. To backannotate the transistor netlist, including the coordinate file data used by Thunder, first create the design.net file:

shell> vi design.net

Add the following lines to this file, and save the file:

.include “../xt/SPARCDSP.net”

.coordinate “../xt/SPARCDSP.coor”

3. Now enter the following:

shell> rain backannotate banode=design.nmat circuit=design.net

Rain backannotates the coordinate file and the circuit file. Rain creates new netlist and coordinate files in the xt directory named SPARCDSP.net.ba and SPARCDSP.coor.ba, respectively.

This same style of backannotation is required for the resistance and capacitance databases.

4. Assuming that you have already distributed the capacitances as instructed in “Adding Capacitance Data to the Flow” on page 69, type the following commands:

shell> rain backannotate banode=design.nmat capdb=../ice SPARCDSP 0 68

shell> rain backannotate banode=design.nmat resdb ../firePOWER/SPARCDSP_*.hdr.dist

The backannotation of the capacitance database creates new files with the .ba extension, as does the resistance backannotation. Always remember to run DistRC, as shown in Adding Capacitance Data to the Flow on page 69, before backannotating the RC database.

5. The next step in preparing for dynamic analysis is to create the final power-grid database with backannotated names. Enter the following:

shell> cd ../lightning/dynamic

shell> mergenet -o SPARCDSP_VDD ../../firePOWER/SPARCDSP_VDD_*.hdr.dist

This new database replaces the one you had in “Adding Capacitance Data to the Flow” on page 69.

Updating the Circuit File for Dynamic Analysis

The final step in dynamic analysis is to modify the circuit file described in “Creating the Circuit File for Dynamic Analysis” on page 70.

1. To do this, edit the circuit file:





2. Comment out the three lines that load the unannotated data, and uncomment the final lines to load the backannotated transistor file, the backannotated coordinate file, and the backannotated capacitance database.

3. Return to the tutorial directory:

shell> cd ../../../../

You are now ready for all the flows described in Chapter 4, “Using VoltageStorm.”



4Using VoltageStorm

This chapter introduces you to the basic procedures involved in using VoltageStorm. It uses a sample circuit called sparcdsp and assumes that you have prepared the data as described in Chapter 3, “Preparing to Use VoltageStorm.”

Overview

This chapter uses a design called sparcdsp to step you through a variety of flows in VoltageStorm. It cannot take you through every possible way of running VoltageStorm, so it focuses on the basic techniques that allow you to obtain the most value from VoltageStorm.

Circuit Netlist File

In “Generating Basic Static Analysis Data” on page 66, you created a circuit file, which defined the following components:

■ The definition of the power sources for the chip, which are critical for Thunder to identify gates and to perform simulation.

■ The definition of the primary input sources of the chip to which input vector files can be applied. These inputs should not be defined as DC sources, because Thunder treats DC voltage sources as power sources to which vectors cannot be applied. If your input voltage is a constant value over a specific simulation, define the source as a piecewise linear (PWL) source with a single voltage.

■ The definition of the output pin loadings of the chip. It is important to model the loading on the chip outputs in both activity-based analysis and vector-based simulation. A common error in analysis and simulation is to forget output pin loading in the circuit file. Thunder can assess the impact of that loading only if you explicitly define it.

■ The definition of the bidirectional pin loadings of the chip. These pin loadings are also important, because they act like outputs during some time intervals. These pins may also have voltages forced by input vector files as well.


VoltageStorm Transistor-Level Rail Analysis User GuideUsing VoltageStorm

■ The link to the transistor modeling data, which tells Thunder how to compute transistor currents and capacitances as a function of voltage. You can refer to several sets of modeling data for different devices or place data for several models into a single directory, as in this tutorial.

■ The link to the transistor netlist and coordinate file. Ideally, this netlist is hierarchical, although you can also use a flat netlist. If you use backannotated net names, device names, or both, you must link to the proper file. The name-backannotated files from “Backannotating Net and Device Names” on page 70 all have an extension of .ba. The coordinate database provides geometric data about the location of devices in the layout. This data is used to create graphical output.

■ The link to the parasitic capacitance database of signal nets. As with the netlist and coordinate database, if you are using a name-backannotated database, the base file name should have a .ba extension.

See the Thunder Reference Manual for more information on creating Thunder circuit files.

Power-Grid Database

The power-grid database contains the resistors (and capacitors for dynamic power-grid signoff) of a single power net in your design. It is common for this database to contain resistive elements numbering two to six times the number of transistors in your design. For example, a 2-million transistor chip may have 4 to 5 million resistors in its VDD power grid. If you extracted them, the power grid would also contain the parasitic capacitances associated with the power net.

You also need the location of the power supplies that you want to model. When analyzing a block of the design, you select a number of locations on the periphery of the block where power will be connected to the block.

To model package characteristics, you can define a series resistance and inductance for power pins in VoltageStorm. Keep in mind, however, that accurate modeling of inductance requires smaller time steps for dynamic analysis.

Tutorial Circuit

As noted earlier, this chapter uses a tutorial circuit that was previously described in Chapter 3, “Preparing to Use VoltageStorm.” This design is included in the release tree of Cadence software in the tutorial/SPARCDSP directory. The extraction portion of the flow, shown in Figure 2-5 on page 34, is required before running VoltageStorm and is provided in Chapter 3, “Preparing to Use VoltageStorm.” The steps required here assume that you have completed


../thunder/titlecopy.html#firstpage


that extraction already. If you have not performed this extraction, you should do so before continuing here.

To begin here, you must complete “Generating Basic Static Analysis Data” on page 66. For dynamic analysis, you must complete at least “Adding Capacitance Data to the Flow” on page 69.

Static Ipeak Power-Grid Analysis

The most basic power-grid analysis flow is the static power-grid analysis based on peak saturation transistor currents. This type of analysis is commonly called ipeak analysis. Because of its simplicity and ability to find problems quickly in power grids, it is the most common VoltageStorm flow used. The analysis flow in this case is shown in Figure 4-1 on page 75. The extraction of the power-grid database and circuit netlist is completed in “Generating Basic Static Analysis Data” on page 66.

Figure 4-1 Static Ipeak Flow



You can easily estimate the average currents throughout the chip by computing the peak saturation currents for all the transistors connected to the power grid, followed by some simple scaling of data. This method assumes that the average current of a transistor in the chip is somehow related to its size. Although this assumption is not strictly true, the results for a large number of transistors connected to the power-grid highlight the problem areas of the power grid, if not their exact voltages. Effectively applying your knowledge of the circuit to this analysis and filtering and displaying data finds most problems in your power grid. Most chip problems found in dynamic analysis exhibit symptoms of those problems in static analysis.

The following section shows you how to compute this data, and “Viewing Analysis Results” on page 80 introduces you to scaling and filtering.

Performing Ipeak Analysis

To perform ipeak analysis, first run Thunder, then Lightning.

Running Thunder

To run Thunder, follow this procedure.

1. In the directory structure for the sparcdsp chip, move to the SPARCDSP/flat/thunder/static directory, where you created the circuit file introduced in “Creating the Circuit File for Static Analysis” on page 68.

shell> cd SPARCDSP/flat/thunder/static

2. Start Thunder:

shell> thunder

The Thunder console window now appears It is the interactive interface to Thunder. It features several menu options along the top. The only one you might use here is the File menu, which contains options for loading a circuit file, running vectors, and exiting Thunder. At this point, you will focus on loading the circuit file.

3. At the Thunder prompt, type the following to load the circuit file:

Thunder> load sparcdsp.ckt

Messages appear in the console window as Thunder processes the circuit. After it completes processing, a plotter window appears with a view of the chip. Each dot in the window corresponds to a transistor in the design. This display is used primarily in ClockStorm, so you can ignore it here.

You are now ready for analysis.

4. To compute peak saturation currents, type the following command:



Thunder> pwrnet ipeak VDD

This command creates an output file named VDD.ipeak, which contains the desired peak currents. The currents are computed for each transistor connected to the VDD voltage source, assuming a VGS voltage magnitude of VDD and a VDS voltage magnitude of VDD. You can scale the voltages applied to the devices to compute these currents, but it is not necessary. You can scale the resulting currents by using options of the command, but you can also do this scaling in Lightning. Transistors tied to DC voltage sources to turn them off and transistors with source and drain shorted together are assigned currents of 0.0 A.

5. Exit Thunder:

Thunder> quit

An alternate way of using Thunder is to create a command file—for example, ipeak.cmd—that contains the three Thunder commands just given. You can use the command-line version of Thunder to perform the analysis by entering this command:

shell> thunder.tty ipeak.cmd

Thunder.tty creates the VDD.ipeak output file and the Thunder log file. You do not have to run thunder.tty now, but if you do, there is no harm in overwriting the VDD.ipeak file.

Running Lightning

Next, run Lightning by following these steps.

1. Move to the directory containing the VDD power-grid database.

shell> cd ../../lightning/static

If you have the power grid for dynamic analysis (with capacitances), you can use it here with the same results.

2. Run Lightning:

shell> lightning

The Lightning console window appears with a Lightning prompt. This window is similar in appearance to the Thunder console window. It has different menu options, and the File menu has additional options as well.

3. To load the power-grid database, type the following:

Lightning> load SPARCDSP_VDD.mhdr

This command loads the binary power-grid database for VDD and displays the power grid in the plotter window that appears. The layers of material are color coded: METAL_3 is purple, METAL_2 is tan, and METAL_1 is blue.



4. The next step is to define where the power pins are to be placed. Enter the following in the Lightning console window:

Lightning> putvsrc METAL_3 Vsrc1 3.3 24200 1706100




Or, you can run the vsrc.cmd file that you generated in “Generating Basic Static Analysis Data” on page 66:

Lightning> run vsrc.cmd

When you specify a voltage source name, be sure to name each source differently. A white dot corresponding to the placement of the voltage source appears in the plotter window. The voltage source is actually placed at the power-grid subnode on METAL_3 nearest the specified location. Units are in nanometers for X and Y. The resulting window display is shown in Figure 4-2 on page 78.

Figure 4-2 Lightning View After Voltage Source Is Created

Note: You can also place current sources graphically by moving your mouse over the point in the power grid on which you wish to place the power pin and pressing the right button. Select place VSRC from the menu. A window appears on which you can select



the method of executing the command. Once again, do not take this step now.

You now have the voltage sources and the power grid. You only need the currents, which were computed earlier in Thunder and are stored in the file named VDD.ipeak.

5. Load these currents into Lightning:

Lightning> iload ../../thunder/static/VDD.ipeak

A status message on the screen informs you that the command is complete.

6. As a matter of practice after loading the static current data, type this command:

Lightning> scan tc

This command reports statistics about the tap currents just loaded. The data range is 0.0 A to 0.003912 A, with an average current of 0.000959 A and a total current of 17.30 A. If you recall, you have not scaled the current data yet, but to see the effect of solving the power grid with unscaled static currents, type the following:

Lightning> solve

Lightning> scan ir

The solve command prints a number of messages, ending with the memory utilization of the solve. The scan ir command scans the voltages in the power grid and reports their range. In this case, the voltage range is -13.7 V to 3.3 V. This unrealistic voltage range is a clear sign that currents in the power grid are too high. This block would never consume over 17 amperes on average with a 3.3-voltage power supply—that represents over 56 watts. To obtain more appropriate currents, a good estimate for most blocks and chips is to scale currents by 0.01. You can do this in two ways in Lightning:

❑ Through the scalecurrents command, which is designed to scale currents in a specific geometric region

❑ By setting an environment variable to scale them globally

The first method will not be used in this case, because global scaling is necessary.

7. To perform global scaling, enter the following command:

Lightning> setenv currentscalefactor 0.01

This Lightning environment variable is explained in the Lightning Manual.

8. To see the effect of this setting, use the scan command:

Lightning> scan tc

The report printed this time indicates the total current is 0.1730 A, as expected.

9. Now perform the solve again by typing these commands:

Lightning> solve

Lightning> scan ir




Now the voltage range is 3.13 V to 3.3 V. As expected in this linear circuit, the total IR drop was reduced from 17.0 V to 0.170 V, a factor of 100. The scan ir command tells you the minimum voltage in your power grid.

You are now ready to proceed to the next section to learn more about these analysis results. You will learn how to use a variety of techniques to view data in VoltageStorm now that you have the power-grid solve data.

Viewing Analysis Results

In this section, you learn how to use a variety of techniques to gather data from VoltageStorm now that you have the power-grid solve data from “Static Ipeak Power-Grid Analysis” on page 75.

VoltageStorm Outputs

The most common outputs produced by VoltageStorm are the plots of power-grid IR drop, resistor current flow, and electromigration analysis. Although these plots are valuable in understanding the behavior of your design, other forms of feedback are also available:

■ Filtered plots, which are plots of your design with filters applied to data values. The filters determine the subset of data that you view and how each subset should be colored to make the plot meaningful. These plots can be stored in GIF format.

■ Text reports, which contain the subset of the data in which you are interested. The specific data reported is controlled by the filters just described. Although text reports are easy to pass to other tools, they can be very large if you do not filter carefully.

■ Sorted text reports, which can rank your data in worst-case order. You can print this data or access it interactively to take you to the worst errors on your chip.

■ GDSII overlays of filtered data, which enable you to overlay the results of your analysis filtering directly on top of the design in the layout editor.

■ Saved states of your power grid, which you can reload at a later time. This option makes it more efficient to perform data filtering because you do not need to perform the solve again.

■ Movies, which are a unique feature of dynamic analysis in VoltageStorm. Plots of individual time steps are created in the same form as in static analysis but can be placed together to form an animated sequence of your power grid’s behavior.



Filters

The high volume of data processed by VoltageStorm makes normal reporting of every item in the database excessive in size as well as nearly impossible to sort. Therefore, VoltageStorm uses a concept called filtering. Because you are normally interested in only specific problem spots or in sorting data into categories of coarser granularity, filter settings are used to categorize the data for either reporting or plotting. For example, when screening for excessive IR drop, you might be interested only in seeing where the IR drop exceeds 10 percent of your VDD voltage in the power grid. If only 0.01 percent of the subnodes in your grid exceed this limit, there is no need to report all voltages to sort out that small fraction. In addition, if you want to investigate some data further, such as IR drop, you can focus on a specific subrange of voltages to identify the trend in voltages on your chip that led to the excessive IR drop.

Effective use of filtering on the various analysis types in VoltageStorm gives you significant insight into the behavior of your chip and why it behaves that way.

Filtering is a data filtering and binning technique that is applied to each analysis type. The analysis types in the order of most common use are shown in Table 4-1.

Table 4-1 Analysis Types

To Specify This Analysis Type ... Use This Option: Or This Abbrevation:

Tap current (current drawn by transistor taps connected to the grid)

Tap_Current tc

IR drop (voltage on each node of the power grid)

IR_drop ir

Resistor current (current through resistors) Resistor_Current rc

Current density (current through a resistor, divided by the area of the resistor)

Current_Density rj

Electromigration risk (probable time until failure because of electromigration)

EM_risk er

Resistor voltage (voltage drop across a resistor)

Resistor_Voltage rv

Voltage source current (current drawn from voltage sources connected to the grid)

Vsrc_Current vc



Each analysis type can have up to eight filters; each filter consists of a range. You can establish a set of filter ranges by using these methods:

■ Selecting the auto-filter setting on the command line

■ Entering the range on the command line

■ Using a command file

■ Interactively selecting filters from the dialog box activated by the Settings – Filters command in the plotter window

You can change your range settings at any time. During analysis, Lightning checks values against the ranges for every filter that you selected.

You can also quickly turn the filters for an analysis type on or off by using the buttons on the Filters dialog box, which you access through the Settings – Filters command in the plotter window. You can rapidly choose the particular profile of analysis types that you want to use for a given analysis.

When a value falls between the minimum and maximum values that you have set for one of the filters, Lightning reports the value as being in that range. In cases where you define overlapping ranges, Lightning assigns a value that strikes the overlap to the lowest numbered range.

Figure 4-3 on page 83 shows a graphical representation of the ranges of a single filter.

Resistor power (average power dissipated by a resistor)

Resistor_Power rp

Voltage source power (power drawn from voltage sources connected to the power grid)

Vsrc_Power vp

Inductor voltage (voltage across any inductors)

Inductor_Voltage iv

Inductor current (current through any inductors in the grid)

Inductor_Current ic

To Specify This Analysis Type ... Use This Option: Or This Abbrevation:



Figure 4-3 Filters of a Single Analysis Type in Lightning

Using the ranges defined in Figure 4-3:

■ If a specified node in the circuit has a voltage of 3.235 V, filtering yields a range assignment of 6.

■ Lightning assigns a node in the circuit with a voltage of 3.07 to range 1.

■ Lightning does not assign a node at 3.28 V to a range.

Note: Define filter ranges only for those data values that you need to view, because every error identified causes processing in Lightning. For large circuits, this processing can be extensive if all nodes or elements are flagged. Cadence recommends that you exercise caution in defining filters for large circuits.

Applying Filters

In this section, you create a number of plots by using the data in “Static Ipeak Power-Grid Analysis” on page 75. It is assumed that you are continuing from the end of that section. This section emphasizes how to filter analysis types effectively and how to generate meaningful plots faster.

Filters

Lightning assigns a voltage of 3.21 to filter 4

Node voltage

Voltage range settings (filter settings)

3.21

3.26

3.25

3.24

3.23

3.22

3.20

3.15

3.10

3.05

8

7

6

5

4

3

2

1



When looking at the power grid for this design, you can see some potential problems just from the structure. The upper third of the grid covers the datapath of the design. Power is routed in horizontal rows with regular columns of gridding. The middle control portion of the design is powered from the right side only in horizontal power buses. The bottom third of the design, the memory, is routed horizontally as well but is connected at each end. From this structure, it is reasonable to guess that the datapath is the least likely portion to have weak spots, the control section is likely to have weak spots on the left side, and the bottom might have weak spots, depending on the current consumed on each power bus.

Plotting IR Drop

You can set the IR drop filters both automatically and manually by using the filter command (see the “filter” section in the Lightning Manual.)

Automatic filter setting is an easy way to define the filters; options define how to distribute the results throughout the filter range (evenly distributed, logarithmic, or exponential).

Manual filter setting enables you to define the filters exactly.

As you recall from the last time that you used the scan ir command in Lightning, the range of voltages in the design was from 3.13 to 3.3 V.

Manually define IR drop filtering by entering these commands:

Lightning> filter ir 1 0.00 3.14








Lightning> scan ir

Lightning> plot ir

The filters are set to assign the color red to the voltages in the range 0.00 V to 3.14 V, orange to the voltages in the range 3.14 V to 3.16 V, and green to the voltages closest to 3.3 V.

The scan command prints the range of voltages from the IR drop analysis with the number for each filter.

The plot command also prints this report; the scan command can be viewed as a subset of the plot, except that it performs no plotting. The plot command actually creates a color-coded plot resembling a thermal plot. It shows you where in the circuit the largest IR drops




occur as well as the voltage trends from the power pins to each area of the design. This plot is shown in Figure 4-4.

Figure 4-4 First Plot of IR Drop

The largest IR drop is in the central control section on the left side. The plot of the power-grid routing shows that power routing for much of the control circuitry is provided only from one side of the block, yielding high IR drops at the isolated end of the power bus. In contrast, power is supplied to the top and bottom blocks from both sides of the block. When the block is placed in a chip, global power routing contributes additional sources of IR drop. Two lines at the top of the lower block showing larger IR drop in the center of the power bus indicate another area to investigate further.

Setting the filters to span the entire range of voltage in the design creates a coarser granularity in the data of interest. It would be of more interest to focus on the larger range of IR drop.

1. In the plotter window, select Settings – Filters.

A dialog box appears on the screen for filter setting. It is set to the IR drop analysis type by default.



2. To create a new plot, set the lower end of each filter to 0.0 rather than the current number in the dialog box.

This setting is recommended to make filter setting easier for you. If you specify the exact range for each filter, you must change two numbers every time that you adjust filters. These changes are redundant and may cause errors. The filtering mechanism is designed so that if a value fits in range 1, it is set to range 1, and no other filter is checked. Checking the filters continues in priority sequence up to filter 8, so overlapping filter ranges are acceptable.

3. Turn off filters 7 and 8.

It is good practice to plot only the voltage range covering the IR drop of interest. Each data value falling into a filter range causes extra data processing. If all data values fall into filters, this processing becomes excessive for large chips. It is associated with plotting, not scanning, so efficient filter setting uses the scan command to set filters in their proper vicinity to avoid plotting too much or too little data when you use the plot command. Once you create a plot, you can adjust your filters to create the most meaningful plot.

4. Click on OK.

Lightning now executes the filter command with the settings specified in the Filter dialog box.

5. Type the following to see the results of these changes:

Lightning> plot ir

6. Now activate the Filters dialog box again to focus on the voltage range 3.19 V to 3.25 V.

The original filter setting that you specified at the beginning of “Plotting IR Drop” on page 84 used four filters to span this range. Create six filters to span this range.

7. Set the lower range of filters 1 through 6 to 3.19.

8. Set the upper range of the filters to the following:

❑ Filter 1 to 3.2

❑ Filter 2 to 3.21







9. Select the OK button.

10. Select the Plot button on the right side of the plotter window.

A plot of finer voltage resolution in that range is created, as shown in Figure 4-5.

Figure 4-5 Using Filters to Examine a Specific Voltage Range

11. Using the mouse, move to the lower left corner of the control block (center block) at about 349000 603000, press the middle mouse button, and hold it while you move the mouse to the upper right portion of the block at about 2614000 1010000.

When you release the middle button, the Which/Scalecurrents/Measure dialog box appears.

The center portion of the chip is the control logic. If you know that this logic has a quarter of the relative activity of the rest of the design, you can adjust for this in static analysis.

12. Select the measure command.

13. Select OK.

The total current in the selected region—0.06089 A, in this case—is printed in the console window.



14. Draw the box by using the middle button again.

15. Select the scalecurrents command.

The dialog box changes to show the range and the scale type selected. It also allows you to specify the scale factor. The scale type should be relative to scale the currents in this window.

16. In the scale factor box, enter 0.25.

17. Press OK.

Lightning executes the scalecurrents command.

18. To measure the impact of this scaling, use the middle button to draw the box around the control block again.

19. Select the measure command again.

20. Select OK.

The total current is now 0.01522 A.

21. Now type the following sequence:

Lightning> scan tc

Lightning> solve

Lightning> scan ir

The total current has been reduced to 0.1273 A. After the solve, the range of voltages in the grid is 3.243 V to 3.3 V. The scan ir command shows that the filters do not capture much information in a plot, so you must change your filter ranges.

22. Bring up the Filters dialog box again.

23. Set the lower range of filters 1 through 6 to 0.0 V.

24. Set the upper range of the filters to the following:







25. Select the OK button.



26. Select the Plot button on the right side of the plotter window.

The resulting plot is shown in Figure 4-6.

Figure 4-6 IR Drop Plot After Control Scaling

More information is now visible, because the filters are set to focus on the voltage range near the IR drop magnitude rather than including voltages near 3.3 V. The largest IR drop is now in the two lines at the top of the memory block mentioned earlier. An additional weak spot is now more visible at the bottom of the design. An undesirable IR drop trend appears in the control block. You can now see the IR drop trend in the middle of the datapath section at the top of the design.

27. Now that you understand how filtering works, experiment with the use of the automatic filter setting.

You are now prepared to examine the tap current distribution and the flow of current in the design.

Note: The key to finding weak spots in your power grid is to look for anomalies in the plots that you create. In this case, single power lines stand out, indicating that they have either a high current load or are too narrow. Also, look for abrupt changes in voltage. The changes show breaks in the connectivity of a design. The normal appearance of the voltage on a chip



is a set of concentric circles resembling a bull’s-eye in the center of the chip. Bull’s-eyes in other locations, particularly away from the center of the chip, are worth investigating. As you gain experience using VoltageStorm, you will become proficient in finding weak spots in power grids.

Plotting Tap Currents

You just created a plot of the IR drop throughout the design. Before proceeding to look at the current flow, look at the geometric distribution of tap currents. Earlier, you used the scan tc command to see the total current in the design. Now you will create filters for plotting the tap currents. The last information on tap currents reported that the total current was 0.1273 A and that the maximum current was approximately 39 μA.

1. Activate the Filters dialog box.

2. Set the analysis type to Tap_Current.

3. Set the maximum value for filters 1 through 5 to 1.0.

4. Set the minimum value of the filters to the following:

❑ Filter 1 to 2e-5




❑ Filter 5 to 0.0

5. Select OK.

6. Select the button for Tap_Current on the right side of the plotter window.

7. Select the Plot button.

The plot of tap currents in Figure 4-7 on page 91 shows larger areas of current in the datapath, smaller currents in the control section, and three rows of high currents in the memory section, with the highest currents on the left side. This configuration explains the high IR drop on the three rows in the memory.



Figure 4-7 Current Distribution

Plotting Resistor Current

After observing IR drop plots, the next question is how the current flows in the design to create the IR drop plot generated. It is important to examine these plots because they also exhibit behaviors that are not obvious from examining the IR drop plots. These plots show current-flow trends that you might not have expected or current from several power pins reconverging in the middle of the chip to create high current through some wires.

Resistor current value distribution has different characteristics than voltage. It tends to vary by orders of magnitude among wires in the power grid. The maximum current should be near the power pins and the minimum near the transistors. When setting filters for resistor current, you will scale down successive filters by a factor, such as 2.

1. As with most filtering, begin with the following:

Lightning> scan rc

The maximum current is 0.0358 A, and the average is 72 μA: 500 times smaller.

2. Activate the Filters dialog box.

3. Set the analysis type to resistor_current.









6. Select OK.

7. Type the scan command again:

Lightning> scan rc

When plotting IR drop for VDD, you set the minimum to a fixed value because you were interested in the low end of the range. Here, you are interested in the high end of the range, so you set the maximum value above the data maximum. The ranges show an increasing trend in the number of currents in each range.

8. Now bring up the Filters dialog box to add a couple more filters before a plot.

9. Set the maximum value for filters 5 and 6 to 1.0.

10. Set the minimum value for filter 5 to 0.0005 and filter 6 to 0.0002.

11. Select OK.

12. Type the following:

Lightning> plot rc

The plot, shown in Figure 4-8 on page 93, displays the highest currents in red and currents of smaller magnitude in cooler shades down the scale.



Figure 4-8 First Resistor Current Plot

13. This plot is too dense for a good current plot, so turn off filter 6 and replot:

Lightning> filter rc 6 off

Lightning> plot rc

The resulting plot, shown in Figure 4-9 on page 94, is not as cluttered with current data.



Figure 4-9 Final Resistor Current Plot

You can see the high current flowing away from each power pin, with the most coming clearly from the upper pins. In the upper portion of the design, you can see the most current flowing down from above, but some power buses show current rising from the bottom of the bus. The power current is therefore split between current paths.

In the current entering the control block from the right side, three upper buses are clearly fed from the top pin, and three lower buses are fed from the bottom pin.

Current reconverges on the left side of the design just below the left edge of the control block. The color of two wires changes from gold to orange and back to gold. While holding down the left button, use your mouse to draw a box around that portion of the design, similar to the box shown on the left side of Figure 4-9 on page 94. When you release the button, Lightning zooms that portion of the design so you can see the grid and current overlay in greater detail. You can see the source of reconverging current: two power wires enter from the left and are connected. After passing a number of connections down to logic, the color changes back to gold from orange, because the logic consumes some of the current and therefore less continues down the power bus.

Press the ZR button on the upper right side of the plot window to zoom the entire chip. As you learn to apply filters, examine results, and zoom in and out, you will become quite effective in using VoltageStorm to learn the behavior of your chip.



You can see that each type of analysis plot has its own ideal feedback density. This density is better illustrated by examining current density.

Plotting Current Density

Once you understand how current flows through your design, you may want to know where the high current densities occur. Use the Current_Density (or rj) analysis type to examine them. You normally set current density limits to 1 mA per micron width, which is the default in Lightning. You can change current density limits by using the model command. You will use the defaults here.

Current density reporting is not based on actual value but on the ratio of wire current density over the limit. You therefore want all wires to have a ratio less than 1.0. This ratio is easier to work with because its value is more consistent across designs. You should only be concerned with values greater than 0.5 and focus on the few highest values.

1. Look at the data range:

Lightning> scan rj

The range is 0 through 1.481.

2. Now bring up the Filters dialog box to add a couple filters before a plot.

3. Set the analysis type to Current_Density.




❑ Filter 2 to 1.0

❑ Filter 3 to 0.7

6. Select OK.

7. Enter the following:

Lightning> plot rj

The plot, shown in Figure 4-10 on page 96, shows a handful of potential problem spots, mainly near the power pins, as expected.



Figure 4-10 Current Density Filtering

Using the Layer Visibility Menu

This is a good time to examine the Layer Visibility menu.

1. Select the top dotted line in the Layer Visibility menu to tear off the menu. Place it to the side for easy access.

The following discussion refers to turning layers on and off. Turning a layer off means selecting the layer in the Layer Visibility menu so that it is not selected and therefore not displayed onscreen.

2. Select All Errors Off.

You see the error overlay from the current density plot disappear. If you select All Errors On, they reappear.

3. Turn the errors off again.

4. Now select All Grid Off.

The plot window should now be empty except for the four white dots corresponding to the voltage pin locations; they are on the show layer.



5. Now turn on METAL_3.

The purple routing for METAL_3 is now visible.

6. Now turn on the METAL_3 errors.

You see a subset of the total errors overlaid on the METAL_3 wires, making it possible to easily examine current density violations on individual layers.

7. Now turn off METAL_3 and its error layer, and turn on METAL_2 and its error layer.

You see the subset of filtered data overlaid on top of the wire routing for METAL_2. If you zoom in on the errors in the middle left, you see the wire segment that exhibited the reconvergent current when the power wires were connected. Many current density violations are created when current flows through various paths, converges, and continues through to the logic.

8. Now turn on the VIA_2 errors and METAL_3. Turn off the METAL_2 errors.

You now see both metal wires and several locations identified where current flows through the via from METAL_3 to METAL_2. These data points mean that the current through the vias may be excessive.

9. Zoom in on the pair of violations in the lower left. The black box in the lower left portion of Figure 4-10 on page 96 shows the zoom area.

When you are close, you can see that two pairs of vias are flagged. The upper pair is more serious, because that power bus supplies more gates. The flagged vias are paired because the via is implemented as a pair of vias, and both are flagged. You will regularly see current crowding in corners of via clusters.

10. Now select All Grid On and All Errors On, and reset the zoom.

Layer visibility is useful when you want to zoom in and understand your layout and the data better.

Note: The wires drawn on the screen are stick diagrams; they do not show actual wire widths.

Worst Error List

You can examine a list of the worst errors in VoltageStorm.

1. On the Lightning plotter window, select Error List – Error List.

2. Select the Current_Density analysis type.

The Error List dialog box displays a list of errors numbered 0 through 19.



3. Double-click on Error 0. The wire segment in the upper right corner is highlighted to show you where the worst error is located.

4. Now change the action selection to Goto Error.

5. Double-click on Error 0 again.

The display pans so that the error is in the middle of the window.

6. Press the ZI button twice in the upper right corner of the plotter window to zoom in on the error.

7. Now double-click on Error 4.

The display moves you to the lower left corner of the block so you can see the fourth worst error on a via.

8. Press the ZR button to reset the plotter view, and close the Error List dialog box.

Saving Filter Settings

Having created several sets of filters, you may want to save them so you can reload them later. To save them, type the following command:

Lightning> write filters filters.cmd

This command writes all current filter settings as commands in the filters.cmd file, which you can reload by using the next command:

Lightning> run filters.cmd

This file is used later in this chapter.

What if VSRC1 Were Not Connected?

You originally placed four voltage source pins on the chip. You may have forgotten their names and locations.

1. Use the mouse and the middle button to draw a box around the entire design, being sure to include the four white dots corresponding to your voltage source pins.

2. Release the button, and select the Which command.

3. Select the element type voltage source.

4. Select OK.

A small report is printed in the console window showing you the definition of the voltage sources.



You can disable a voltage source to see the impact. Try an experiment to observe the behavior of the block if Vsrc1 were disabled.

5. Enter the following sequence of commands:

Lightning> plot ir

Lightning> disable-vsrc Vsrc1

Lightning> solve

Lightning> plot ir

The second plot shows a high IR drop in the upper left corner of the design, because the power connection was disabled.

6. To return to the previous state, type the following:

Lightning> enable-vsrc Vsrc1

Lightning> solve

Lightning> plot ir

You now see your previous IR drop plot again. You can also experiment with voltage sources by placing more on your design and solving again. Remember that you must solve the circuit again if you change voltage sources or currents.

Defining Electromigration Model Parameters

The graphical user interface (GUI) contains a function for defining model parameters associated with each physical layer in a design, that is, METAL_2, VIA_1, METAL_1, CONT, and so forth.

The model parameters are categorized into three groups:

■ Parameters used in current density electromigration analysis

■ Parameters used in electromigration risk analysis

■ Thermal parameters used to calculate changes in resistance values with temperatures

Use the EM Model dialog box to set the three different groups of model parameters.

1. From either the Lightning console window or the plotter window, select Settings – EM Model.

The EM Model dialog box, similar to the one shown in Figure 4-11 on page 100, now appears.



Figure 4-11 EM Model Dialog Box for Current_Density Model Type

2. From the Layer popup menu, select the layer for which you want to set the parameters. The model types you can select are Current_Density, EM_Risk, or Thermal.

Depending on the model type that you select, you will see one of three model dialog boxes for that model type:

❑ When you set the parameters for the Current_Density model type, a dialog box similar to the one shown previously in Figure 4-11 appears. New current types listed in the popup are Avg, Rms, Peak, and Rec.

❑ When you specify to set the parameters for the EM_Risk model type, a dialog box similar to the one shown in Figure 4-12 on page 101 appears.



Figure 4-12 EM Model Dialog Box for EM_Risk Model Type

❑ When you set the parameters for the Thermal model type, a dialog box similar to the one shown in Figure 4-13 on page 102 appears.



Figure 4-13 EM Model Dialog Box for Thermal Model Type

3. Enter the desired parameter values for the layer and model type that you select.

For information on entering parameter values, refer to the parameter descriptions for the model command in thje “model” section of the Lightning Manual.

See Modeling Electromigration Risk,” of the VoltageStorm Cell-Level Rail Analysis Users Guide for more information on electromigration modeling.



../vstormpe_ug/issues.html#model_electro_risk

../vstormpe_ug/issues.html#firstpage

../vstormpe_ug/issues.html#firstpage


Saving Plots

Having generated a series of plots based on sets of data for the sparcdsp design, you might want to save some GIF images of the plots. Follow this procedure to save a set of images:

1. On the left side of the plotter window, select the button for IR drop.


3. Type the following in the Lightning window:

Lightning> image save ipeak_ir.gif

4. Select the Resistor_Current button.



Lightning> image save ipeak_rc.gif

7. Select the Current_Density button.



Lightning> image save ipeak_rj.gif

You have now saved three plots. You can load these GIF images into word processors or back into Lightning.

10. To reload the IR drop image, type this command:

Lightning> image load ipeak_ir.gif

11. You are done for now, so exit Lightning:

Lightning> quit

Recommended Analysis Design Flow

Given the methods described in previous sections to graphically display your data, you can now follow the recommended flow.

1. Use Thunder to generate the current data for your design.

2. Load the power grid into Lightning, and place the voltage source pins.

3. Use the image command to create a GIF image of the grid for reference.

4. Load the current data from Thunder into Lightning.



5. For the blocks whose relative activity you know, use the scalecurrents command to scale the currents for the blocks. The scale factor for a memory is typically 1 divided by the number of words. If your design has blocks whose activity is exclusive (only some portions can be active at any one time), scale the currents in those blocks accordingly. For example, if a block has four units, only one of which can be active at a time, scale the currents in the block by 0.25.

6. Generate the plot of tap currents to visually inspect the areas of scaled currents. If you missed any blocks, return to step 5. When you are done, generate a GIF image of the plot for reference.

7. Given the total current reported by the tap currents scan and an estimate of your expected total power current, compute the appropriate value for setting the CurrentScaleFactor environment variable, and set that variable. The computation is as follows:

scale_factor = power_estimate/(Vdd*Ifrom_scan_tc)

Use the scan tc command to verify the results. Expected power consumption can be in the range of 0.5 W to 3.0 W per 1 million transistors.

Note: The estimate of the expected total power current is derived from the total expected power consumption during active logic switching. You may not want to average in the inactive time of the design, because it can be substantially lower than average power consumption.

8. Solve the power grid.

9. Use the savestate command to save the solved state. Saving it makes it easier to continue later without having to solve the system again, which is important for large designs.

10. Iterate between using the scan ir command and setting the filter to derive a good set of filters to observe IR drop. These filters are generally equally sized steps. When appropriate for your design size, complete the iteration by using the plot ir command. The scan command is recommended for early iterations for efficiency on large designs. Plotting about 25 percent of the data values should yield a meaningful plot without excess processing. Look for filter settings that highlight irregular patterns in the grid. Use the image command to create a GIF image of your plot.

11. Iterate between the scan rc command and filter setting to derive a good set of filters to observe resistor current flow in your design. These filters generally decrease in magnitude logarithmically. When appropriate for your design size, complete the iteration by using the plot rc command. The scan command is recommended for early iterations for efficiency on large designs. Plotting about three percent to five percent of the data values should yield a meaningful plot without excess processing. Look for filter



settings that clarify how current flows throughout the grid. Create a GIF image of your plot by using the image command.

12. Create a plot for each layer with only the metal layer and its error layer turned on. For example, turn off the grid and all errors, then turn on METAL_2 and METAL_2 errors, and save the image. These plots help in understanding the behavior of each metal layer.

13. Iterate between the scan rj command and filter setting to derive a good set of filters to observe resistor current density in your design. These filters generally decrease in magnitude logarithmically. When appropriate for your design size, complete the iteration by using the plot rj command. The scan command is recommended for early iterations for efficiency on large designs. Look for the few wire segments that have the highest values. Plotting the top 300 current values or all those above 0.8 should yield a meaningful plot. Create a GIF image of your plot by using the image command. If you defined appropriate model parameters, you can also generate a plot of electromigration risk.

14. Create a plot for each layer with only the metal layer and its error layer turned on. For example, turn off the grid and all errors, then turn on METAL_2 and METAL_2 errors, and save the image. Those plots help you identify the specific wires most likely to fail because of electromigration.

Recommendations for Using Lightning

This section recommends techniques for obtaining the best results from Lightning. These insights are most meaningful if you are analyzing a very large design.

■ Because of the volume of data in large designs, store temporary Thunder and Lightning files in the /tmp directory of your local machine. Lightning uses the temporary files for commands, and if they reside on a machine elsewhere on the network and your network is overloaded, Lightning’s performance might be adversely affected. Moving as many files as possible to the local machine can improve its performance significantly, perhaps by as much as five times.

■ Using the scan command to iterate the filter settings avoids the processing involved in plotting large volumes of data until it is really needed. Depending on your design size and network performance, iterating with the plot command with significant amounts of data can be slow.

■ It is good practice to save the state of the analysis after a solve to avoid having to solve the power grid again to continue analysis in another session. To reload the saved state, you must define the voltage sources on the power grid at the same locations as on the grid used when saving the state. Tap currents are not saved as part of the saved state, so you must load them again.



■ Be sure you have enough disk space when you process a lot of data with Lightning to avoid problems. If your local disk is limited in size, store the design data on another machine, and store the temporary files locally.

■ Redrawing the grid of a large design can be time-consuming. Be careful about resizing the screen and zooming too often when you work on large designs. You can use Ctrl-C to interrupt the redrawing of the grid when you zoom or pan.

Static Activity-Based Power-Grid Analysis

Activity-based analysis is another approach to static analysis that better resolves the distribution of currents on your power grid. The activity-based approach assumes that you have a mechanism such as a Verilog simulator to compute and report the relative activity of the nets in the design. The VoltageStorm activity-based data flow is shown in Figure 4-14 on page 107. These relative activities can be used in conjunction with net capacitances to estimate the average current load of each gate in the design. This form of analysis clearly provides more realistic power current data than the ipeak approach.

The following sections step you through activity-based analysis.



Figure 4-14 Activity-Based Data Flow

Using Activity Data to Compute Current

As input, activity-based analysis uses a file containing the activity levels of nets in the design. This input file is optional but recommended. In addition, activity-based analysis has three other important input parameters.

■ The clock cycle time of the chip for which the activity values are defined

■ The value of VDD

■ The default activity to use for gates whose activity is not specified

The average current for each gate is computed using the loading of the gate, VDD, the cycle time, and the activity of the gate.

The average current consumed by a gate is derived by the following equation:

IAVG A CGATE× VDD× F×=



where A is the activity ratio of the gate, and CGATE is the total capacitance of the nets in the gate, including loading. This equation for average current is derived simply by considering the charge, Q, required to charge the outputs of the gate in a clock cycle interval (1/AF). If a gate has multiple transistors connected to VDD, the average current is split evenly among the transistors. This derivation of average current is not a function of transistor sizes.

If your design has multiple clocks, select one clock to be the reference for the activity analysis, and scale the gates associated with other clocks accordingly. For example, if CLK1 has a period of 10 ns and CLK2 has a period of 15 ns, and CLK1 is to be the reference for activity-based analysis, scale the activity of gates in the CLK2 domain by 0.666. On the other hand, if you actually have toggle-count numbers for all nets, use CLK1 as the reference to divide all net toggle counts to drive activity value.

If you have different power supply voltages, you should analyze these power grids separately. For each power net, specify the parameters and generate the report.

Performing Activity-Based Power-Grid Analysis

The tutorial/release_version/sparcdsp directory of the Cadence installation includes an additional file that you need for this analysis. This file was copied into your data directory in Chapter 3, “Preparing to Use VoltageStorm.”

1. Assuming that you are in the SPARCDSP/flat/lightning/static directory, copy this file into the thunder/dynamic directory:


shell> cp ../../../../data/activity.list .

This file contains a list of nets in the design and their activity levels. In particular, it lists nets on the clock trees, all of which have activities of 1.0. The file only contains a subset of nets in the design, so activity analysis here uses the default activity factor. This analysis uses the name-backannotated netlist, capacitance database, and power-grid database.

2. Start Thunder and load the design:

shell> thunder


3. Set the parameters for the activity command, and load the file of activity values:

Thunder> activity default 0.03

Thunder> activity cycle_time 5ns

Thunder> activity vdd_range 3.3

Thunder> activity filen activity.list



In this case, the default activity is set to three percent. The cycle time is set to 5 ns, and the VDD range is set to 3.3. The activity filen command reads the file and sets the activity for each node as specified in the file.

4. Complete the analysis by generating the report, then exit Thunder:

Thunder> activity report VDD

Thunder> quit

The activity report command computes the tap currents on the basis of these activities and writes them in the file called VDD.iavg.

You now proceed to power-grid analysis.

5. Change to the lightning/dynamic directory:

shell> cd ../../lightning/dynamic

6. Copy the files from the static directory for defining voltage sources (created in “Running Lightning” on page 77) and defining filters (created in “Saving Filter Settings” on page 98):

shell> cp ../static/vsrc.cmd .

shell> cp ../static/filters.cmd .

7. Start Lightning, load the grid, define the voltage sources, and load the currents just computed.

shell> lightning




Lightning> iload ../../thunder/dynamic/VDD.iavg

You now have the information necessary for a solve. Use the filters that you created earlier.

8. Before solving the grid, make a plot of the tap currents, so you will see how the plot has changed:

Lightning> plot tc

The red spots in the grid indicate the location of gates in the clock tree. Other gates are scaled according to their loading, assuming a three percent activity, as shown in Figure 4-15 on page 110.



Figure 4-15 Tap Current Plot Based on Activity-Based Analysis

You can see the high currents associated with clock gates at the bottom of the design.

You can also see that the total current has changed from 0.1273 A in “Plotting Tap Currents” on page 90 to 0.08858 A. This change means that the filters for IR drop and resistor currents must change.

9. Now solve the grid:

Lightning> solve

10. Because of the current change, change the IR drop filter maximum values to the following:

❑ Filter 1 to 3.0








11. Now plot the IR drop and resistor current:

Lightning> plot ir

Lightning> plot rc

The IR drop plot, shown in Figure 4-16 on page 111, shows the large IR drop on the bottom of the memory, because the gates on the power bus are all drivers on the clock tree.

Figure 4-16 IR Drop Plot Based on Activity-Based Analysis

The large IR drop in the control block was expected on the basis of the results of the ipeak analysis. The IR drop at the bottom of the memory also was identified in the ipeak analysis, although it was not as significant as it is here. The plot of resistor current, shown in Figure 4-17 on page 112, also shows current flow as expected, given the grid and the IR drop.

12. Exit Lightning:

Lightning> quit



Figure 4-17 Resistor Current Plot Based on Activity-Based Analysis

Using the Wrong Grid

A common mistake when building a name-backannotated power grid for dynamic analysis and one that is not name-backannotated for static analysis is mixing up data so that the tap current file is crossed between data sets. SPARCDSP contains the data to enable you to create the symptom of this mistake. Follow these steps:

1. Start Lightning:

shell> lightning

2. Load the power grid and define the voltage sources:



3. Try to load in the currents:


You should see a large number of warning message scroll in the Lightning console window. You can use Ctrl-C to interrupt the command. The error messages are of the following form:



Warning: current source name undefined in the netlist

This error means that the transistor names in the tap current file did not match the transistor names in the power-grid database. The error occurred because the power grid in this case is name-backannotated, so all transistor names include the schematic name, but the tap current transistor names from the thunder/static directory are layout names. If you load the current data in VDD.iavg from the /thunder/dynamic directory, they will match.

You will also see this error if you are in the /lightning/static directory and try to load currents from the /thunder/dynamic directory. You will not receive these errors if both static and dynamic data sets have the same names, whether name-backannotated or not.

4. Exit Lightning:

Lightning> quit

Loading a Current Set Twice

Another cause of error is loading tap currents twice for the same transistors, but failing to clear the current values in between. The ability to load multiple tap current files permits you to create these files for several blocks of the design independently and merge them together in a single power-grid analysis. When a current file is loaded twice, the second current values are simply added onto the devices again—effectively doubled. Try the following:

1. Move to the lightning/dynamic directory.

2. Start Lightning, load the power grid, and define the voltage sources:

shell> lightning



3. Load the activity currents and look at the total current:


Lightning> scan tc

4. Load the currents again and look again at the total current:


Lightning> scan tc

5. Clear the currents, reload the currents, and look again:

Lightning> iclear


Lightning> scan tc



You can see that when you loaded the currents twice, the total current was doubled. When you cleared the currents and loaded them again, the values reverted to those of a single load. VoltageStorm’ flexibility also makes it easier to create inadvertent errors.

6. Exit Lightning:

Lightning> quit

Static Vector-Based Power-Grid Analysis

The third method for performing static power-grid analysis is to use dynamic vectors to exercise your design while tallying average currents in the transistors connected to the power supplies, as shown in Figure 4-18 on page 114. This method yields average currents for transistors on the basis of the specific vector set. This type of average current is useful in electromigration analysis. However, the vector set must be sufficiently representative of your design usage to achieve quality average currents.

Figure 4-18 Vector-Based Static Power-Grid Analysis Flow



Vectors Input to Thunder

You can specify input vectors to Thunder in three ways:

■ Define SPICE-like voltage sources in the netlist.

■ Use a Thunder-specific vector file to describe waveforms.

■ Use VCD files.

The SPICE-like voltage sources that Thunder supports are DC, pulse, and piecewise linear (PWL). The format for all three forms are provided in the Thunder Reference Manual. The example analysis here uses SPICE-like voltage sources to drive only the clock to illustrate how to perform this analysis.

Performing Vector-Based Netlist Analysis

Follow these steps to analyze the netlist:

1. Change to the thunder/dynamic directory:


If you examine the sparcdsp_input_sources.inc file, you see that pulse waveforms for CLK and CLKN have been defined. The waveforms have a period of 5 ns. Only the clocks are used in this case to illustrate dynamic vector-driven static power-grid analysis.

2. Start Thunder and load the circuit:

shell> thunder


3. Because the DC solution is always a difficult step in the simulation of a large design and may result in some unrealistic initial states that are resolved after a clock cycle, simulate for six clock cycles to initialize the system properly.

After computing an initial state, save it to reuse later:

Thunder> s 30

Thunder> save ic state.ic

The s command performs the DC solution and simulates the circuit for 30 ns: six clock cycles. As the simulation progresses, Thunder updates the progress bar. The save ic command saves the voltages of the circuit in the format of .ic cards. This file is used in “Dynamic Analysis” on page 119 to avoid the computation of a DC solution.

4. Now begin tallying currents for devices connected to voltage source VDD:

Thunder> pwrnet tally VDD


../thunder/titlecopy.html#firstpage


The pwrnet tally command instructs Thunder to begin tracking the average, peak, and RMS currents for all devices connected to voltage source VDD when you next perform simulation.

5. Separately tally the current from the VDD source as well:

Thunder> devi tally VDD

Thunder> devi tran VDD

The devi tally command instructs Thunder to begin tracking the minimum, maximum, and average current for the VDD voltage source when you next perform simulation. The devi tran command instructs Thunder to create a Thunder.tran output file that provides the transient waveform for the current of voltage source VDD. This transient waveform file can be read and displayed by StormCenter, Cadence’s interactive waveform viewer.

6. Simulate for another 10 ns (two clock cycles), report tallied currents for VDD, and exit Thunder:

Thunder> s 10

Thunder> pwrnet report VDD

Thunder> devi report

The pwrnet report command instructs Thunder to write the tallies gathered so far into the VDD.avg, VDD.max, and VDD.rms files. In this case, the three files are all in ASCII format, which you can examine. The devi report command instructs Thunder to report the minimum, maximum, average, and RMS current of the VDD voltage source.

According to SPICE convention, the current of a device entering the device at the terminal is positive, so normal current flow into the VDD voltage source is negative. Therefore, the reported minimum value is the peak absolute current generated by the VDD source, and the average current should be negative. It is common for the maximum current to be positive because of the charge injected into VDD when a signal such as the clock switches high.

7. Exit Thunder:

Thunder> quit

8. To examine the VDD voltage source current waveform, start StormCenter:

shell> storm

9. Select Load Default to load the Thunder.tran file into StormCenter.

10. Select New Plot to bring up the Plot dialog box.

11. Select the line marked Thunder.tran : 000 : I(VDD).

12. Select Plot Selected.



The current waveform for the VDD voltage source is now visible in the plotter window. You see the four edges of the clock signal: two clock cycles, each with a rising and falling edge. The waveform begins at 30 ns because that is when the command was given to begin reporting the waveform.

13. Select File – Exit to exit StormCenter.

You have now completed the netlist analysis portion of the vector-based static power-grid analysis.

Performing Vector-Based Static Power-Grid Analysis

The power-grid analysis portion of the flow is much like the analysis performed in the activity-based static analysis, except that the current input file is different.

1. Start Lightning:


shell> lightning

2. Load the design and the command file:



3. Perform the analysis:

Lightning> iload ../../thunder/dynamic/VDD.avg

Lightning> solve

4. Now apply the analysis-filtering techniques presented in “Recommended Analysis Design Flow” on page 103. The IR drop in this case goes as far down as 3.265 V. IR drop filter maximums of 3.27, 3.275, 3.25, 3.285, 3.29, 3.295 for filters 1 to 6, respectively, show that the maximum IR drop occurs in the left side of the central section, as shown in other vector analyses. This plot is shown in Figure 4-19 on page 118.



Figure 4-19 IR Drop Plot Resulting from Vector-Based Analysis

When performing static analysis, remember that you are averaging currents over clock cycles, which means that periods of high current are averaged with periods of low current, yielding an average much less than the peak. This averaging will become clear when you perform dynamic analysis in “Dynamic Analysis” on page 119.

On the other end of the spectrum is the VDD.max file computed by the pwrnet command in Thunder. It tracks the peak current of each transistor on the power grid.

5. Load it in and solve the circuit:

Lightning> iclear

Lightning> iload ../../thunder/dynamic/VDD.max

Lightning> solve

When you perform analysis filtering on this data, you see that the IR drop now extends down to 2.772 V. This figure is an overestimation of the peak IR drop in the power grid, because it models all transistors turned on to their maximum current at the same time. The actual peak IR drop is somewhere between that reported using the VDD.max file and that reported using the VDD.avg current file. Use the VDD.max current file only on small blocks for which you want to perform an easy pass/fail screening of the block power grid. If you try to apply peak currents to large designs to which many vectors have been



applied, you will see an unrealistic measure of IR drop. You can use it on small blocks in which many gates could potentially switch at once.

6. Exit Lightning:

Lightning> quit

Dynamic Analysis

Dynamic analysis supplements static analysis by providing more precise insight into the behavior of the power grid. Static analysis averages tap currents to look at the long-term average behavior of the power grid. Dynamic analysis keeps the time distribution of current in place so you can see the voltage and current waveforms in a more numerically precise sense. It provides better visibility into the magnitude of the IR drop.

Goals

The goal of VoltageStorm is to help you find weak spots in the implementation of your power grid. Dynamic analysis is one of the tools to help you find these weak spots. Dynamic analysis has two specific goals:

■ It helps you find weak spots in the power grid by predicting a worst-case test vector for IR drop from the test vectors that you have. It is difficult to find the worst-case IR drop test vector, because it is a function of the physical implementation of your design, not the logical implementation.

■ It enables you to analyze specific test vectors on your design. This capability is most useful when you know some specific test vectors that you must analyze in great depth to obtain the exact magnitude of IR drop on the power grid.

The key to success in dynamic power-grid analysis is selecting the step size (or interval size) for power-grid analysis. Step size is different from the simulation time step in netlist analysis. Netlist analysis uses internal time-step control to keep the simulation accurate. Power-grid analysis step size reflects how often the tap currents passing from netlist analysis to power-grid analysis are updated. If the step size is too small, power-grid analysis is very slow. If it is too big, the ability to sort out the time variation of switching behavior is lost. To this end, use the typical gate delay as the size of the time step for updating current data from netlist analysis to power-grid analysis.

Vector Compression

Vector compression was initially introduced in “Vector Compression” on page 49, and this section expands that discussion.



Vector compression is optional in VoltageStorm. You may prefer to apply vector compression during dynamic analysis because of its ability to help predict a worst-case vector, as well as the performance improvement that it yields when VoltageStorm processes a large design.

Obtaining usable results from vector compression requires you to set the parameters for compression carefully. You set three parameters:

■ method, which determines whether to compress using the peak or averaging across multiple vectors

■ period, which is the time period over which you want compression to be applied

■ intervals, which is the number of time steps that you want in each period

In “Vector Compression” on page 49, the time period over which you compress is called the clock cycle, and each time step, or interval, is called a bucket. Figure 2-16 on page 50 has 10 intervals in the time period.

Dynamic Tap Current Files

The tap current data generated by dynamic analysis is best described initially by eliminating vector compression. For this discussion, assume that there is no compression; the period option of the pwrnet tallyint command is equal to the total simulation time. When you perform dynamic analysis in Thunder, it keeps track of the peak, average, and RMS current of each transistor over each time interval (bucket) for power-grid analysis. For each new time interval, additional data is added to the output files for each transistor connected to VDD. The size of the data files is therefore a function of the number of transistors connected to VDD and the number of time steps of analysis. The data files for these three tallies have the .ptimax, .ptiavg, and .ptirms extensions, respectively. These three files are always created by the pwrnet tallyint command and are updated as the simulation proceeds. The number of time intervals in these files is the number of intervals specified in the command option.

Figure 4-20 on page 121 shows how to apply averaging within intervals for a transient waveform. The waveform is broken into nine total time intervals corresponding to the three intervals (buckets) for each of the three clock cycles. The upper plot shows the current waveform for each interval. The lower plot shows the average value of the current waveform within each interval. Any current spikes due to noise are filtered in this averaging process.



Figure 4-20 Mapping from Transient Current Waveforms to Average Values for Each Interval

The next question is how you should set the number of intervals. As noted previously, the optimal size of a power-grid time step is the delay of a normal gate. Making the time step smaller than half a gate delay does little to increase the information available for the additional computation, unless you intend to model inductances in your power grid. If you make the step size larger, the activity of several gates that operate at different times are merged into simultaneous operation with respect to power-grid analysis by the bucketing. This large step size results in overestimates of IR drops in the .ptimax file. The .ptiavg file contains much more appropriate results because the storage of average currents in each bucket compensates for the bucketing.

In typical designs, the clock period is approximately 10 gate delays, so you use a step size that is a tenth of the clock period. You must perform this analysis yourself to be sure that you

Current

Current

Cycle 1

Cycle 2 Cycle 3Cycle 1

Cycle 2 Cycle 3

Time

Time

average

average average average

0

0

1 1 1

1 1 1

2 2 2

222

3 3 3

333



are using the correct step size for your design. Without compression, therefore, the number of intervals to use is the simulation time divided by the step size.

Setting Parameters for Compression

The next issue to understand is how to set the vector compression options for your design. Compression uses the activity of your design to try to predict a worst-case IR drop test vector for power-grid analysis, as well as to reduce the number of power-grid matrix solves required for analysis. If your goal is to measure a realistic IR drop for a specific test vector, you should not use compression.

The first question to address in vector compression is what to use as the period. In general, use the clock period as the period of compression, because you want to gain a better insight into the operation of your design over a clock cycle. Most activity occurs near the edges of the clock, so you want to see if IR drop problems occur because of the clock itself or in logic switching after the clock. Ultimately, you may want to find where gates are still switching just before a clock edge, that is, where path timing may be of concern.

If your design has multiple clocks and no specific clock dominates the area of the chip, you can consider several approaches. Your knowledge is key in making the correct decision. You can run analysis several times, each time setting the options to focus on a specific clock as the basis of the compression period. You can also use the least common multiple of the clock periods to set the compression period. Each approach has merits, depending on the specific aspects of your design.

The second question to address is the number of intervals to apply. Once again, the starting point is based on the delay of a typical gate. The number of intervals to use is then the period divided by this gate delay. There is no harm, other than power-grid solve performance, in using more intervals.

The third question is the selection of the method to apply in compression: peak or averaging. Understanding compression is the critical step in making the right decision. The table on page 37 shows compression as a process applied down the columns of the table. Compression using the peak (method=000) applies the largest value in the column as the compressed value for the bucket. Compression using average (method=111) takes the average down each column.

Figure 4-21 on page 123 uses the data from Figure 4-20 on page 121 to illustrate these two forms of compression. The three data cycles are broken apart here and stacked on top of each other. The left side of Figure 4-21 on page 123 shows the three cycles of data compressed using the peak operation, resulting in the bottom current waveform. The right side of Figure 4-21 on page 123 shows the application of average compression to derive the bottom waveform.



Figure 4-21 Example of Peak and Average Vector Compression

CurrentCurrent

Time

Time

Time

Time

Time

Time

Current Current

CurrentCurrent

Current Current

Average-of-averages currentPeak-of-averages current

Time Time

0

0

0

0 0

0

0

01

1

1

1

1

1

1

1

2

2

2

2

2

2

2

2

3

3

3

3

3

3

3

3

Pea

k o

f va

lues

Ave

rag

e o

f va

lues



If your design is small and could possibly have more simultaneous activity than is represented by the vectors, you might want to use peak compression. This form of compression can be applied to larger designs as well if you increase the number of intervals by a factor of 2-3. Increasing the intervals is necessary for large designs because the finer time-stepping reduces the overestimation of IR drop resulting from bucketing activity at the same time, when in reality it occurs at different times. If you use peak compression, you should use the .ptiavg file in power-grid analysis so that you apply peak-of-average currents.

Do not use peak compression if your design contains much exclusive logic, where at most one in n components could ever operate at once. If you apply peak compression in these cases, you will predict a worst-case vector that activates all of the components at once. A common example is memories, where only a single word line might be driven at once.

Compression using averaging works well in many cases. It should not overestimate IR drop, but it can underestimate it. If you use average compression, use either the .ptimax or the .ptiavg file in power-grid analysis so that you apply average-of-peak or average-of-average currents. The opportunity to underestimate IR drop is higher if you use the .ptiavg file in power-grid analysis. The average-of-peak currents is a good data set if the time steps are small enough that the peak current in a time step does not highly overestimate the average current in the time step.

These vector compression techniques are intended to find weak spots in the power grid, and some quantitative errors may occur. Once vector compression helps you to identify a specific worst-case IR drop vector, you can analyze that vector without compression to obtain a more precise measure of the IR drop in your design.

Dynamic Analysis Flow

Dynamic analysis is the next step in complexity beyond vector-driven static analysis. The dynamic analysis flow, illustrated in Figure 4-22 on page 125, uses vectors as input to the netlist analysis performed by Thunder. It generates dynamic current data to feed into the power-grid analysis performed by Lightning. The Itaputil tool is primarily used to obtain summaries of the dynamic current data from Thunder. In advanced usage, it also extracts subsets of the dynamic tap current data and places them in a separate file.



Figure 4-22 Dynamic Analysis Flow

Performing Dynamic Netlist Analysis with Thunder

When you performed vector-based analysis in “Performing Vector-Based Netlist Analysis” on page 115, you created a file called state.ic that contained the state of the circuit after DC solution. This state file is used here. The primary difference between the previous vector analysis and the following is the replacement of the pwrnet tally and pwrnet report commands by the single pwrnet tallyint command. The tallyint option creates a dynamic tap current data set for dynamic power-grid analysis during simulation.

1. To begin the analysis, move to the following directory:


2. As an additional variation on the application here, the simulation is driven by a VCD-format input file. To use this file, copy it from the data directory:



shell> cp ../../../../data/inputs.vcd .

3. Start Thunder:

shell> thunder

4. Load the circuit file:


5. Enter the following command to tell Thunder to use the initial conditions specified in the file when you begin simulation. Simulating the circuit more than once improves the performance of DC solution on large circuits.

Thunder> use ic state.ic

6. Perform vector compression using the peak function across vectors, and compute 20 time steps in the 5-ns period:

Thunder> pwrnet tallyint method=000 intervals=20 period=5ns VDD

In this case, because simulation runs for 10 ns, two vectors are compressed into one, and each power-grid analysis time step is 250 ps wide. If you set the period on the command to 10 ns, no vector compression is performed, and the power-grid analysis time steps would be 500 ps wide. The options of this command have no impact on the accuracy of Thunder analysis; they only set the parameters for later power-grid analysis in Lightning.

7. Tally the current from the VDD source, create a Thunder. tran output file, submit a VCD-format file, and report tallied currents for VDD:

Thunder> devi tally VDD

Thunder> devi tran VDD

Thunder> vcd inputs.vcd

Thunder> devi report

This simulation generates several files. The pwrnet tallyint command creates three files: VDD.ptimax, VDD.ptiavg, and VDD.ptirms. They correspond to the peak, average, and RMS currents, respectively, for each interval of analysis. In this case, the data was compressed using the peak over the two vectors. The three files then correspond to the peak-of-peak, peak-of-average, and peak-of-RMS currents. As before, the devi tran command created the Thunder.tran file containing the transient waveform for the VDD voltage source current.

8. Exit Thunder:

Thunder> quit

9. After completing netlist analysis, run the following command:

shell> itaputil summary VDD.ptiavg

This command generates a summary of the current data in the VDD.ptiavg file. There are 20 intervals of data, and the report shows the minimum, maximum, and average current



over all transistors connected to VDD, as well as the total VDD current in that interval. If you average the total current over the 20 intervals, you can obtain a good approximation of the total VDD current reported by the devi report command. The devi report command also shows the current on VDD due to charge injection through the well, which is not associated with any specific device attached to VDD, so a difference in the total current results. This difference is discussed in “Tap Currents in Decoupled Analysis” on page 35.

10. Enter the following command:

shell> itaputil s VDD.ptimax

This command uses the abbreviated form of the summary but applies it to the VDD.ptimax file. The total current in each interval of the .ptimax file is greater than that in the .ptiavg file.

Given the dynamic current files, you are ready to proceed to the power-grid analysis.

Performing Dynamic Netlist Analysis with UltraSim

Dynamic analysis with UltraSim offers two flows:

■ It can use lumped capacitance for the signal nets for higher performance in the actual circuit simulation.

■ It can use distributed resistance and capacitance for signal nets for greater accuracy in signal timing.

These two flows are described in the following sections.

UltraSim Lumped-Capacitance Flow

The lumped-capacitance flow, which Cadence recommends, uses lumped capacitance for the signal nets. In this flow, UltraSim takes as input a circuit file output by the capdbutil utility. This circuit file contains lumped capacitance data. Thunder, in contrast, directly accepts as input a capacitance database output by Ice.

The lumped-capacitance flow takes less time than the distributed resistance and capacitance flow, but it is less accurate, since it models the capacitance and resistance as one capacitor and resistor per net.

Figure 4-23 on page 128 shows the lumped-capacitance flow.



Figure 4-23 UltraSim Lumped-Capacitance Flow

Resistanc

GDSII


Connectivity

XTC

Annotat

SPICE Stripe

Capacitan

DistR

MergeNet

RC

Power-

Ice Fire

Lightning

or

capdbut Circuit

UltraSi

Tap current data

(*.ptiavg,

Transistor




Preparing the Data for the Lumped-Capacitance Flow

The steps involved in preparing the data for a dynamic netlist analysis using the lumped-capacitance flow are as follows:

1. Gather the data required by XTC, Fire, and Ice.

2. Run XTC to generate a circuit netlist and stripes database.

3. Run Fire to generate a resistance power-grid database.

4. Run Ice to compute the capacitance data for the power and signal nets.

5. Run the capdbutil utility as follows to generate the lumped capacitance:

capdbutil summary -dir directory_name -usim -out output_file_name

where directory_name is the name of the Ice data directory, and output_file_name is the name of the file containing the lumped capacitance.

Note: UltraSim cannot directly process the capacitance data produced by Ice. The capdbutil utility can now process the Ice data to generate a lumped-capacitance file acceptable to UltraSim.

6. Run DistRC to merge the output of Fire & Ice and generate a distributed RC network of the power grid.

7. Run MergeNet on the DistRC output to convert the stripe-based format of the RC network to the layer-based format of the power grid for input to Lightning.

Running UltraSim in the Lumped-Capacitance Flow

Now you are ready to run UltraSim. For more information on UltraSim, refer to the UltraSim User Guide.

1. Run UltraSim by using the following command on the command line:

ultrasim [-f circuit] [options]

where circuit is the name of the circuit file. See the UltraSim User Guide for information on the options available.

2. Use the .usim_opt capfile command in the circuit file to specify the name of the node capacitance file containing the lumped capacitance for the signal nets:

.usim_opt capfile=lumpc.sp

where lumpc.sp is the name of the file containing the lumped capacitance for the signal nets.

3. Place the .usim_ir command in the circuit file.



This command is equivalent to the pwrnet tallyint command in Thunder for reporting the dynamic current of all devices connected to the specified voltage source during dynamic simulation. The current information is used by Lightning for dynamic analysis of the power grid connected to the voltage source.

The syntax of this command is as follows:

.usim_ir signal=signal_name start=start_time clockcycle=clock_period intervals=number_of_points cycles=number_of_cycles_for_this_measure filename=filename_for_this_measure method=[0|1|2][0|1|2][0|1|2]

This syntax contains the following parameters:

❑ signal=signal_name

Specifies the name of the signal for which voltage drop must be calculated.

❑ start=start_time

Specifies the start time of the measure.

❑ clockcycle=clock_period

Specifies the length of the clock cycle. You must specify the unit.

❑ intervals=number_of_points

Specifies the number of measurement intervals within a clock cycle.

❑ cycles=number_of_cycles_for_this_measure

Specifies the number of clock cycles for which this measure will be calculated.

❑ filename=filename_for_this_measure

Specifies the root name of the files containing the peak, average, and RMS tap currents for this measure.

❑ method=[0|1|2][0|1|2][0|1|2]

Specifies the method that UltraSim uses in post-processing clock analysis data. It is similar to the method option used by many of the clock commands in Thunder. This information might be used to reduce the amount of probe information to be calculated.

[012] The first position specifies the method of peak current calculation.

[012] The second position specifies the method of average current calculation.

[012] The third position specifies the method of RMS current calculation.

0: Reports the maximum out of each interval over all periods.



1: Reports the average out of each interval over all periods.

2: Does not calculate peak, average, or RMS current.

The default is 212.

Here is an example of this command:

.usim_ir signal=vdd start=0 clockcycle=20n intervals=20 cycles=1 filename=ms1_vdd_ir.000 method=000

UltraSim performs the current calculation by using the transistor-level netlist created by XTC in SPICE format, SPICE model files, capacitance data at various nodes, and stimuli data. At the end of its processing, UltraSim generates the same device current and capacitance files as Thunder: *.ptiavg, *.ptirms, and *.ptimax.

Example UltraSim Circuit File for the Lumped-Capacitance Flow

Following is a sample circuit file used to run UltraSim in the lumped-capacitance flow:

#top-level data for BIST

.usim_opt sim_mode=a

.options post probe accurate

.temp 25

#include the SPICE model

.lib “./log013x.l” FF

#include the netlist from XTC

.include ./bisttop.net

#include the capacitance data generated by capdbutil using Ice data


#Specify voltages and signal waveforms

vvdd vdd 0 1.5

vgnd gnd 0 0

Vclk clk 0 PWL (0 0 ...)

#include the vector file

.vec ./usim.vec

.tran 20p 10n

.usim_ir signal=vdd start=0 clockcycle=5n intervals=20 cycles=1 filename=vddir method=010

.end

Note: The net name is used in this example, but in Thunder you use the DC voltage source. Applying this example to Thunder, you would use vvdd.



UltraSim Distributed Resistance and Capacitance Flow

The second flow available with UltraSim uses distributed resistance and capacitance for signal nets. UltraSim takes as input a circuit file that you create and an interconnect database in DSPF format output by Rain.

The distributed resistance and capacitance flow is more accurate than the lumped-capacitance flow but yields a longer run time. It models capacitance and resistance per segment rather than per net, and the consequent increase in segments, nodes, resistors, and capacitors that UltraSim must process extends the run time while increasing the accuracy.

This flow is shown in Figure 4-24 on page 133.



Figure 4-24 UltraSim Distributed Resistance and Capacitance Flow

Resistanc

GDSII


Connectivity

XTC

Annotat

SPICE Stripe

Capacitan

DistR

MergeNet RC

Power-

Ice Fire

Lightning

or

Circuit

UltraSi

Tap current data

(*.ptiavg,

Transistor


Rain Interconnect

Tablege



Preparing the Data for the Distributed Resistance and Capacitance Flow

The steps involved in preparing the data for a dynamic netlist analysis using the distributed resistance and capacitance flow are as follows:

1. Gather the data required by XTC, Fire, and Ice.

2. Run XTC to generate a circuit netlist and stripes database.

3. Run Fire to generate a resistance power-grid database.

4. Run Ice to compute the capacitance data for the power and signal nets.

5. Run Fire on the signal nets.

6. Run DistRC on the signal nets.

7. Run Rain.

8. Run DistRC to merge the output of Fire & Ice and generate a distributed RC network of the power grid.

9. Run MergeNet on the DistRC output to convert the stripe-based format of the RC network to the layer-based format of the power grid for input to Lightning.

Running UltraSim in the Distributed Resistance and Capacitance Flow

Now you are ready to run UltraSim. For more information on UltraSim, refer to the UltraSim User Guide.

1. Run UltraSim by using the following command on the command line:

ultrasim [-f circuit] [options]

where circuit is the name of the circuit file. See the UltraSim User Guide for information on the options available.

2. If you want to specify the capacitance, use the .usim_opt capfile command in the circuit file to specify the name of the node capacitance file containing the lumped capacitance for the signal nets:


where lumpc.sp is the name of the file containing the lumped capacitance for the signal nets.

3. Place the .usim_ir command in the circuit file.

This command is equivalent to the pwrnet tallyint command in Thunder for reporting the dynamic current of all devices connected to the specified voltage source



during dynamic simulation. The current information is used by Lightning for dynamic analysis of the power grid connected to the voltage source.

See the “Running UltraSim in the Lumped-Capacitance Flow” on page 129 for the syntax of the .usim_ir command:

UltraSim performs the current calculation by using the transistor-level netlist created by XTC in SPICE format, SPICE model files, capacitance data at various nodes, and stimuli data. At the end of its processing, UltraSim generates the same device current and capacitance files as Thunder: *.ptiavg, *.ptirms, and *.ptimax.

Example UltraSim Circuit File for the Distributed Resistance and Capacitance Flow

Following is a sample circuit file used to run UltraSim in the lumped-capacitance flow:

#top-level data for BIST

.usim_opt sim_mode=a

.options post probe accurate

.temp 25

#include the SPICE model

.lib “./log013x.l” FF

#include the netlist from XTC

.include ./bisttop.net

#include the capacitance data generated by capdbutil using Ice data

..usim_opt capfile bist.dspf

#Specify voltages and signal waveforms

vvdd vdd 0 1.5

vgnd gnd 0 0

Vclk clk 0 PWL (0 0 ...)

#include the vector file

.vec ./usim.vec

.tran 20p 10n

.usim_ir signal=vdd start=0 clockcycle=5n intervals=20 cycles=1 filename=vddir method=010

.end

Note: The net name is used in this example, but in Thunder you use the DC voltage source. Applying this example to Thunder, you would use vvdd.



Running Lightning

The *.ptiavg, *.ptirms, and *.ptimax files generated by UltraSim are input to Lightning, along with the power-grid database generated by MergeNet. The next section tells you how to perform a dynamic power-grid analysis with Lightning.

Performing Dynamic Power-Grid Analysis

Dynamic power-grid analysis is similar to static analysis. Dynamic analysis performs a series of power-grid matrix solves, one for each time step. Currents are updated for each time step, and capacitance models are updated. The resulting states for each solve are saved automatically, as if you had entered the savestate command.

1. Change to the proper directory and perform the analysis:


shell> lightning




Lightning> filter tc 5 1e-6 1

Lightning> watch movie moviedir tc

Lightning> tran ../../thunder/dynamic/VDD.ptiavg

The initial commands given to Lightning are the same as those used in previous analyses. The filter and watch commands are used to create movie data during analysis. The last command specifies the current file to apply and initiates the dynamic analysis. As the analysis is performed, you see a report after each individual matrix solve. When the analysis is complete, a set of new files appears in your directory.

2. Look at the list:

Lightning> !ls

You see a set of files with the Lightning.tran_int prefix and a file called Lightning.worstcase. These files are discussed and used in the next section.

The CurrentScaleFactor environment variable is not set in dynamic analysis. If you set it, it would scale the currents appropriately. Some designers choose to set it just above 1.0 to slightly overestimate power currents to compensate for the averaging of peak currents resulting from taking averages either within each time step or across vectors in compression.

You cannot apply the scalecurrents command in dynamic analysis because the command only applies to static currents already loaded.



You can set up filters to generate plots and reports during dynamic analysis. However, this procedure is only useful for tap current movies, because the range of values of other analysis types is unknown until after analysis is complete. In the next section, you create a movie of the design’s behavior after analysis.

Viewing Dynamic Analysis Results

You can now examine the results of the dynamic analysis. This section explains how to set the filters and how to create and replay a movie.

Output of Dynamic Analysis

The output of dynamic power-grid analysis is unique: a movie of the behavior of the power grid over the time intervals of analysis. You can examine plots and reports of individual states just as in static analysis, but the sequencing of these states in a movie format adds more value to the analysis.

The tran command computes the state of the power grid after each time step during analysis. These states are saved in a set of files sequentially numbered beginning with Lightning.tran_int0. You can load each of these states individually by using the loadstate command and generate plots and reports of these individual states, as described previously. The most valuable saved state created during dynamic analysis is the Lightning.worstcase state. It contains the worst-case voltage over dynamic analysis for each subnode in the power grid, so you can examine a single file to determine the worst IR drop occurring in dynamic analysis.

The next section shows you how to use the saved states to create a movie of your power-grid behavior.

Applying Filters to Dynamic Analysis

Applying filters in Lightning to create a movie is best performed using the worst-case voltage state after dynamic analysis. This file was created during dynamic analysis and therefore provides a good basis for setting the filters.

1. Load this state into Lightning:

Lightning> loadstate Lightning.worstcase

2. Set the IR drop filter maximum values to the following:


❑ Filter 2 to 3.1




❑ Filter 4 to 3.2



Now use this state along with the algorithm given in “Recommended Analysis Design Flow” on page 103 to create a set of filters for IR drop and resistor current plots. Use the worst-case file for this filter setting, because it determines the maximum amount of data that will be displayed in any single frame of movie generation. Most frames plot small amounts of data.

Figure 4-25 on page 138 shows the plot resulting from the application of these filters.

Figure 4-25 IR Drop Plot Resulting from Worst-Case State Analysis

Figure 4-26 on page 139 shows the resistor current plot from this data as well.



Figure 4-26 Resistor Current Plot Resulting from Worst-Case State Analysis

Making Movies

After setting the filters as instructed in the previous section, you are now ready to create a movie of the IR drop and resistor currents. You must first tell Lightning for what types of analysis you want to create a movie. In this case, you use IR drop and resistor current. You can create movies of tap currents only with the tran command, as shown earlier. Any attempt to create a movie of tap currents after you enter the tran command displays no data and eliminates the previous data. The watch command tells Lightning how you want to create reports, where you want the reports saved, and what information you want the reports to contain. In this case, you want to create a movie, store it in a directory called moviedir, and create movies for IR drop and resistor current. Once this directory is set up, you can create the movie.

1. Type these commands:

Lightning> watch movie moviedir ir rc

Lightning> makemovie Lightning.tran_int 0

The makemovie command loads each state, performs the analysis, and saves the data in the moviedir directory. When it finishes, you can load the movie and watch it.



2. Before you can watch a movie, you must first load it into the movie viewer. Type the following:

Lightning> loadmovie moviedir ir

The movie window appears on the screen, and you see each frame load in a movie clip view. When each one is loaded, you can use the scroll bar to scan the clips. The first clip is of the power grid itself.

3. To watch the movie, press the play button at the top.

Each frame appears in order. The frames with the largest IR drop are typically those in which the clock switches. When the movie finishes, you can use the forward button to single-step through the frames so that you can study each individually.

You can also examine a frame more closely from the clip view by double-clicking on the frame of interest.

4. To load the resistor current movie interactively, select Load Movie – Resistor_Current.

5. Select OK when the dialog box appears.

The resistor-current (rc) movie data is loaded in. You can now play the movie and examine the frames more closely.

To study a specific frame in further depth than the movie shows, select that frame and use the State menu to load that state into Lightning to apply further filters.

You have now performed both static and dynamic analysis on the tutorial circuit.

PGS Exploration

VoltageStorm’s power-grid exploration capability enables you to optimize the power grid or correct a problem in it. You can experiment with power-grid changes, such as adding or changing vias, voltage sources, or resistors, then perform power-grid analysis to show the effects of these changes on the power grid.

When to Use PGS Exploration

Power-grid layout changes are easier to complete if none of the signal routing is completed, so you should consider using PGS Exploration while creating your power networks. PGS Exploration is available once you have placed all cells and transistors and have a complete physical power network. You do not have to wait until you have completed signal routing.



Because you can easily explore the effects of changes to a power-grid network, you can determine if you have overdesigned the power grid. Although some overdesign is necessary, significant overdesign decreases the available signal routing area, wasting valuable die area. PGS Exploration lets you rapidly understand the consequences of reducing or increasing power route widths, so you can adjust your power-grid design to your requirements.

Note: If you have already completed any signal routing, always use engineering judgment when using PGS Exploration. It is possible to make changes to the power-grid network in VoltageStorm that would be impossible to implement in a physical layout. For example, increasing the width of a 20-micron power-grid wire 10 times is likely to be impractical in layout if signal routing already exists.

How to Use PGS Exploration

Once you load the power grid and tap currents into VoltageStorm, you can use PGS Exploration.

Modify the power-grid resistor network as desired. When you want to understand the effects of the changes, simply perform a power-grid solve. Since there is no limit to the number of modifications that you can make or the number of times that you can perform a power-grid solve, simply continue to repeat the modification and solve steps until the power grid is clean.

When you are satisfied that your power-grid design is acceptable, write out the change report from VoltageStorm and use it as a guide for implementing the changes in layout.

The change report contains a summarized list of the changes made to the power grid. The changes are made to resistors within VoltageStorm; however, the change report is written in layout format, which contains width, length, layer, and coordinate information that enables a layout designer to easily implement the required layout changes to the power grid. To avoid redundant layout changes when a resistor is modified more than once, the change report lists only the final modification.

PGS Exploration Commands

PGS Exploration includes the following commands:

■ addres, which adds a resistor to the power grid

■ changeres, which modifies an existing power-grid resistor (or resistors)

■ addvia, which adds a new via to the power grid

■ addvsrc, which adds a voltage source to the power grid



■ show, which displays the selected nodes or elements

■ unselect, which deselects single or multiple nodes or elements

■ write, which writes out the change report

Most of these commands allow you to modify the power-grid network, typically by first selecting the object to modify, then executing the change command.

Selecting Objects

You can use a number of methods to select objects for modification:

■ You can select objects interactively by using the middle mouse button and drawing a selection box over the area to be selected. To be selected, an object must be completely inside the selection box.

■ You can also select objects by using the select command.

■ You can select resistors interactively by clicking on them with the middle mouse button.

■ You can select nodes interactively by clicking on them with the left mouse button.

Using PGS Exploration

To use PGS Exploration, follow these steps:

1. Move to the directory containing the VDD power-grid database:

shell> cd ../static

2. Run Lightning:

shell> lightning

3. Load the power-grid database into Lightning:


4. Add four voltage sources to the power grid (one at each side of the design: top, bottom, left, and right):


At this point, you will see four white spots representing voltage sources at each corner of the power grid (see Figure 4-27 on page 143).



Figure 4-27 View of Power-Grid Within Lightning

5. Load the tap currents into Lightning:


6. Scale the loaded currents down by a factor of 100 to more accurately reflect total current draw:

Lightning> scalecurrents global relative 0.01

Lightning reports the old and new total currents after the scaling is completed.

7. Solve the power grid:

Lightning> solve

Note: You can also use the Analysis – Perform steady-state analysis command on the pulldown menu to activate a solve.

Lightning now performs a static solve of the power grid.

8. Use the auto-filtering to define the filter ranges for IR drop, and display the IR drop in the Lightning plotter window:

Lightning> filter ir auto

Lightning> plot ir

Notice the large IR drop in the left side of the central control section. It occurs because the power routing to this block comes only from the right side.

9. To explore solutions to this large IR drop, add a resistor on the METAL_1 layer to connect the upper row of the control block.



First zoom in on the upper left corner of the central control by using the left mouse button to draw a box from the lower left to the upper right around the area.

10. Select a node in the control block and in the circuit above it.

Select a node by either clicking on it with the left mouse button or entering the following commands if you know the node coordinates:

Lightning> select n 407327 979001

Lightning> select n 405361 1049772

Note: You can obtain the coordinates of any object by moving the cursor over the object and monitoring the X,Y coordinates in the upper right corner of the Lightning interface.

11. Now add a resistor between the selected nodes:

Lightning> addres selected 1000

This step adds a resistor with a width of one micron (1000 units) between the two selected nodes, displayed in white. The resistance of this resistor is automatically calculated from the process technology information.

12. Repeat steps 10 and 11 to add a second resistor to the adjacent nodes.

13. Deselect anything that is currently selected:

Lightning> unselect all

14. Solve the circuit again and re-plot the IR drop:

Lightning> solve

Lightning> plot ir

The top row of the control block displays a decreased IR drop.

15. Now remove the added resistor from the power grid, re-solve, and re-plot the IR drop:

Lightning> addres undo

Lightning> solve

Lightning> plot ir

The IR drop on the top row returns.

16. To see if you can correct the IR drop by simply increasing the width of METAL_1, increase the width of METAL_1 in the control block.

First, use the zoom reset command to make sure that you are viewing the complete database:

Lightning> zoom reset

Note: You can also perform a zoom reset from the Lightning graphical user interface by using the ZR button in the upper right.



Use the middle mouse button to draw a box that encloses the central block (coordinates will be approximately 340000,60000 to 2500000,1000000).

The Which/Scalecurrents/Measure dialog box appears.

17. Select the Change Resistors command in the dialog box, select the METAL_1 layer, and specify a scale factor of 3.0. Click on OK to effect the change.

Lightning reports the change command that you issued from the dialog box approximately as follows:

Lightning> changeres area 340000 60000 2500000 1000000 METAL_1 3.0

You have now increased the width of all METAL_1 resistors in the control block by a factor of 3.

18. Solve the circuit and re-plot the IR drop:

Lightning> solve

Lightning> plot ir

You now see that the IR drop for the control block has been reduced, meaning that a significant amount of the IR drop was caused by the resistance of the METAL_1 layer.

19. Having modified resistances in the power grid, verify that the current density limits have not been exceeded. Use auto-filtering to set the filters for the current density, and plot the current density (RJ) errors.

Lightning> filter rj auto

Lightning> plot rj

The red color in the upper right corner indicates that the current density has exceeded the limits.

20. Change the width of the resistor in the upper right corner by a factor of 5.0 (remember that you can select a resistor by simply clicking on it with the middle mouse button), deselect all, solve the circuit, and replot the current density errors:

Lightning> select r 2849381 1705496

Lightning> changeres selected 5.0


Lightning> solve

Lightning> plot rj

You will see that changing the width of this resistor by 5 made a significant improvement in current density, as expected.

21. Re-plot the IR drop:

Lightning> plot ir

22. Generate a report of all changed resistors:



Lightning> changeres report

This report lists all resistors that have been changed.

23. Generate a report of all added resistors:

Lightning> addres report

24. The added resistor at the top left of the control block is no longer needed, so you can now delete it. Select it by using the middle mouse button and enter the following commands:

Lightning> changeres selected delete

Lightning> erase show


Note: To remove the resistor from the display, you must use the erase show command, which highlights the selected objects in white.

25. Now write out the change report to guide the layout changes:

Lightning> write gridchanges tutorial.eco

This step creates a file named tutorial.eco that contains all the commands that made changes to the power grid during this session.

26. Having completed your exploration session, you can either save the database using a save state command, or reset all modifications to the power grid.

27. To understand how the reset functionality works, use the following commands to reset all changed and added resistors, solve the circuit, and replot the IR drop.

Lightning> changeres reset

Lightning> addres reset

Lightning> solve

Lightning> plot ir

The IR drop will revert to the state that it was in when you first started—a large IR drop in the left of the control block.

28. Exit Lightning by typing the following:

Lightning> quit

Static PGS for Mixed-Signal Designs

Static power-grid signoff (PGS) for mixed-signal designs has always been a challenge because there is no easy way to define the current draw for analog blocks and cells. The existing mechanisms in VoltageStorm that estimate the current consumed by the devices connected to the power grid are primarily designed for digital designs and do not necessarily provide a good approximation for analog circuitry.



Like pure digital designs, however, mixed-signal designs are equally prone to unexpected voltage drops and electromigration on the power grids.

VoltageStorm now includes additional functionality to enable you to verify power grids of mixed-signal designs through static power-grid analysis.

Overview

Most mixed-signal designs do not intimately mix analog and digital circuitry. In a majority of cases, they keep the analog sections of the design separate from the digital for both logical and physical design phases.

In a typical layout hierarchy of a mixed-signal design, analog and digital circuitry are instantiated as separate blocks within the layout, as shown in Figure 4-28 on page 147.

Figure 4-28 Mixed-Signal Design Containing Separate Blocks

VoltageStorm uses this instantiation to enable static power-grid analysis of mixed-signal designs by allowing you to specify, on a block-by-block basis, how much current is drawn by a specific block, and how that current is to be distributed across the devices of that block (see Figure 4-29 on page 148).

Digital blocks

Analog blocks



Figure 4-29 Power Consumption by Analog Blocks

Performing Static PGS for Mixed-Signal Designs

Within VoltageStorm, Thunder calculates transistor tap current information by using the design’s netlist and SPICE models, then outputs these tap currents to Lightning for attachment to the power-grid network.

In the case of analog blocks, you must give Thunder information on the total current consumption for each block and on how to distribute that current throughout the block.

Running Thunder

To run Thunder, follow this procedure.

1. Move to the thunder directory and create a new directory named mixed by copying the static directory:

shell> cd ../

(You should now be in the SPARCDSP/flat/thunder directory.)

shell> cp -r static mixed

2. Move into the mixed directory and copy the run.cmd file from the original data directory into the current directory:

shell> cd mixed

shell> cp ../../../../data/run.cmd .

3. Remove the old VDD.ipeak file (you will be creating new ipeak files):

Analog block #1 = 1.5 mAdistributed across 1000 devices

Analog block #2 = 3 mAdistributed across 250 devices

Analog block #3 = 0.5 mAdistributed across 100 devices



shell> rm VDD.ipeak

4. Edit the run.cmd file:

shell> vi run.cmd

5. Examine the contents of this command file:

*Thunder command file

load sparcdsp.ckt

pwrnet ipeak file=vdd_normal.ipeak vdd

pwrnet specify DEF = D_INCR_4_LC_380 current= 100.0ma

pwrnet specify INST = Xovo current = 35.0ma

pwrnet specify DEV = Xovo.Ma803 current = 5.0ma

pwrnet ipeak vdd

stats

Note: The instance and device names given in the example of the run.cmd file are subject to change whenever there is a new release of XTC. If Thunder issues a warning or error message regarding the instance or device name, obtain the current instance and device names from the netlist generated by XTC.

The command file is simple, containing commands that do the following:

❑ Load the circuit into Thunder

❑ Direct Thunder on what type of analysis to perform

❑ Inform Thunder of the specific current consumption for named blocks and/or devices

Observe the powernet specify command, which defines what total current consumption numbers to use for named blocks, instances, or devices. This current value is used during static power-grid analysis.

For example, given the command file just shown, you can see that:

❑ All instances of block D_INCR_4_LC_380 have a current of 100 mA.

❑ One specific instance of this block has a current of 35 mA.

❑ One specific device of this instance has a current of 5 mA.

Thunder calculates the tap currents for all other blocks, instances or devices.

Note: This functionality is not limited to analog circuitry. If you have a digital circuit to which you want to pre-assign a current consumption number, you can also use the pwrnet specify command.



6. Edit the sparcdsp.ckt file and change it to define a mixed-signal flow (comment out the lines for static analysis and un-comment the lines for mixed-signal analysis), then save the file:


7. Start Thunder on the command line by using the run.cmd command file:

shell> thunder.tty run.cmd

After Thunder has finished, you see two output files for VDD:

❑ vdd.ipeak contains the normal tap current information for VDD, based on the calculation of IDS for each transistor.

❑ vdd.aipeak contains the tap current information for the blocks, instances, or devices for which total current consumption is defined by the pwrnet specify command.

8. You can take a more detailed look at these tap currents by running Itaputil (to create ASCII output) as follows:

shell> itaputil a vdd.aipeak > vdd.aipeak.asc

shell> vi vdd.aipeak.asc

As you scroll down, you will notice that all the devices have the same current values, except for the devices near the bottom (beginning with Mxev.ajih.aupb). These devices have slightly lower currents.

The tap currents in this file are for transistors contained within instances of block D_INCR_4_LC_380. Most of the devices have the same current, because the current was evenly distributed from current consumption numbers defined by the pwrnet specify commands.

For each instance of the block named D_INCR_4_LC_380, set a current consumption value of 100 mA. Since this block contains 27 transistors, each transistor is assigned a current of 3.7037 mA.

The instance named Mxev.ajih.aupb was explicitly assigned a current of 35 mA. This current has also been evenly distributed throughout the 27 transistors, so each transistor in this instance is assigned a current of 1.2963 mA.

Finally, one device, Mxev.ajih.aupb.a1027, has a current of 5 mA. This device was explicitly set to have a consumption of 5 mA in the command file.



Performing Ipeak Analysis

To understand the difference between executing power-grid analysis using automatically calculated tap currents and using the pwrnet specify command, you will compare two different power-grid analyses.

First, you will run Lightning on the traditional ipeak file containing tap current information automatically calculated by Thunder.

Then you will run Lightning by using the combination of ipeak and aipeak files to see the effect of defining currents using the pwrnet specify command.

1. Go to the Lightning directory and create a new directory named mixed by copying the static directory:

shell> cd ../../lightning

(You should now be in the SPARCDSP/flat/lightning directory.)

shell> cp -r static mixed

2. Move into the mixed directory and copy the run1.cmd and run2.cmd files from the original data directory into the current directory:

shell> cd mixed

shell> cp ../../../../data/run1.cmd .

shell> cp ../../../../data/run2.cmd .

3. Before running Lightning, take a look at run1.cmd to see what commands you are going to run:

shell> vi run1.cmd

This command file loads the circuit, sets the filters, and loads the tap currents from the vdd_normal.ipeak file.

4. Now execute Lightning:

shell> lightning run1.cmd

You just loaded the power grid, loaded the current tap data that you generated in Thunder, scaled the ipeak data down to more reasonable levels, and solved the matrix.

Before you look at the IR drop, focus a bit more on the current taps.

5. In Lightning, select Settings – Filter to activate the Filters dialog box, and set the analysis type to Tap_Current.

6. Switch off filters 4-8 so that only filters 1, 2, and 3 are on.

7. Select OK and plot the tap current information by using the following command:

Lightning> plot tc



8. Observe where these higher tap currents are located and record how many fall into which filter ranges in the Lightning control window.

9. Save the image so that you can make a comparison later:

Lightning> image save tc.gif

10. Now look at the IR drop:

Lightning> plot ir

Closely observe the IR drop, where the greatest IR drop occurs, and again the number of nodes that fall into each filter range.

11. Save this image also for later comparison:

Lightning> image save ir.gif

Performing Ipeak Analysis Using Analog Ipeaks

You will now re-run Lightning by using the tap current data generated for those devices by the pwrnet specify command on specific blocks, instances, or devices.

1. Use an available terminal to look at the run2.cmd file:

shell> vi run2.cmd

Load the normal data first (vdd.ipeak), and scale it to a reasonable value before loading the tap current data generated for the devices controlled by the pwrnet specify command (vdd.aipeak).

2. Run Lightning with this command file:

Lightning> run run2.cmd

You will see the current tap data for filters 1-3.

3. In a shell window, use the xv utility to bring up the saved GIF image from the first run, and position the window so you can easily compare it with the Lightning plotter window:

shell> xv tc.gif &

Note: Watch for color map problems with the two images. To make sure that you are always observing the correct colors, keep the cursor in the window of interest.

4. Note the differences.

Notice the number of current taps falling into the filter ranges.

See how filter ranges 1 and 2 now contain elements, but before they did not.

5. In the Lightning plotter window, observe that a whole set of devices in the upper right are now flagged. Zoom in to take a closer look.



6. Using the middle mouse button, drag a selection box over some of the taps currently highlighted. When the Which/Scalecurrents/Measure dialog box appears, select the Which command and press OK.

Lightning reports information on the selected tap currents. Observe that the instance names are those on which you used the pwrnet specify command and that some of the tap currents have a familiar value (3.7073 mA).

Note: In some cases—when parallel devices drive the same node through diffusion only—multiple individual tap currents are merged into a single tap current to conserve memory. In the tap current report that you just ran, the tap currents reported as 7.4074 mA are actually a combination of two (3.7073 mA) tap currents.

7. When you have finished, select zoom reset (ZR).

8. Now plot the IR drop and again use xv to bring up the image from the first run to compare:

Lightning> plot ir

shell> xv ir.gif &

See how the voltage drop has changed. The maximum voltage drop is now larger in the middle block; however, there is slightly more voltage drop in the top region than before.

9. When you have completed your observations, quit Lightning:

Lightning> quit

Conclusion

You have now seen how you can assign a current consumption number to blocks, instances, or devices. This procedure enables you to verify a mixed-signal design and to sign off its power grid by using static power-grid analysis.



AStormCenter

This appendix describes StormCenter™, Cadence’s interactive waveform viewer. You use StormCenter to examine a dynamic analysis created by VoltageStorm Transistor-Level PGS at different magnifications.

Starting StormCenter

To start StormCenter, enter the following at a shell prompt:

shell> storm

Note: If you have not set your path variable, enter this instead:

$(SIMPLEX_HOME)/bin/arch/storm

where arch is your platform’s architecture.

A blank StormCenter window appears, as shown in Figure A-1 on page 156. You can resize this window as you choose.


VoltageStorm Transistor-Level Rail Analysis User GuideStormCenter

Figure A-1 Blank StormCenter Window

Viewing a Waveform

To view the results of a power-grid current analysis in StormCenter, follow this procedure:

1. In the StormCenter window, either select File – Open File or click the Open File button.

The File Selection dialog box appears.

2. Select a power net dynamic current file from the list of files, or type in your file selection.

Here, the selected file is storm.tran.

3. Click the OK button or press Return.

StormCenter reads in the data from the storm.tran file but does not plot it; you can load several data files in StormCenter.

4. Click the New Plot button.

Wav

efor

m a

rea

Time-axis window



The Select Signals dialog box appears, as shown in Figure A-2 on page 157.

Figure A-2 StormCenter Select Signals Dialog Box

StormCenter lists each available signal by file name, followed by an internal version number and the name of the signal. All available signals are listed unless a filter is specified. The filter



is a regular expression entered in the space next to the Filter button. When the user clicks the Filter button the list of available signals is filtered according to the regular expression specified.

To view signals as separate plots, do the following:

1. To select a signal to plot, click on that signal name in the Available Signals selection box.

To select additional signals, click those signals while holding down the Ctrl key.

To select all signals, select the first signal and drag the cursor to the end of the list.

2. When you have selected the desired signals, click on the Plot Selected button.

To view multiple signals overlaid on a single plot, follow these steps:

1. To select a signal to plot, click that signal name in the Available Signals selection box.

To select additional signals, click those signals while holding down the Ctrl key.

To select all signals, select the first signal and drag the cursor to the end of the list.

2. Click the Add to Selection button.

StormCenter copies the selected signal names to the Selected Signals window.

To remove any signals from the Selected Signals window, highlight the signal name in that window and click the Remove from Selection button.

3. When all the signals that StormCenter is to overlay are in the Selected Signals window, click on the OK button.

Figure A-3 on page 159 shows a power-grid analysis that includes a waveform display of a power-grid analysis for the sample circuit in storm.tran.



Figure A-3 Waveform Display for Sample Circuit

The dashed-line box in the fourth waveform window indicates a violation.

Zooming and Panning

Use the Zoom In and Zoom Out buttons to magnify or shrink the view of a waveform.

Figure A-4 on page 160 shows a zoomed-in view of Figure A-3 on page 159.



Figure A-4 Zoomed Waveform Segment

Click on Zoom Reset to bring the image to its default size.

Use the Pan buttons or the scroll bars to the left and at the bottom to move around.

Try setting your own time markers and using them to zoom:

This section of thewaveform display...

...expands and flattens slightly.



1. Click the left mouse button in the Time Axis window, which is the window just above the scroll bar at the bottom. Use the left mouse button to click and drag the resulting marker anywhere in the plot, or click anywhere in the plot to move this marker there quickly.

2. Now click the middle mouse button in the Time Axis window. Use the middle mouse button to click and drag the resulting marker anywhere in the plot, or click the middle mouse button anywhere in the plot to move this marker there quickly.

It does not matter which marker is to the left and which is to the right. By default, the first marker that you create is green; the second marker that you create is red.

Figure A-5 on page 161 shows the zoomed-out view of the picture in Figure A-4 on page 160 with two markers now in place.

Figure A-5 Zoomed-Out View with Two Markers

In each row, the values shown in the signal value window now indicate the value of that waveform at the points intersected by the markers. The color of each value corresponds to the color of that marker.

Marker One Marker TwoIndicates timebetween markers



3. Click the right mouse button in the Time Axis window. A menu appears with the following options:

Zoom Between Markers

Zoom Reset

Goto Time

Goto Mark One

Goto Mark Two

4. Select Zoom Between Markers. The view zooms to show the area between your two markers. Figure A-6 on page 162 shows the zoomed-in view between the markers shown in Figure A-5 on page 161.

Each Goto option moves the view to the point that you specify. When you select Goto Time, you specify the time in a dialog box. Zoom Reset zooms the view out to show the entire waveform.

Figure A-6 Zoomed Waveform Display Between Markers



Adding Labels

You can add fixed or time/value-based labels to the waveform.

1. Control-click the point at which you want to place a label. It can be anywhere in any window that contains waveform data.

The Label Options dialog box appears, shown in Figure A-7 on page 163.

Figure A-7 Label Options Dialog Box

2. Enter the text for a label.

The Label Options dialog box appears with the Time, Value, X Position, and Y Position fields showing information for the point that you clicked in the window. You can change those:

❑ Use the Timed Label option to create a label that is locked in position relative to the timeline. This label is the default. A timed label moves to stay with its point on the timeline regardless of how you use the Zoom or Pan buttons. When the Timed Label option is on, only the Time (horizontal value on the timeline) and Value (vertical value on the waveform) fields are available.

❑ Use the Fixed Label option to create a label that is locked in position relative to the waveform window. A fixed label remains where you place it regardless of how you

Enter a labelhere



use the Zoom or Pan buttons. When the Fixed Label option is on, the X Position and Y Position fields are available.

Figure A-8 on page 164 shows a timeline label in the fourth waveform window.

Figure A-8 Waveform Window Showing New Label

Editing Signals

Click the signal name window, shown in Figure A-3 on page 159, to highlight that window. Now right-click anywhere in that window to obtain a menu of actions that affect only that plot.

■ Edit Signal

Modifies the signals that StormCenter displays on the selected plot, or changes the color or line styles of signals on the plot. When you click on Edit signal, StormCenter displays the Select Signals dialog box, shown in Figure A-2 on page 157. To edit a signal, follow these steps:

a. Select the individual signal of interest in the Select Signals box.

b. Click on the Options button.

The Signal Editing dialog box appears.

c. Select the line type and choose a color that you wish to apply to the signal.

d. Click on OK.

The Signal Editing dialog box disappears and you return to the Select Signals dialog box.

■ Edit Labels

Changes existing labels.

■ Cut

The label appears whereyou clicked.



Moves the selected plot to an internal clipboard.

■ Copy

Copies the selected plot to an internal clipboard.

■ Paste Before

Pastes the contents of the internal clipboard before the selected plot.

■ Paste After

Pastes the contents of the internal clipboard after the selected plot.

■ Delete

Removes the selected plot without changing anything currently in the internal clipboard.

Resizing Plot Windows

Resize the plot window by following these steps:

1. Click the left mouse button on the line between the top two plots.

2. While downholding the button, move the mouse up and down to move the relative location of that plot line.

3. With the button in a new part of the window, release the button. You have resized the plot window for that signal.



BPreparing to Use VoltageStorm Using QRC

This chapter describes how to generate the data required to run VoltageStorm Transistor-Level Rail Analysis using QRC. The QRC interface is preferred over the Fire and Ice interface, described in Chapter 3, “Preparing to Use VoltageStorm”, for the following reasons:

■ Adds the ability to support manufacturing effects (130nm, 90nm, 65nm, and less).

❑ Wire edge enlargement (WEE)

❍ Modeled as a function of drawn width and drawn spacing

❍ Separate modeling of resistance and capacitance

❑ Erosion modeled as a function of metal density

❑ Metal fill

❍ Handles both floating and grounded metal fill

❍ Predictive fill provides an approximation of the effect of metal fill

❑ Resistance I - Modeled as a function of sheet resistance which varies with drawn width.

❑ Resistance II - Modeled as a function of resistivity and rho (varies with drawn width and spacing)

❑ Thickness variation (Erosion and etching)

❍ Modeled as a function of metal width and effective density

❍ Moved from a 1 dimensional to 2 dimensional table

❍ Support of polynomial equations for flexibility

❑ Resistance degrading - Modeled as a function fo temperature and width

■ Removes the requirement for running XTC and Fire and Ice which are not as well supported.


VoltageStorm Transistor-Level Rail Analysis User GuidePreparing to Use VoltageStorm Using QRC

Required Data

Because VoltageStorm offers a variety of power-grid analysis methodologies, the exact list of inputs required depends on the specific methodology that you use. If you are a beginner, start with the simplest method to become familiar with VoltageStorm’s operation. As you learn more about its capabilities and the ways that it can help you find power-grid problems, you can venture into the more sophisticated methodologies.

All power-grid analysis methodologies require three specific data sets:

■ A design circuit file—for example, sparcdsp.ckt—that defines the input sources to be used for the analysis

■ The extracted power-grid resistance network to be analyzed

■ Model data with which is used to compute transistor currents

These three data sets are shown in Figure B-1 on page 170.

More advanced flows require the computation of signal and power-grid capacitances. Some flows also require the creation of node name match files or transistor name match files. The most complex preparation flow for VoltageStorm is shown in Figure B-2 on page 171.

Power-Grid Analysis Methodologies

There are three power-grid analysis methodologies; static worst case, static activity-based, and dynamic. Data preparation will need to be done according to which of these methodologies are being used (See Table B-1 on page 169).

The most basic power-grid analysis flow is the static power-grid analysis based on peak saturation transistor currents. This type of analysis is commonly called Ipeak analysis. Because of its simplicity and ability to find problems quickly in power grids, it is usually the first VoltageStorm flow used.

Activity-based analysis is another approach to static analysis that better resolves the distribution of currents on your power grid. The activity-based approach assumes that you have a mechanism such as a Verilog simulator to compute and report the relative activity of the nets in the design. These relative activities can be used in conjunction with net capacitances to estimate the average current load of each gate in the design. This form of analysis clearly provides more realistic power current data than the ipeak approach.

Dynamic analysis supplements static analysis by providing more precise insight into the behavior of the power grid. Static analysis averages tap currents to look at the long-term average behavior of the power grid. Dynamic analysis keeps the time distribution of current




in place so you can see the voltage and current waveforms in a more numerically precise sense. It provides better visibility into the magnitude of the IR drop.

Each of these analysis types are described in great detail in the chapter “Using VoltageStorm” on page 73.

Table B-1 Power-Grid Analysis Methodologies

The trade-offs in terms of turnaround, precision and capacity among these three methodologies are shown in Table B-1 on page 169.

Table B-2 Power-Grid Analysis Methodologies Trade-offs

Analysis Type Static - worst case Static activity-based Dynamic

Extraction Needs

Powergrid: Ronly

Signals: none

Powergrid: R only

Signals: C/Cload

Powergrid: RC

Signals: C (or RC) + Cload

Tap Current Idstat Iavg Piecewise linear (PWL)

Analysis Type Static - worst case Static activity-based Dynamic

Turnaround fast slower slowest

Precision least accurate more accurate most accurate

Capacity greatest less least


Figure B-1 Minimum Extraction Required for Static Power-Grid Analysis

* See Running QRC with Calibre Input chapter of QRC Extraction Users Manual for details on preparing Calibre for input to QRC.

Assura LVS Assura LVS

Flat/hierarchicalSPICE netlist

Powergrid DBfor selected

Transistormodeldata

QRC

Tablegen

CircuitFile

Calibre*

Assura LVS

Vldb dabaseExtracted database

Difference filesCross reference tables

Reports

power nets

Thunder or UltrasimTransistor Simulationand Analysis Engine

VoltageStorm Power-Grid Signoff

LightningPower-Grid

Analysis

extract.rul

RSF file

Calibre flow

Techology

QRC

Data

RSF file

QRC

Assura Flow

Designin GDSII



Figure B-2 Maximum Extraction Required for Dynamic Power-Grid Analysis

* See Running QRC with Calibre Input chapter of QRC Extraction Users Manual for details on preparing Calibre for input to QRC.

Assura LVS Assura LVS

Flat/hierarchicalSPICE netlist

Powergrid DBfor selected

Transistormodeldata

QRC

Tablegen

CircuitFile

Calibre*

Assura LVS

Vldb dabaseExtracted database

Difference filesCross reference tables

Reports

Lump C SPEFfor all nets**

power nets

Thunder or UltrasimTransistor Simulationand Analysis Engine

VoltageStorm Power-Grid Signoff

LightningPower-Grid

Analysis

TechologyData

QRC

extract.rul

RSF file

Assura FlowCalibre flow

Designin GDSII

QRCRSF file



** To include SPEF one must add the following command in the circuit file that is input to Thunder:

.spef file-name

PowerGrid Analysis Flow.

In this section, you step through the data preparation flow shown in Figure B-1 on page 170, followed by the addition of capacitance computation for dynamic analysis. The results of this data preparation are used in Chapter 4, “Using VoltageStorm.”

Directory Structure

Cadence recommends that you use a common directory structure when you use its extraction and analysis tools to run different flows. This directory structure, used by the Cadence flow scripts, prevents any confusion that may arise from running several tools in a single directory. Figure Figure B-3 on page 172 shows the recommended directory structure for the sample design used in this chapter.

Figure B-3 Typical Design Directory Structure in Using VoltageStorm

working directory

dataDesign Name

Thunder/Ultrasim lightningQRC

tablemodels static staticdynamic dynamic

moviedir



In this directory structure, the directories perform the following functions:

■ The data directory stores the source data for the design being run.

■ The Design and subdirectories store the specific data created in the execution of the flows in this chapter as well as those in Chapter 4, “Using VoltageStorm.”

■ The tablemodels directory is where Tablegen stores tabular data for device models.

■ The Thunder/Ultrasim directory is where Thunder or UltraSim analyzes the transistor netlist. The static and dynamic subdirectories separate the runs for different flows because the circuit files are different for each case.

■ The lightning directory is where Lightning analyzes the power grid. The static and dynamic subdirectories separate the different data between static and dynamic flows because static flows do not require capacitance data in the power grid. If you create a power grid for dynamic analysis, this grid can also be used for static analysis.

■ The QRC directory is where the data is prepared for powergrid analysis.

Flows to prepare data for input to QRC

There are two flows to prepare the data for QRC:

1. Assura LVS flow

2. Calibre

See Running QRC with Calibre Input chapter of QRC Extraction Users Manual for details on preparing Calibre for input to QRC.

For the Assura LVS flow three inputs are needed:

1. Design in GDSII format.

2. Assura run specific file (RSF).

3. Rules files that contain technology specific design rules (extract and basic compare rules).

The below Assura LVS information only covers the minimum needed for QRC-VST flow. For additional information see the Assura LVS documentation.

Assura LVS Run Specific file (RSF) Input

The Assura RSF consist of several sections:



❑ A mandatory avParameters section that sets run-time options for Assura DRC and LVS (Input layout/rule files/global RSF options).

❑ One or more avCompareRules sections that specify controls and rules for an LVS run (Input schematic/binding file/other rules and options)

❑ An rcxParameters section that sets run-time options for an RCX run.

❑ Optional statements ouside the above sections.

❑ One or more mandatory Assura tool invocation commands

avDRC, avExtract, avDX, avNX avNVN, avLVS and avRCX

The following are some inportant avParameters:

❑ ?technology

Specifies where the technology information is such as rule files.

❑ ?inputLayout

Specifies the input data format and the input data filename of the layout data.

❑ ?cellName

Specifies name of the cell you want to analyze

❑ ?viewName

Specifies the view.

❑ ?techLib

Specifies the location of the technology mapping file to be used for the run.

❑ ?joinPins

Specifies under what conditions virtual connections can exist between labels with identical names.

❑ ?diskLIst

Lets you specify disks to be used by the run. You can limit the amount of space used on a given disk. Files are limited to 2GB.

❑ ?multiCPU

For multi CPU runs.

❑ ?textPriOnly



Determines whether or not to process only the text in the top cell.

❑ ?runName

Specifies the name of the run.

❑ ?workingDirectory

LVS results directory

Below is an example Assura LVS RSF file.

joinableNet()

avParameters(

?inputLayout ( "gds2" "../data/ARM_128x32.gds2" )

?cellName "ARM_128x32"

?viewName "layout"

?techLib "./assura_tech.lib"

?runName "ARM_128x32"

?workingDirectory "./lvsdir"

?technology "tech_dir"

?avrpt t

?textPriOnly t

)

avCompareRules(

schematic(

netlist( cdl "../data/ram.cdl" )

)

)

avDX()

avNX()

Some of the important settings to understand in the above RSF example are:

❑ The top cell name is ARM_128x32

❑ The ARM_128x32.gds file is located in the data directory

❑ The dummy schematic netlist file ram.cdl is in the data directory.

❑ The technology file is referenced by assura_tech.lib file.

-- assura_tech.lib file

-- DEFINE tech_dir ./tech_dir

DEFINE tech_dir ../data/cln90



❑ The Assura LVS results are in the directory lvsdir

❑ Only top level text is used.

An example assura syntax is as follows:

assura arm.rsf | tee lvs.log

No log file is generated by default so the the standard output was piped into a log file.

Assura LVS extract rules

LVS extract rules are typically in a file called extract.rul. The general format of the extract.rul file is as follows:

drcExtractRules(

layerDefs(original layer definition rules)

<layer derivation rules>

<connectivity rules>

<device extraction rules>

<parameter extraction rules>

)

■ LVS Layer definition and layer derivation rules - Specify layer definition and derived layer rules.

■ LVS connectivity rules - Establishes connectivity between the defined and derived layout layers. Key commands are geomConnect and geomStamp.

■ LVS device extraction rules - Commands to extract specific devices such as MOSFETs, LDDs, and BJTs, and their associated device terminals.

■ LVS parameter extraction rules - Commands to measure and extract layout device parameters such as MOSFET width and length.

Below is an example for extracting a CMOS N transistor from layout data

drcExtractRules(

;In Layer Derivation Section:

;Derive Device Recognition Layers:

ngate = geomAnd( nplus poly )

;Derive Device Terminal Layers:

nsd = geomAndNot( nplus ngate )



;Derive Contacts:

ptap = geomAnd( psd pwell )

;In Connectivity Section:

;Extablish Connectivity:

geomConnect( svia( cont metal poly nsd psd )

svia( ptap pwell psd))

;In Device Extraction Section:

;Extract devices

extractMOS(‘n” ngate poly(“G”) nsd(“S” “D”) pwell(“B”)

;In Parameter Extraction Section:

w = measureParameter( length( ngate coincident poly ) .5u)

nameParameter (w “w”)

nameParameter (l “l”)

) ; end drcExtractRules

Assura LVS comparison rules

Assura LVS comparison rules include all the rules associated with comparing a layout netlist to a schematic netlist. The rules include run control options, input schematic specification, and rules governing device parameter comparison. The general format of the rules are as follows:

av(CompareRules (

general_rules

schematic (

;netlist specification -- required

netlist()

other_network_specific_rules

)

layout (

network_specific_rules

)

bindingFIle (“./bind.rul”)

); end of avCompareRules



Must changes in extract rules for QRC-VST and settings required for QRC

For accurate IR analysis with QRC-VST flow it is requried to separate out S/D and tie contacts. This is required to avoid shorting with IR analysis as QRC consider everything below contacts as superconductors.

■ Original extract rules

odCont = geomButtOrOver(CO OD);

geomConnect(

buttOrOver(cemit1 tpdiff)

via( nplug inbase1 tndiff)

via( odCont metal1 tndiff)

via( pl1co metal1 poly)

via( odCont metal1 tpdiff)

; Portion of the rules that need changing for QRC-VST flow+

odCont = geomButtOrOver(CO OD) ;

nplug = geomOr(nplug pplug)

odCont2 = geomAnd(odCont npplug)

odCont1 = geomAndNot(odCont npplug)

...

■ Rules needed for QRC-VST flow

odCont = geomButtOrOver(CO OD);

geomConnect(

buttOrOver(cemit1 tpdiff)

via( nplug inbase1 tndiff)

via( odCont metal1 tndiff)

via( odCont2 metal1 nplug)

via( odCont2 metal1 pplug)

via( pl1co metal1 poly)

via( odCont metal1 tpdiff)

...

The required setting in QRC is

?ignoreVias (layers(“name_of_tie contacts”) nets(“name_power nets”))

How to run Assura LVS for QRC/VST flow without a schematic netlist

■ Create a dummy input netlist for the top cell with empty .subcktt

.SUBCKT <top_cell_name>



.ENDS

■ Run only avDX() and avNX()

Assura LVS outputs

Assura LVS outputs layout information in vldb databse to be read for parasistic extraction by QRC. Various report files and cross referencing files are also output.

QRC Parasitic Extraction Flow

The QRC outputs for static and dynamic analysis consists of the following (see Figure B-1 on page 170 and Figure B-2 on page 171):

■ A SPICE netlist

The QRC transistor netlist is in SPICE format, so you can submit it to several simulators. This netlist is in flat and hierarchical form. In addition to the transistors extracted by QRC, the circuit file contains voltage source definitions for power sources and primary circuit inputs, as well as lines pointing to transistor modeling information. The exact contents of the circuit file vary, depending on the specific flow that you are executing. When the netlist is analyzed, an output file is created that uses the transistor name to identify the tap current sources in a power-grid analysis.

■ A Powergrid Database for selected power nets.

■ Lumped C SPEF file (dynamic only)

For dynamic analysis an additional Lumped C SPEF file for all nets gets created.

For more information on QRC, see the QRC Extraction Users Manual.

Power-Grid Resistance Network

The power-grid resistance network is the R or RC power-grid database output of QRC. The netlist is in binary form to minimize disk usage and to improve the efficiency of the data parsing. Power grid capacitance data is extracted by QRC only if you need it for dynamic power-grid analysis. If the database contains power grid capacitance data, this data is ignored during static power-grid analysis.

QRC computes the capacitance data for both power and signal nets. Capacitance data is required only if you request dynamic analysis for either netlist analysis or power-grid analysis. If capacitance data is not required, avoid performing this step, because it is the most resource-consuming step in the flow.



QRC needs a stripped down version of LVS rules. This file was generated by Assura LVS as runname.xcn. or by avParameter ?rcxfile. Extraction technology data needs to be compiled with lvsfile by capgen.

Resistance is calculated from contact to contact as shown in Figure B-4 on page 180

Figure B-4 Calculating resistance between contacts

The following are guidelines needed for setting up QRC.

■ Use the defeat_via_array keyword in p2lvsfile for all the contacts/via layers. See Figure B-5 on page 181. Note that p2lvsfile is a layer mapping file that provides resistance values and some control commands for mapping.



Figure B-5 Using defeat_via_array

■ Do not use the array_via_spacing keyword in p2lvsfile if running power grid or electromigration analysis. This command is used only in timing flow.

■ Do not turn on any rc reduction option in QRC.

■ For static ldsat based analysis set the set the following RSF options for extraction

?type selectd_nets

?extract “res”

?netsFile “nets”

where file nets lists all the power nets.

■ For static activity base and dynamic analysis set the following RSF options for extraction

?type select_nets

?extract “both”


?capExtractMode “decoupled”

?capGround “VSS”

■ PGDB generation flow is only enabled with SPEF output flow. Set the following RSF options options:

?outputFormat “spice”

?pgdb “t”

?spef “t”

?output “pgdb_spef”

■ Fracture length settings should be:

?maxFractureLength 250

Typically this contact has a higherpossibliity for electromigration problems.If one made this array into one contact,one could not tell which contact hadthe electormigration problem.



?fractureLenghtUnits “microns”

■ Always print parasitic resistor length and width.

?parasiticResWidth “t”

?parasiticResLength “t”

■ For good QoR one MUST not extract resistor on contact connecting to ties for power nets If separate S/D and tie contacts in extract rule, then nothing needs to be done

?ignoreVias (layers(“odCont2”) nets(“VDD”))

■ Always extract explicit resistors for vias/contacts

?addExplicitVias “t”

■ Always set split pin option to true

?splitPins “t”

■ Other mandatory commands

?lvsSource “assura”

?runName “ARM_128x32_mfn”

?netNameSpace “layout”

Below is an example of a QRCcommand file.

avParmeters(

?inputLayout (“gds2” “./ARM_128x32.gds2”)

?cellName “ARM_128x32”

?viewName “layout”

?workingDirectory “./lvsdir”

?techLib “./assura_tech.lib”

?runName “ARM_128x32”

?technology “tech_dir”

)

rcxParameters(

?lvsSource “assura”

?extract “both”

?runName “ARM_128x32_mf”

?maxFractureLength 250

?fractureLengthUnits “microns”

?capExtractMode “decoupled”

?capGround “VSS

?type “selected_nets”


?netNameSpace “layout”

?outputFormat “spice”



?pgdb “t”

?spef “t”

?output “pgdb_spef”

?ignoreVias (layers(“odCont2”) nets(“VDD”))

?splitPins “t”

?outputNetNameSpace “layout”

?addExplicitVias “t”

?parasiticResWidth “t”

?parasiticResLength “t”

)

avRCX()

Transistor Model Data

Transistor model data is output by Tablegen. It consists of tabular data of transistor currents and capacitances for many bias conditions. VoltageStorm uses this data to compute transistor currents in transistor netlist analysis and simulation. See Tablegen: Creating Device Model Tables chapter of the VoltageStorm DataPrep manual for details.

Creating Model Tables

Next, you must create the model tables that Thunder uses for analysis. Once you have created the model tables for your process, they are used until your model cards change. This procedure assumes that HSPICE is available and in your path. See the Data Preparation Manual for more information about running Tablegen.

Running Static and Dynamic Analysis

You are now ready to either proceed to Chapter 4, “Using VoltageStorm,” to begin static analysis and the continue to add capacitance data to your flow for dynamic analysis.




Glossary

This glossary defines the terms and concepts that you should understand to use VoltageStorm Transistor-Level PGS effectively.

ACAC is an abbreviation for “alternating current,” which is current that reverses direction at a regular rate. The current flow in signal wires is generally AC.

average currentAverage current is the asymptotic average current flowing through each tap point.

DCDC is an abbreviation for “direct current,” which is current that flows in only one direction. The current in a power grid is generally DC. DC is also a standard representation of a waveform that is typically used as a voltage source in circuit simulation. It displays a flat waveform.

delayDelay is the time that it takes a signal to propagate from a given input to a given output.

dynamic analysisDynamic analysis is a method of analyzing a circuit to obtain operating currents and voltages. It is time-based, analyzing the circuit netlist over a specified period, such as a clock cycle.

electromigrationElectromigration is the mass transport of metal resulting from the transfer of momentum between conducting electrons and diffusing metal atoms. It occurs in metal wires that conduct high current densities. Conducting electrons collide with diffusing metal atoms and impel the atoms in the direction of electron flow. This collision produces a mass flux opposite to that of the current. Divergences in this mass flux can result in damage to the conductor in the form of voids or hillocks. This problem can be minimized by limiting the current density in metal conductor lines, vias, and contacts.

fusingFusing is the instant failure of a wire segment because of excessive instantaneous current. This failure mechanism is related to electromigration and is sometimes classified as a subset of Joule heating.


VoltageStorm Transistor-Level Rail Analysis User GuideGlossary

hierarchical designA hierarchical design is a way of structuring logic at more than one level of abstraction; that is, a symbol at one level of abstraction represents the internal contents of a cell at a higher level of hierarchy.

HSPICEHSPICE is a specific commercial implementation of the SPICE simulator that has become an industry-standard tool for performing circuit simulation. It was developed by Meta Software.

ipeak analysisIpeak analysis is a static power-grid analysis based on peak transistor saturation currents.

IR dropIR drop is a reduction in voltage that occurs on the VDD network of an integrated circuit because of the current flowing through the resistance of the VDD network itself (V = I x R).

ItaputilItaputil is a Cadence utility that either reports characteristics of tap current files or extracts portions of the data and places them into a new tap current file.

Joule heatingJoule heating is a cause of electromigration in which a specific segment of a wire becomes excessively heated because of high currents.

Miller capacitanceMiller capacitance is coupling capacitance between nets associated with coupling between the gate and the source/drain of a transistor.

Moore’s LawMoore’s Law refers to an observation made by Gordon Moore, former CEO of Intel, that the number of transistors on silicon integrated circuits has approximately doubled once every 18 months since 1962, the year in which the technology was invented.

parasitic capacitanceParasitic capacitance is any capacitance causing unwanted effects between conductors or in devices.

peak currentPeak current is the maximum value of a current waveform.



piecewise linear (PWL)Piecewise linear is a standard representation of a waveform that is typically used as a voltage source in circuit simulation. The waveform displays no recurring pattern.

power gridA power grid is a large collection of interconnected wires on a chip that distributes power from the pins to all the gates and transistors on the chip. It is similar in function to a power distribution system that delivers power from a power station to residential and commercial facilities.

power-grid signoff (PGS)Power-grid signoff (PGS) is the process of requiring a chip to pass static power-grid analysis before tapeout.

pulsePulse is a standard representation of a waveform that is typically used as a voltage source in circuit simulation. The waveform displays a recurring pattern.

RMS currentRMS current is the root-mean-square value of a current waveform.

skin effectA skin effect is the concentration of a time-varying current near the surface of a conductor as opposed to a steady-state current flowing through a conductor that is distributed uniformly throughout the cross-section of the conductor. The penetration depth of the current is called the skin depth and is inversely proportional to the frequency of the time-varying current.

static analysisStatic analysis is a method of analyzing a circuit without using time-based simulation.

steady-state analysisSteady-state analysis is an analysis of a system that assumes that the components have steady-state values.

SVSSVS, or schematic versus schematic, is a comparison of the original schematic netlist to the netlist output by XTC.

tap currentsTap currents are currents arising from the connection of devices such as transistors to the power grid.



tapeoutTapeout is the process of placing the final chip layout design files on media for delivery to a mask-making vendor.

test vectorA test vector is an input pattern designed to exercise functionality in integrated circuits.

transient analysisTransient analysis is a time-based analysis of a system.

UDSMUDSM refers to ultra-deep submicron designs, or designs with a drawn gate width of 0.25 microns or smaller.

VDDVDD is the common name of the power node, which is the voltage supply. It is the same as VCC.

VDS

VDS is the drain-source voltage of a transistor.

vector compressionVector compression is a technique used in VoltageStorm that attempts to construct a worst-case power consumption vector through the compression of data from a number of vectors into a single resulting vector. Refer to “Vector Compression” on page 49 and “Vector Compression” on page 119 for more details.

VGS

VGS is the gate-source voltage of a transistor.

viaA via is a connection point between two adjacent metal routing layers defined by a pad in each layer.

VSSVSS is the common name of the ground node, which is a conducting body used as the electrical current return. It is the same as GND.



Index

AAC 185Accura 12, 43activity command 108

filen command 109report command 109

activity-based analysiserrors

loading a current set twice 113using the wrong grid 112

flow 106input 107output 109performing 108purpose 106

addres command 141, 144addvia command 141addvsrc command 141All Errors Off command 96analysis types

Current_Density (rj) 81, 82, 95, 97EM_risk (er) 81Inductor_Current (ic) 82Inductor_Voltage (iv) 82IR_drop (rj) 81Resistor_Power (rp) 82Resistor_Voltage (rv) 81Vsrc_Current (vc) 81

asynchronized transistor currents 41auto-filtering 82, 84, 143, 145average current

calculating 45, 107computing in vector compression 51definition 185dynamic analysis 126estimating 76reporting 47tracking in Thunder 116, 120

average current density 27average-of-average currents 124average-of-peak currents 124averaging compression 122, 124

B.ba files 71, 74backannotation

capacitance database 71circuit file 71coordinate file 71net and device names 69, 70, 74

bidirectional pin loadings 73Black’s Equation 27block power grids 30, 31, 32block-by-block power-grid

macromodels 56Boltzmann’s constant 27bulk terminal 36bull’s-eyes 90

CCalibre 70capacitance data 62, 69, 179.capdb command 12.capdb statement 70capdbutil utility 12, 127, 129change report 13, 145changeres command 141circuit file 59, 127, 132, 168clock period 107, 120, 121, 122ClockStorm

feedback in 34, 54transistor display in 76

.coordinate command 69coordinate database 74coordinate file 71, 72copper interconnect 25Copy command 165cross-coupling capacitance 22.cshrc file 65current consumption 148, 153current density 26

analysis type see Current _Density (rj) analysis type

plotting 95current source 11Current_Density (rj) analysis type 81, 95,



97Current_Density model type 100CurrentScaleFactor environment

variable 79, 104, 136Cut command 164

Ddata directory 63, 173DC sources

defining for Thunder 73defining in static power-grid analysis 43definition 185solution 125support in Thunder 115transistors tied to 77

decoupled netlist power-grid simulation flow 33

decoupling capacitance 49, 58delay 185Delete command 165description 127design flow in VoltageStorm 14devi command

report command 116, 127tally command 116tran command 116, 126

directory structure 63, 172.dist files 69DistRC

merging Fire and Ice databases 62running 69when to run 71

distributed reisistance and capacitance flowexample circuit file 135

distributed resistance and capacitance 11, 127

distributed resistance and capacitance flowdescription 132preparing data for 134running 134

Dracula 70drain terminal 36dynamic analysis see dynamic power-grid

analysisdynamic directory 64, 173dynamic power-grid analysis

block-by-block macromodels 56capacitance computation 62, 172capacitance data 62, 179

comparison to static power-grid analysis 47

creating file 70creating final database 71definition 185feedback 54filters see filtersflow 124generating capacitance data 69maximum extraction 61, 171methodologies 12, 47movies 17, 80, 139netlist analysis 49, 125output 137performing 136purpose 41, 119requirements 48step size 49, 58, 119tap current files 120Thunder 11UltraSim 11, 127vector compression 119when to perform 40without vector compression 55

dynamic tap current files 36

EECOs 13Edit Labels command 164Edit Signal command 164electromigration

analysis type see EM_risk analysis typecauses

block power-grid isolation 31conservative design for timing 31copper interconnect 25design tools 30hierarchical design 30I/O pad location 31Joule heating 23low-power design 31power-grid connections 32processing advances 29titanium nitride layers 24

corrections 58definition 22, 25, 185fusing 24input to analysis 39metal configuration data 25



model parameters 99reducing the impact of 24risk analysis 27static analysis 39, 46symptoms 24

EM Model command 99EM Model dialog box 99EM_risk analysis type 81EM_Risk model type 100engineering change orders 13environment variables 64

SIMPLEX_TOOLBOX_H 65SIMPLEX_TOOLBOX_V 65

Error List command 97Error List dialog box 97errors 96, 97

Ffiltered plots 17, 80filters

analysis types 81auto-filtering 82, 84, 143, 145creating movies 137manual filtering 84number permitted 82plotting current density 95plotting IR drop 84plotting resistor current 91plotting tap currents 90purpose 81ranges 82saving 98values

setting maximum 88, 90, 92, 95setting minimum 88, 90, 92, 95

Filters command 85Filters dialog box 82, 88, 90, 92, 95Filters menu 82filters.cmd file 98Fire

database 67directory for power-grid resistance

extraction 64directory for stripes 64directory for technology files 64extracting power-grid resistances from

stripe database 66header files 69merging capacitance data into

database 62firePOWER directory 64, 66Fixed Label option 163flat directory 64flow scripts

creating simp_template directory 65directory 64directory structure used 63, 172extracting power-grid resistances from

stripe database 66templates 65use in extraction-for-timing flows 62

fusing 22, 24, 185

Ggate terminal 36GDSII files

annotated 70layout processed by XTC 64, 66output by VoltageStorm 17, 80unlabeled vector input signals 47, 48

generate command 68genFIRE_EXT flow script 69genICE flow script 69genXT flow script 69GIF image

creating 103, 104, 105plots 17, 80saving 103

global power grids 31, 32global scaling 79

Hhierarchical design 30, 186hosts file 65, 69HSPICE 38, 68, 183, 186

II/O pads 31I/O rings 31Ice

directory for capacitance extraction 64directory for stripes 64directory for technology files 64function 62



running 69ice directory 64iclear command 118icm directory 64iload command 118image command 103, 105inductor current analysis type see

Inductor_Current (ic) analysis typeinductor voltage analysis type see

Inductor_Voltage (iv) analysis typeInductor_Current (ic) analysis type 82Inductor_Voltage (iv) analysis type 82integrated netlist-power-grid simulation

flow 33intervals parameter 120ipeak analysis

circuit file 76definition 186filtersflow 75performing 76, 151

IR dropanalysis type see IR_drop (ir) analysis

typeaverage 20best-case 53calculating 20causes 20

block power-grid isolation 31conservative design for timing 31design tools 30hierarchical design 30I/O pad location 31low-power design 31power-grid connections 32processing advances 29

corrections 58creating movies of 139definition 19, 186filtering

automatically 84, 143, 145manually 84

filters 110, 137global 20, 21local 20, 21mixed-signal designs 151peak 20plotting 111printing voltage ranges 84symptoms 21worst-case 50, 53

worst-case test vector 48, 119, 122, 124

IR_drop (ir) analysis type 81Itaputil

function 11, 124, 186running 126, 150

JJoule heating 22, 23, 186

LLabel Options dialog box 163Layer Visibility command

All Errors Off command 96All Errors On command 96, 97All Grid Off command 96All Grid On command 97

Layer Visibility menu 96layers

error overlay 96turning on and off 96

LifeTime variable 28Lightning

adding voltage sources 11creating directory for 67creating movies 137data passed to Thunder 11directory for analyzing power grid 64,

173exiting 111, 113, 114, 119filters see filtersfunction 11loading currents 112, 113, 143loading power-grid database 142modeling power grid 11obtaining best results from 105power pin location 67running 77, 109, 112, 113, 117, 136saving plots 103scaling currents 143solving power grid 143using PGS Exploration 142

lightning directory 64, 173Load Default command 116loadstate command 137lognormal standard deviation 28LSF 65, 69



lumped capacitance 11, 127lumped-capacitance flow 127

example circuit file for 131preparing data for 129running 129

Mmacromodels 56makemovie command 139match files 59, 70, 168mean time to failure 23, 27, 28measure command 87, 88MergeNet

function 67output power-grid database 62running 69

method parameter 120Miller capacitance 39, 186mixed-signal designs

instantiating as separate blocks 147static power-grid analysis 146

model command 95Model dialog box 99, 100model parameters

categories 99electromigration 99grouping 99

model tables 64, 67, 68, 173, 183Moore’s Law 29, 186movie files

applying filters in Lightning to create 137

creating in Lightning 139output by VoltageStorm 17, 80

MTTFsee mean time to failure

multiple clocks 122

Nnetlist analysis

automatic time-step control 42dynamic power-grid analysis 49, 125feeding back results of dynamic power-

grid analysis 54feeding back results of power-grid

analysis 34, 52passing tap current data to power-grid

analysis 35, 43scaling saturation currents 44static power-grid analysis 39, 115step size 49time step 119vector-based 52vector-based simulation 46

New Plot command 116

Pparasitic capacitance

computing for signal nets 46computing in dynamic power-grid

analysis 48computing in static power-grid

analysis 47definition 186

Paste After command 165Paste Before command 165peak analysis 51peak compression 122, 124, 126peak current

computing in vector compression 51definition 186dynamic power-grid analysis 126reporting 47static power-grid analysis 75tracking in Thunder 116, 120

peak-of-average currents 126peak-of-peak currents 126peak-of-RMS currents 126period parameter 120PGS Exploration

commands 141how to use 141purpose 13when to use 140

PGS see power-grid signoffpiecewise linear sources

defining for Thunder 73defining in static power-grid analysis 43definition 187support in Thunder 115

pin currents 10pin loadings 73plot command

ir command 84, 104rc command 104rj command 105



Plot dialog box 116power grids

analysis methodologies 32block 30, 31creating database 67database 74definition 187global 32name-backannotated 112resistance 20

power pinslocation 67, 74, 78represented by voltage sources 11

power-grid analysisadvanced methodologies 52design flows

decoupled netlist power-grid simulation 33

integrated netlist-power-grid simulation 33

dynamic see dynamic power-grid analysis

filtersinput 59, 168output 53performed by Lightning 11recommended design flow 103scaling saturation currents 44static activity-based see activity-based

analysisstatic ipeak analysis see ipeak analysisstatic see static power-grid analysisstatic vector-based see vector-based

analysisstep size 119tap currents 35transistor information 36

power-grid database 67, 74, 77, 142power-grid resistance network 59, 62, 168,

179power-grid signoff 10, 39, 187

static see static power-grid analysispowernet specify command 149.ptiavg file 120, 121, 124, 127, 131.ptimax file 135, 136, 120, 121, 124, 127,

131, 135, 136.ptirms file 120, 131, 135, 136pulse sources 115, 187pwrnet command

computing peak saturation currents 77report command 116

tally command 116tallyint command 120, 125, 130, 134

RRain

backannotating capacitance database 71

backannotating circuit file 71backannotating coordinate file 71match files used 70

resistor currentanalysis type see Resistor_Current (rc)

analysis typecreating movies of 139plotting 91, 111

resistor power see Resistor_Power (rp) analysis type

resistor voltage see Resistor_Voltage (rv) analysis type

Resistor_Current (rc) analysis type 81Resistor_Current command 140Resistor_Power (rp) analysis type 82Resistor_Voltage (rv) analysis type 81resistor-inductor-capacitor grid 11resistors

adding 144changing 145removing 144, 146

RMS currentcomputing in vector compression 51definition 187dynamic analysis 126reporting 47tracking in Thunder 116, 120

Ssaved solved states 104saved states 17, 80savestate command 104saving plots 103scalecurrents command 79, 88, 104, 136,

143scaling currents 44, 79, 104, 136scan command 84, 105

ir command 79, 88, 104rc command 91, 92, 104rj command 95, 105



tc command 79, 88, 104Select Signals dialog box 157, 164series resistance and inductance 43, 74show command 142Signal Editing dialog box 164simp_template directory 64, 65, 66SIMPLEX_TOOLBOX_H environment

variable 65SIMPLEX_TOOLBOX_V environment

variable 65skin effects 29, 187solve command 79, 88source terminal 36SPARCDSP directory 64, 66, 173SPARCDSP.net file 66SPICE model file 12, 131, 135static analysis see static power-grid analysisstatic directory 64, 173static power-grid analysis

activity-based see activity-based static analysis

advantages of 39capacitance data 62, 179definition 187electromigration analysis 39feedback 52filters see filtersgenerating capacitance data 69generating data for 66input 42ipeak analysis see ipeak analysismaximum saturation currents 44methodologies 12, 42minimum extraction 60, 170mixed-signal designs 146net activity data 45netlist analysis 39, 115output 17, 80PGS Exploration before 14tap currents 38vector-based see vector-based analysisvector-based simulation 46when to perform 10, 38

static tap current files 36steady-state analysis 43, 187step size 119storm.tran file 156StormCenter 116, 155 to 165

adding labels 163editing signals 164main window 156

panning 159resizing plot windows 165starting 155viewing waveforms 116, 156zooming 159

stripe files 64, 66stripes directory 64, 66SVS 187synchronized transistor currents 40

Ttable models 12Tablegen 12

command file 68creating model tables 68, 183output transistor model data 63, 183

tablegen.cmd file 68tablemodels directory 64, 173tap currents

analysis type see Tap_Current (tc) analysis type

calculating 36decoupled analysis 35definition 35, 187file

dynamic 36, 120static 36

loading twice 113plotting 90, 109sinks 11static analysis 38time correlation 41

Tap_Current (tc) analysis type 81tapeout 188technology files 64, 65temperature

Black’s equation 27temperature coefficient 27test structures 27, 28test vectors

analyzing 119creating worst-case 10, 119, 122, 124definition 188input to Thunder 11simulating 41specifying to Thunder 115

text reports 17, 80Thermal model type 100, 101Thunder



creating directory for 67creating model tables for 68, 183data passed to Lightning 11difference from UltraSim 12directory for analyzing transistor

netlist 64, 173exiting 77, 109, 116, 126function 11, 103geometric data 69loading capacitance data 70loading circuit file 115loading transistor circuit file 126log file 77modeling power grid 11output 77performing power-grid analysis on

mixed-signal designs 148running 76, 108, 115, 126running from command file 77, 150running from command line 77specifying input vectors 115validating currents computed in 38

thunder directory 64, 173time correlation 41, 50time step 119, 121, 137Timed Label option 163titanium nitride 24toolbox bin directory 64tran command 137transient analysis 42, 188transient waveforms 120transistor capacitance 48transistor circuit file

backannotating 71contents 62, 68, 73creating 68function 68loading 76, 126output pin loading 73preparing for dynamic analysis 70updating 71

transistor model datain circuit netlist file 74input to Thunder 11output by Tablegen 63, 183power-grid analysis 59, 168static power-grid analysis 42

tutorial circuit 74tutorial data files 65tutorial directory 64

UUDSM 188UltraSim

differences from Thunder 12distributed resistance and capacitance

flow 132flows in dynamic analysis 11, 127function 11lumped-capacitance flow 127

ultrasim command 129, 134unselect command 142.usim_ir command 129, 134.usim_opt capfile command 12, 129, 134

VVCD files 47, 115, 125VDD

adding pads to design 58definition 188distribution network 38ideal voltage 19input to activity-based analysis 107number of transistors connected to 36power-grid database 77, 142resistive connectivity matrix 49static power-grid analysis 42tallying current from 126VDS voltage magnitude 77VGS voltage magnitude 77voltage source waveform 116

VDD.ipeak file 77VDS 44, 77, 188vector compression

avoiding 55clock period 120, 121, 122definition 188dynamic power-grid analysis 48, 119intervals 120, 122method

averaging 122, 124peak 122, 124, 126

method of compression 120multiple clocks 122parameters set 120peak analysis 51purpose 10, 49setting parameters 122



time correlation 50vector-based analysis

flow 114input 115output 118performing analysis 117performing netlist analysis 115specifying vectors 115

VGS 44, 77, 188via 188via arrays 30voltage drop see IR dropvoltage source current see Vsrc_Current

analysis typevoltage source power

analysis type see Vsrc_Power (vp) analysis type

voltage sourcesadding in Lightning 11components of analysis 11connected to power grid 82DC 73defining 109, 112, 113defining additional 43defining power 68input to Thunder 11locating 78, 98piecewise linear 73representing power pins 11specifying vectors in Thunder 115

VoltageStormanalysis methodologies 32directory structure 63, 172exploring power grid 140filters see filtersfunction 9goals 119input 42, 59, 168methods of finding weak spots 10output 17, 80recommended analysis design

flow 103tutorial 59vector compression see vector

compressionVsrc_Current (vc) analysis type 81Vsrc_Power (vp) analysis type 82VSS

definition 188ideal voltage 19number of transistors connected to 36

static power-grid analysis 42

Wwatch command 139weak spots 10, 39, 40Which command 98Which/Scalecurrents/Measure dialog

box 145, 153worst error list 97worst-case IR drop test vector

creating by vector compression 48, 52predicting 10, 119, 122, 124

write command 142

Xxt directory 64xt.cmd file 66XTC

command file 65cross-referencing net and device

names 70directory 64model names created 68output transistor netlist 62running 66

xv utility 152, 153

ZZI button 98zoom reset command 144zooming 94, 97, 98, 106ZR button 94, 98


Voltagestorm

Technology

Transcript of Voltagestorm