Voltage Supervisor with Manual Reset Inputww1.microchip.com/downloads/en/DeviceDoc/22035a.pdf ·...

TC1270A/71AVoltage Supervisor with Manual Reset Input

Features:• Precision voltage monitor

- 2.63V, 2.93V, 3.08V, 4.38V and 4.63V trip points (Typical)

• Manual Reset input • Reset Time-out Delay:

- 280 ms (Typical) • Power Consumption ≤ 15 µA max • No glitches on outputs during power-up • Active Low Output Options:

- Push-Pull Output• Active High Output Option:

- Push-Pull Output• Replacement for (Specification compatible with):

- TC1270, TC1271 - TCM811, TCM812

• Fully static design• Low voltage operation (1.0V)• ESD protection:

- ≥ 4 kV Human Body Model (HBM)- ≥ 400V Machine Model (MM)

• Extended (E) Temperature range:-40°C to +125°C

• Package Options:- 4-lead SOT-143 - 5-lead SOT-23- Pb-free Device

Package Types

Functional Block Diagram

Device Features

1

2

4

3

TC1271A

SOT-143

VSS VDD

RST MR

1

2

4

3TC

1270A

SOT-143

VSS VDD

RST MR

1

2

3

5

4

TC1271A

SOT-23-5

1

2

3

5

4

TC1270A

SOT-23-5

NC NC

VDD

MR RST

VSS VSS

VDD

MR RST

18.5 kΩ

VDD

MR

RST

RST

Glitch Filter

VoltageDetector

PP

PP

Generator & Delay

Timer

Out

put

Driv

er(280 ms)

Circuitry (TC1271A)

(TC1270A)

Reset

Device

Output

Res

et D

elay

(m

s) (T

yp)

Res

et T

rip

Poin

t (V)

(3)

Volta

ge

Ran

ge (V

)

Tem

pera

ture

R

ange

Packages CommentType Active

Level

TC1270A Push-Pull Low

280 (1) 4.63, 4.38,3.08, 2.93,

2.63(4)

1.0V to

5.5V

-40°C to

+125°C

SOT-143 (2), SOT-23-5

Replaces TC1270 and TCM811

TC1271A Push-Pull High Replaces TC1271 and TCM812

Note 1: The 280 ms Reset Delay time-out is compatible with the TC1270, TC1271, TCM811, and TCM812devices.

2: The SOT-143 package is compatible with the TC1270, TC1271, TCM811, and TCM812 devices.

3: Custom Reset Trip Points available, contact factory.

4: The TC1270/1 and TCM811/12 1.75V Trip Point Option is not supported.

© 2007 Microchip Technology Inc. DS22035A-page 1

TC1270A/71A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †Supply Voltage (VDD to VSS) ...............................+7.0VInput Current, VDD..............................................10 mAOutput Current, RESET, RESET........................10 mAVoltage on all inputs and outputs

w.r.t. VSS ............................ -0.6V to (VDD + 1.0V)Storage Temperature Range ..............-65°C to +150°COperating Temperature Range...........-40°C to +125°CMaximum Junction Temperature, TS................... 150°CESD protection on all pins

Human Body Model ....................................... ≥ 4 kVMachine Model .............................................. ≥ 400V

† Notice: Stresses above those listed under "AbsoluteMaximum Ratings" may cause permanent damage tothe device. This is a stress ratings only and functionaloperation of the device at those or any other conditionsabove those indicated in the operational listing of thisspecifications is not implied. Exposure to AbsoluteMaximum Rating conditions for extended periods mayaffect device reliability.

ELECTRICAL CHARACTERISTICSElectrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.

Parameter Sym Min Typ(1) Max Units Test Conditions

Operating Voltage Range VDD 1.0 — 5.5 VSupply Current IDD — 7 15 µA VDD > VTRIP, for L/M/R/S/T,

VDD = 5.5V— 4.75 10 µA VDD > VTRIP, for R/S/T, VDD = 3.6V— 10 15 µA VDD < VTRIP, for L/M/R/S/T

Reset Trip Point Threshold (3)

VTRIP 4.54 4.63 4.72 V TC127xAL: TA = +25°C4.50 — 4.75 V TA = –40°C to +125°C4.30 4.38 4.46 V TC127xAM: TA = +25°C4.25 — 4.50 V TA = –40°C to +125°C3.03 3.08 3.14 V TC127xAT: TA = +25°C3.00 — 3.15 V TA = –40°C to +125°C2.88 2.93 2.98 V TC127xAS: TA = +25°C 2.85 — 3.00 V TA = –40°C to +125°C2.72 2.77 2.82 V TC127xA:(5) TA = +25°C 2.70 — 2.85 V TA = –40°C to +125°C2.58 2.63 2.68 V TC127xAR: TA = +25°C 2.55 — 2.70 V TA = –40°C to +125°C

Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated.2: RST output for TC1270A, RST output for TC1271A.3: TC127XA refers to either the TC1270A or TC1271A device.4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.5: Custom ordered Voltage Trip Point. Minimum order volume requirement.

DS22035A-page 2 © 2007 Microchip Technology Inc.

TC1270A/71A

Reset Threshold Tempco — ±30 — ppm/°CReset Trip Point Hysteresis (4)

VHYS — 0.3 — % Percentage of VTRIP Voltage

MR Input High Threshold VIH 2.3 — — V VDD > VTRIP(MAX), TC127XAL/M 0.7 VDD — — V VDD > VTRIP(MAX), TC127XAR/S/T

MR Input Low Threshold VIL — — 0.8 V VDD > VTRIP(MAX), TC127XAL/M — — 0.25 VDD V VDD > VTRIP(MAX), TC127XAR/S/T

MR Pull-up Resistance 10 18.5 40 kΩReset Output Voltage Low (2)

TC1270A VOL — — 0.3 V R/S/T only,ISINK = 1.2 mA, VDD = VTRIP(MIN)

TC1271A — — 0.3 V R/S/T only,ISINK = 1.2 mA, VDD = VTRIP(MAX)

TC1270A — — 0.4 V L/M only,ISINK = 3.2 mA, VDD = VTRIP(MIN)

TC1271A — — 0.3 V L/M only,ISINK = 3.2 mA, VDD = VTRIP(MAX)

TC1270A — — 0.3 V L/M only,ISINK = 50 µA, VDD > 1.0V

Reset Output Voltage High (2)

TC1270A VOH 0.8 VDD — — V R/S/T only,ISOURCE = 500 µA, VDD = VTRIP(MAX)

TC1270A VDD - 1.5 — — V L/M only,ISOURCE = 800 µA, VDD = VTRIP(MAX)

TC1271A 0.8 VDD — — V ISOURCE = 500 µA, VDD ≤ VTRIP(MIN)Input Leakage Current IIL — — ±1 µA VPIN = VDDCapacitive Loading Specification on Output Pins

CIO — — 50 pF

ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.


Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated.2: RST output for TC1270A, RST output for TC1271A.3: TC127XA refers to either the TC1270A or TC1271A device.4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.5: Custom ordered Voltage Trip Point. Minimum order volume requirement.


TC1270A/71A
1.1 AC CHARACTERISTICS
1.1.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been createdfollowing one of the following formats:

FIGURE 1-1: TEST LOAD CONDITIONS

1. TppS2ppS 2. TppST

F Frequency T TimeE ErrorLowercase letters (pp) and their meanings:

ppio Input or Output pin osc Oscillatorrx Receive tx Transmitbitclk RX/TX BITCLK RST Resetdrt Device Reset TimerUppercase letters and their meanings:

SF Fall P PeriodH High R RiseI Invalid (High-impedance) V ValidL Low Z High-impedance

Pin

VSS

CL = 50 pF


TC1270A/71A
1.1.2 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 1-2: MR PIN AND RESET PIN WAVEFORM

FIGURE 1-3: DEVICE VOLTAGE AND RESET PIN (ACTIVE LOW) WAVEFORM

TABLE 1-1: RESET AND DEVICE RESET TIMER REQUIREMENTSElectrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.


VDD to Reset Delay tRD — 50 — µs VDD = VTRIP(MAX) toVTRIP(MIN) –125 mV

Reset Active Timeout Period

TC127XAxVyy (2) tRST 140 280 560 ms VDD = VTRIP(MAX)

MR Minimum Pulse Width tMR 10 — — µsMR Noise Immunity tMRNI — 0.1 — µsMR to Reset Propagation Delay tMD — 0.2 — µsNote 1: Data in the Typical (“Typ”) column is at 5V, 25°C, unless otherwise stated.

2: TC127XA refers to either the TC1270A, or TC1271A device. “x” indicated the selected Voltage Trip Point, while “yy” indicates the package code.

MR

RST

tRST

tMR

RST

tMD tMRNI

VTRIP(MAX)

VTRIP(MIN)

1VVDD

VTRIP

tRST

RST

RST

tRST tRD

VDD < 1V is outside the device operating specification. The RST (or RST) output state is unknown while VDD < 1V.


TC1270A/71A

TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.0V to +5.5V, VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature RangesSpecified Temperature Range TA -40 — +125 °COperating Temperature Range TA -40 — +125 °CStorage Temperature Range TA -65 — +150 °CThermal Package ResistancesThermal Resistance, 5L-SOT-23 θJA — 256 — °C/WThermal Resistance, 4L-SOT-143 θJA — 426 — °C/W


TC1270A/71A

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.

FIGURE 2-1: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AL, TC1271AL- 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-2: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-3: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.).

FIGURE 2-4: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AL, TC1271AL- 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-5: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AT, TC1271AT- 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-6: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.).

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0

0.5

1

1.5

2

2.5

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

1.0V

2.0V

3.0V

4.0V

5.0V

0

0.5

1

1.5

2

2.5

3

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

1.0V

2.0V

3.0V

4.0V

5.0V

0

0.5

1

1.5

2

2.5

3

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

1.0V

2.0V

3.0V

4.0V

5.0V

4.5

5

5.5

6

6.5

7

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

4.8V

5.5V

33.5

44.5

55.5

66.5

7

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

4.5V

5.5V

3.5V

2.53

3.54

4.55

5.56

6.5

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A) 4.0V

5.0V

3.0V


TC1270A/71A
FIGURE 2-7: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AL, TC1271AL- 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-8: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AT, TC1271AT- 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-9: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AR, TC1271AR- 2.55V min. / 2.63V typ. / 2.70V max.).

FIGURE 2-10: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-11: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-12: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.).

0

0.5

1

1.5

2

2.5

3

1 2 3 4 5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

0

0.5

1

1.5

2

2.5

3

1 2 3 4 5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

0

0.5

1

1.5

2

2.5

3

3.5

1 2 3 4 5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

4.5

5

5.5

6

6.5

7

4.5 4.7 4.9 5.1 5.3 5.5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

2.53

3.54

4.55

5.56

6.57

3 3.5 4 4.5 5 5.5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

2

3

4

5

6

7

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C


TC1270A/71A
FIGURE 2-13: VTRIP and VHYS vs. Temperature (TC1270AL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-14: VTRIP and VHYS vs. Temperature (TC1270AT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-15: VTRIP and VHYST vs. Temperature (TC1270AR, TC1271AR- 2.55V min. / 2.63V typ. / 2.70V max.).

FIGURE 2-16: VOL vs. IOL (TC1270AL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-17: VOL vs. IOL (TC1270AT, TC1271AT- 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-18: VOL vs. IOL (TC1270AR, TC1271AR- 2.55V min. / 2.63V typ. / 2.70V max.).

4.6054.61

4.6154.62

4.6254.63

4.6354.64

4.6454.65

-40 25 125

Temperature (°C)

V TR

IP (V

)

0.20.220.240.260.280.30.320.340.360.380.4

V HYS

(%)

VTRIP (with VDD Falling)

VHYS

VTRIP (with VDD Rising)

3.0663.0683.07

3.0723.0743.0763.0783.08

3.0823.0843.086

-40 25 125

Temperature (°C)

V TR

IP (V

)

0.20.220.240.260.280.30.320.340.360.380.4

V HYS

(%)

VHYS



2.61

2.615

2.62

2.625

2.63

2.635

2.64

-40 25 125

Temperature (°C)

V TR

IP (V

)

0.20.220.240.260.280.30.320.340.360.380.4

V HYS

(%)

VHYS



0

0.02

0.04

0.06

0.08

0.1

0.12

0.00 1.00 2.00 3.00 4.00

IOL (mA)

V OL

(V)

2.0V

3.0V

4.3V

4.4V

4.5V

0

0.05

0.1

0.15

0.2

0.25

0 2 4 6 8IOL (mA)

V OL

(V) 3.2V4.0V

4.5V5.0V

5.5V

3.15

00.020.040.060.08

0.10.120.140.160.18

0.2

0 1 2 3 4

IOL (mA)

V OL

(V)

2.0V 2.45V

2.5V


TC1270A/71A
FIGURE 2-19: VOL vs. Temperature (TC1270AL, TC1271AL- 4.50V min. / 4.63V typ. / 4.75V max.).@ VDD = 4.5V).

FIGURE 2-20: VOL vs. Temperature (TC1270AT, TC1271AT- 3.00V min. / 3.08V typ. / 3.15V max.).@ VDD = 2.7V).

FIGURE 2-21: VOL vs. Temperature (TC1270AR, TC1271AR- 2.55V min. / 2.63V typ. / 2.70V max.).@ VDD = 1.8V).

FIGURE 2-22: VOH vs. IOL (TC1270AL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.)@ +25°C).

FIGURE 2-23: VOH vs. IOH (TC1270AT, TC1271AT- 3.00V min. / 3.08V typ. / 3.15V max.)@ +25°C).

FIGURE 2-24: VOH vs. IOH (TC1270AR, TC1271AR- 2.55V min. / 2.63V typ. / 2.70V max.)@ +25°C).

0

0.02

0.04

0.06

0.08

0.1

0.12

-40 10 60 110

Temperature (°C)

VO

L (V

)

4 mA

2 mA

1 mA 0.5 0.35 mA0.2

A

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

-40 10 60 110

Temperature (°C)

VO

L (V

)

8 mA

6 mA

4 mA

2 mA 1 mA 0.5 A

0

0.05

0.1

0.15

0.2

-40 10 60 110Temperature (°C)

V OL

(V)

4 mA

2 mA

1 mA 0.5 0.35 mA0.2

A

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

0.00 1.00 2.00 3.00 4.00 5.00

IOH (mA)

V OH (V

)

5.5V

5.0V

4.8V

4.75V

1.7

1.9

2.1

2.3

2.5

2.7

2.9

0 1 2 3 4 5

IOH (mA)

V OH (V

)2.9V

2.7V

2.5V

22.5

33.5

44.5

55.5

6

0 1 2 3 4 5

IOH (mA)

V OH (V

)

5.5V

5.0V

4.5V

4.0V

3.0V

2.8V


TC1270A/71A
FIGURE 2-25: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AL, TC1271AL- 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-26: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AT, TC1271AT- 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-27: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AR, TC1271AR- 2.55V min. / 2.63V typ. / 2.70V max.).

FIGURE 2-28: Reset Timeout Period (tRST) vs. Temperature (TC1270AL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-29: Reset Timeout Period (tRST) vs. Temperature (TC1270AT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-30: Reset Timeout Period (tRST) vs. Temperature(TC1270AR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.).

48

49

50

51

52

53

54

55

-40 10 60 110Temperature (°C)

t RPD

(µs)

48

49

50

51

52

53

54

55

-40 10 60 110

Temperature (°C)

t RPD

(µs)

48

49

50

51

52

53

54

55

-40 10 60 110

Temperature (°C)

t RPD

(µs)

275280285290295300305310315320

-40 10 60 110

Temperature (°C)

t RST

(ms)

5.5V

5.0V

4.75V

275280285290295300305310315320325

-40 10 60 110

Temperature (°C)

t RST

(ms)

5.5V5.0V

4.5V4.0V

3.0V

2.8V

275280285290295300305310315320

-40 10 60 110

Temperature (°C)

t RST

(ms)

5.5V

5.0V

4.5V

4.0V

3.0V

2.8V


TC1270A/71A
FIGURE 2-31: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AL, TC1271AL- 4.50V min. / 4.63V typ. / 4.75V max.).

FIGURE 2-32: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AT, TC1271AT- 3.00V min. / 3.08V typ. / 3.15V max.).

FIGURE 2-33: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AR, TC1271AR- 2.55V min. / 2.63V typ. / 2.70V max.).

FIGURE 2-34: VDD Transient Duration vs. Reset Threshold Overdrive(VTRIP (minimum) - VDD).

0.17

0.18

0.19

0.2

0.21

0.22

-40 10 60 110

Temperature (°C)

t MD (µ

s)

5.5V

5.0V

4.8V4.75V

0.17

0.18

0.19

0.2

0.21

0.22

-40 10 60 110

Temperature (°C)

t MD (µ

s)

5.5V

5.0V

4.5V4.0V

0.17

0.18

0.19

0.2

0.21

0.22

-40 10 60 110

Temperature (°C)

t MD (µ

s)

5.5V

5.0V 4.5V

4.0V

0

10

20

30

40

50

60

0.001 0.01 0.1 1 10

VTRIPMIN - VDD (V)

Tran

sien

t Dur

atio

n (µ

s)

4.63V

3.08V

2.63VAbove Line, Reset Occurs

Below Line, No Reset Occurs


TC1270A/71A

3.0 PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PINOUT DESCRIPTIONPin Number

Sym

Pin

Standard Function

TC1270A (Push-Pull, active low)

TC1271A (Push-Pull, active high)

SOT-

23-5

SOT-

143-

4

SOT-

23-5

SOT-

143-

4

TypeBuffer

/ Driver

5 1 5 1 VSS — Power Ground

4 2 — — RST O Push-Pull

Reset output (Push Pull), active lowH = VDD > VTRIP, Reset pin is inactive

(after Reset Timer Delay completes) L = VDD < VTRIP, Reset pin is active

Goes active (Low) if one of these conditions occurs:1. If VDD falls below the selected Reset voltage threshold.2. If the MR pin is forced low.3. During power-up.

— — 4 2 RST O Push-Pull

Reset output (Push Pull), active highH = VDD < VTRIP, Reset pin is active L = VDD > VTRIP, Reset pin is inactive

(after Reset Timer Delay completes)

Goes active (High) if one of these conditions occurs:1. If VDD falls below the selected Reset voltage threshold.2. If the MR pin is forced low.3. During power-up.

3 3 3 3 MR I ST (1) Manual Reset input pin This input allows a push button switch to be directly connected to the TC1270A/71A’s MR pin, which can then be used to force a system Reset. The input filter (ignores) noise pulses that occur on the MR pin.H = Switch is open (internal pull-up resistor pulls signal high).

State of the RST/RST pin determined by other system conditions.

L = Switch is depressed (shorted to ground). This forces the RST/RST pin Active.

2 4 2 4 VDD — Power Supply Voltage

1 — 1 — NC — —Note 1: The MR pin has an internal weak pull-up (18.5 kΩ typical).


TC1270A/71A
3.1 Ground Terminal (VSS) VSS provides the negative reference for the analoginput voltage. Typically, the circuit ground is used.
3.2 Supply Voltage (VDD)VDD can be used for power supply monitoring or avoltage level that requires monitoring.

3.3 Reset Output (RST and RST)There are two types of Reset output pins. These are:

1. Push-Pull active-low Reset2. Push-Pull active-high Reset

3.3.1 ACTIVE-LOW (RST) - PUSH-PULLThe RST push-pull output remains low while VDD isbelow the Reset voltage threshold (VTRIP). The timethat the RST pin is held low after the device voltage(VDD) returns to a high level (> VTRIP) is typically280 ms.

After the Reset delay timer expires, the RST pin will bedriven to the high state.

3.3.2 ACTIVE-HIGH (RST) - PUSH-PULLThe RST push-pull output remains high while VDD isbelow the Reset voltage threshold (VTRIP). The timethat the RST pin is held high after the device voltage(VDD) returns to a high level (> VTRIP) is typically280 ms.

After the Reset delay timer expires, the RST pin will bedriven to the low state.

3.4 Manual Reset Input (MR)The Manual Reset (MR) input pin allows a push buttonswitch to easily be connected to the system. When thepush button is depressed, it forces a system Reset.This pin has circuitry that filters noise that may bepresent on the MR signal.

The MR pin is active-low and has an internal pull-upresistor.


TC1270A/71A

4.0 DEVICE OPERATION

4.1 General DescriptionFor many of today’s microcontroller applications, caremust be taken to prevent low-power conditions that cancause many different system problems. The mostcommon causes are brown-out conditions, where thesystem supply drops below the operating levelmomentarily. The second most common cause is whena slowly decaying power supply causes the Microcon-troller to begin executing instructions without sufficientvoltage to sustain volatile memory (RAM), thus produc-ing indeterminate results.

The TC127XA family (TC1270A, and TC1271A) arecost-effective voltage supervisor devices designed tokeep a microcontroller in Reset until the system voltagehas reached and stabilized at the proper level for reli-able system operation. These devices also operate asprotection from brown-out conditions when the systemsupply voltage drops below a safe operating level.

A Manual Reset input (MR pin) is provided. This allowsa push button switch to be directly connected to theTC127XA device, and is suitable for use as a pushbutton Reset. This allows the system to easily be resetfrom the external control of the push button switch. Noexternal components are required.

The Reset pin (RST or RST) will be forced active, if anyof the following occur:

• During device power up• VDD goes below the device threshold voltage• The Manual Reset input (MR) goes low

Figure 4-1 shows a high level block diagram of thedevices. The device can be described with threefunctional blocks. These are:

• Voltage Detect circuit • Manual Reset with Glitch Filter circuit • Reset Generator circuit

The Reset Generator circuit controls the reset delaytime of the reset output signal.

The reset signal (RST/RST pin) will be held active for aminimum of 140 ms.

The TC1271A has an active-high RST output while theTC1270A has an active-low RST output.

The TC1270A and TC1271A have a push-pull outputdriver.

Figure 4-2 shows a typical circuit for a push-pull device.

FIGURE 4-1: TC127XA High Level Block Diagram.

FIGURE 4-2: Typical Push-Pull Application Circuit.The devices are available in a 4-Pin SOT-143 package,to maintain compatibility with the TC1270, TC1271,TCM811, and TCM812 devices, and the SOT-23-5package which is a lower cost package.

Low supply current makes these devices suitable forbattery powered applications.

VDD

MR

RST

RST

VoltageDetector

ResetCircuit

Manual Resetwith Glitch

Filter Circuit

GeneratorCircuit

or

VRST

MRRST

PushButton

MR

VSS VSS

VDDVDD

Reset Input

TC1270A/1A

VDD

0.1 µF

RST orRST


TC1270A/71A
Device specific block diagrams are shown in Figure 4-3through Figure 4-4.
FIGURE 4-3: TC1270A Block Diagram.

FIGURE 4-4: TC1271A Block Diagram.

4.2 Voltage Detect CircuitThe Voltage Detect Circuit monitors VDD. The device’sReset voltage trip point (VTRIP) is selected when thedevice is ordered. The voltage on the device’s VDD pindetermines the output state of the RST/RST pin.

VDD voltages above the VTRIP(MAX) force the RST/RSTpin inactive. VDD voltages below the VTRIP(MIN) forcethe RST/RST pin active. The state of the RST/RST pinis unknown for VDD voltages between VTRIP(MAX) andVTRIP(MIN). This is shown in Table 4-1

TABLE 4-1: VDD LEVELS TO RST/RST OUTPUT STATES

The term VTRIP will be used as the general term for thetrip point voltage where the device actually trips.

In the case where VDD is falling (for voltages startingabove VTRIP(MAX)):

• Voltages above VTRIP(MAX) will never cause the RST/RST output pin to be driven Active.

• Voltages below VTRIP(MIN) will always cause the RST/RST output pin to be driven Active.

Now in the case where VDD is rising (for voltagesstarting below VTRIP(MIN)):

• Voltages above VTRIP(MAX) will always cause the RST/RST output pin to be driven Inactive, after the Reset Delay Timer (tRST), times out.

VDD

Comparator+

–

OutputDriver

RSTReference

Noise FilterMR

Voltage Delay

(Push-Pull)

VDD

Comparator+

–RST

Reference

Noise FilterMR

Voltage Delay

OutputDriver(Push-Pull)

VDD Voltage LevelOutput State

RST RST

VDD ≥ VTRIP(MAX) H (1) L (1)

VTRIP(MIN) < VDD < VTRIP(MAX) U UVDD ≤ VTRIP(MIN) L HLegend: H = Driven High L = Driven Low

U = Unknown, driven either High or LowNote 1: The RST/RST pin will be driven inactive

after the Reset Delay Timer (tRST) times out.


TC1270A/71A
Table 4-2 shows the various device trip point optionsand their VTRIP(MAX) and VTRIP(MIN) voltages. Also thenegative percentage change from common regulatedvoltages is shown.
In the case where VDD is falling from the regulated volt-age, as the VDD crosses the VTRIP voltage theRST/RST pin is driven active. Now the desired circuitryis in reset, or the circuitry has the indication that theVDD is below the selected VTRIP.

In the case where VDD is rising. As the VDD crosses theVTRIP voltage, the RST/RST pin is driven inactive afterthe Reset Delay Timer elapses. Now the desired cir-cuitry is released from reset and will start to operate inits normal mode, or the circuitry has the indication thatthe VDD is above the selected VTRIP.

TABLE 4-2: SELECTING THE TRIP POINT

The TC1270A/TC1271A devices are optimized toreject fast transient glitches on the VDD line. If the lowinput signal (which is below VTRIP) is not rejected, theReset output is driven active within 50 µs of VDD fallingthrough the Reset voltage threshold.

After the device exits the Reset condition, the delaycircuitry will hold the RST/RST pin active until theappropriate Reset delay time (tRST) has elapsed.

During device power up, the input voltage is below theTrip Point voltage. The device must enter the validoperating range for the device to start operation.

4.2.1 HYSTERESISThere is also a minimal hysteresis (VHYS) on the trippoint. This is so that small noise signals on the devicevoltage (VDD) do not cause the Reset pin (RST/RST) to“jitter” (change between driving an active and inactive).

The characterization graphs shown in Figures 2-13through 2-15 shows the device hysteresis as a percent-age of the voltage trip point (VTRIP).

The Reset Delay Timer (tRST) gives a time based hys-teresis for the system.

4.2.2 POWER-UP/RISING VDD As the device VDD rises, the device’s Reset circuit willremain active until the voltage rises above the “actual”trip point (VTRIP).

Figure 4-5 shows a power-up sequence and the wave-form of the RST and RST pins. As the device powersup, the voltage will start below the valid operating volt-age of the device. At this voltage, the RST/RST outputis not valid. Once the voltage is above the minimumoperating voltage (1V) and below the selected VTRIP,the Reset output will be active.

Once the device voltage rises above the VTRIP voltage,the Reset delay timer (tRST) starts. When the Resetdelay timer times out, the Reset output (RST/RST) isdriven inactive.

FIGURE 4-5: RST/RST pin Operation Power-up.

Trip Voltage

Selection

VTRIP(MAX)(1)

/ VTRIP(MIN)

(2)

- % From Regulated Voltage

5.0V 3.3V 3.0V

L 4.75V 5.0% — —4.50V 10.0% — —

M 4.50V 10.0% — —4.25V 15.0% — —

T 3.15V — 4.5% —3.00V — 9.2% —

S 3.00V — 9.2% —2.85V — 13.7% —

R 2.70V — — 10.0%2.55V — — 15.0%

Note 1: Voltage regulator circuit must have tighter tolerance (%) than VTRIP(MAX) % from regulated voltage.

2: Circuitry being reset must have a wider tolerance (%) than VTRIP(MIN) % from regulated voltage.

Note: While the Reset delay timer (tRST) isactive, additional system current isconsumed.

VTRIP

1VVDD tRST(1)

RST

RST

Note 1: Additional system current is consumedduring the tRST time.


TC1270A/71A
4.2.3 POWER-DOWN/BROWN-OUTSAs the device powers-down/brown-outs, the VDD fallsfrom a voltage above the devices trip point (VTRIP). Thedevice will trip at a voltage between the maximum trippoint (VTRIP(MAX)) and the minimum trip point(VTRIP(MIN)). Once the device voltage (VDD) goesbelow this voltage, the RST/RST pin will be forced tothe active state.
Figure 4-6 shows the waveform of the RST pin asdetermined by the VDD voltage. As the VDD voltage fallsfrom the normal operating point, the device “enters”reset by crossing the VTRIP voltage (betweenVTRIP(MAX) and VTRIP(MIN)). Then when VDD voltagerises, the device “exits” reset by crossing the VTRIP volt-age (below or at VTRIP(MAX)). After the “exit” state hasbeen detected, the Reset Delay Timer (tRST) starts.Once the tRST time completes, the Reset pin is driveninactive.

Table 4-3 shows the state of the RST or RST pins.

TABLE 4-3: RESET PIN STATES

FIGURE 4-6: RST Operation as determined by the VTRIP.

DeviceState of RST Pin when: State of RST Pin when:

Output DriverVDD < VTRIP VDD > VTRIP (1) VDD < VTRIP VDD > VTRIP (1)

TC1270A L H — — Push-Pull

TC1271A — — H L Push-Pull

Note 1: The RST/RST pin will be driven inactive after the Reset Delay Timer (tRST) times out.

VDD VTRIP

RST

1V

< 1V is outside the device specificationstRD

tRST

tRD tRST

VTRIP

(with VDD Falling)

(with VDD Rising)


TC1270A/71A
4.3 Negative Going VDD TransientsThe minimum pulse width (time) required to cause aReset may be an important criteria in the implementa-tion of a Power-on Reset (POR) circuit. This time isreferred to as transient duration. The TC127XA devicesare designed to reject a level of negative-goingtransients (glitches) on the power supply line.
Transient duration is the amount of time needed forthese supervisory devices to respond to a drop in VDD.The transient duration time (tTRAN) is dependant on themagnitude of VTRIP – VDD (overdrive). Any combinationof duration and overdrive that lies under theduration/overdrive curve will not generate a Resetsignal. Generally speaking, the transient duration timedecreases with and increases in the VTRIP – VDDvoltage. Combinations of duration and overdrive thatlies above the duration/overdrive curve are detected asa brown-out or power-down condition.

Figure 4-7 shows an example transient duration vs.Reset comparator overdrive. It shows that the fartherbelow the trip point the transient pulse goes, theduration of the pulse required to cause a Reset getsshorter. So any combination of duration and overdrivethat lays under the curve will not generate a Resetsignal. Combinations above the curve are detected asa brown-out or power-down.

Transient immunity can be improved by adding abypass capacitor (typically 0.1 µF) as close as possibleto the VDD pin of the TC127XA device.

FIGURE 4-7: Example of Typical Transient Duration Waveform.

4.4 Manual Reset with Glitch Filter Circuit

The Manual Reset input pin (MR) allows the Reset pins(RST/RST) to be manually forced to their active states.The MR pin has circuitry to filter noise pulses that maybe present on the pin. Figure 4-8 shows a blockdiagram for using the TC127XA with a push buttonswitch. To minimize the required external components,the MR input has an internal pull-up resistor.

A mechanical push button or active logic signal candrive the MR input.

Once MR has been low for a time, tMRD (the ManualReset delay time), the Reset output pins are forcedactive. The Reset output pins will remain in their activestates for the Reset delay timer time out period (tRST).

Figure 4-9 shows a waveform for the Manual Resetswitch input and the Reset pins output.

FIGURE 4-8: Push Button Reset.

FIGURE 4-9: MR Input – Push Button.

4.4.1 NOISE FILTERThe noise filter filters out noise spikes (glitches) on theManual Reset pin (MR). Noise spikes less than 100 ns(typical) are filtered.

Time (µs)0V

Supp

ly V

olta

ge

5V

VTRIP(MIN) - VDD

tTRAN (Duration)

VTRIP(MAX)VTRIP(MIN)

(Overdrive)

Transient Overdrive Voltage (mV)

Tran

sien

t Dur

atio

n (m

s)

Area below curve will not generate a reset signal

Area above curve will generate a reset signal

VDD

MR

VSS

RST MCLR

+5V

TC127XA PIC® MCU

RST

VIL

tMR

RST

tMD

VIH

tRST

MR

The MR input typically ignores input pulsesof 100 ns.


TC1270A/71A
4.5 Reset Generator CircuitThe output signals from the Voltage Detect Circuit andthe Manual Reset with Glitch Filter Circuit are OR’dtogether and is used to activate the Reset GeneratorModule.
After the reset conditions have been removed (the MRpin is no longer forced low and the input voltage isgreater than the Trip Point voltage), the Reset Genera-tor circuit determines the reset delay timeout required.

The delay circuit creates a 280 ms (typical) delay

4.5.1 RESET DELAY TIMERThe Reset delay timer ensures that the TC127XAdevice will “hold” the embedded system in Reset untilthe system voltage has stabilized. The Reset delaytimer time out is shown in Table 4-4.

The Reset Delay Timer starts once the VoltageDetector Circuit output AND the Manual Reset withGlitch Filter Circuit output become inactive. While theReset Delay Timer is active, the RST or RST pin isdriven to the active state. Once the Reset Delay Timertimes-out, the RST or RST pin is driven inactive.

The Reset delay timer (tRST) starts after the devicevoltage rises above the “actual” trip point (VTRIP).When the Reset delay timer times out, the Reset outputpin (RST/RST) is driven inactive.

The Reset Delay Timer is cleared, if either (or both) theVoltage Detector Circuit output OR the Manual Resetwith Glitch Filter Circuit output become active. The RSTor RST pin continues to be driven to the active state.

Figure 4-10 illustrates when the Reset Delay Timer(tRST) is active or inactive.

4.5.2 EFFECT OF TEMPERATURE ON RESET POWER-UP TIMER (tRPU)

The Reset delay timer time out period (tRST)determines how long the device remains in the Resetcondition. This time out is affected by both the deviceVDD and temperature. Typical responses for differentVDD values and temperatures are shown inFigures 2-28, 2-29 and 2-30.

TABLE 4-4: RESET DELAY TIMER TIME OUTS

FIGURE 4-10: Reset Power-up Timer Waveform.

Note: While the Reset delay timer (tRST) isactive, additional system current isconsumed.

tRSTUnits

Min Typ Max

140 280 560 ms↑ ↑

This is the minimum time that

the Reset delay timer will “hold” the

Reset pin active after VDD rises above VTRIP

This is the maximum time that the Reset delay timer will

“hold” the Reset pin active after

VDD rises above VTRIP

VTRIP

VDD

RST tRST

Reset DelayTimer Inactive

ResetDelayTimerInactiveR

eset

Del

ayTi

mer

Act

ive

See Figures 2-9,2-7 and 2-8

See Figures 2-12, 2-11 and 2-10

See Figures 2-9,2-7 and 2-8


TC1270A/71A

5.0 APPLICATION INFORMATIONThis section shows application related information thatmay be useful for your particular design requirements.

5.1 Supply Monitor Noise SensitivityThe TC127XA devices are optimized for fast responseto negative-going changes in VDD. Systems with aninordinate amount of electrical noise on VDD (such assystems using relays) may require a 0.01 µF or 0.1 µFbypass capacitor to reduce detection sensitivity. Thiscapacitor should be installed as close to the TC127XAas possible to keep the capacitor lead length short.

FIGURE 5-1: Typical Application Circuit with Bypass Capacitor.

5.2 Conventional Voltage MonitoringFigure 5-2 and Figure 5-3 show the TC127XA inconventional voltage monitoring applications.

FIGURE 5-2: Battery Voltage Monitor.

FIGURE 5-3: Power Good Monitor.

TC127XAVDD

RST

VSS

0.1 µF

RSTMR

VDD

RST

VSS

BATLOWTC127XA

+

––

VDD

RST

VSS

Power GoodTC127XA

+

–

PwrSply


TC1270A/71A
5.3 Modifying The Trip Point, VTRIPAlthough the TC127XA device has a fixed voltage trippoint (VTRIP), it is sometimes necessary to makecustom adjustments. This can be accomplished byconnecting an external resistor divider to the TC127XAVDD pin. This causes the VSOURCE voltage to be at ahigher voltage than when the TC127XA input equalsit’s VTRIP voltage (Figure 5-4).
To maintain detector accuracy, the bleeder currentthrough the divider should be significantly higher thanthe 10 µA maximum operating current required by theTC127XA. A reasonable value for this bleeder currentis 1 mA (100 times the 10 µA required by theTC127XA). For example, if VTRIP = 2V and the desiredtrip point is 2.5V, the value of R1 + R2 is 2.5 kΩ(2.5V/1 mA). The value of R1 + R2 can be rounded tothe nearest standard value and plugged into theequation of Figure 5-4 to calculate values for R1 andR2. 1% tolerance resistors are recommended.

FIGURE 5-4: Modify Trip-Point using External Resistor Divider.

5.4 Controllers and Processors With Bidirectional I/O Pins

Some microcontrollers have bidirectional Reset pins.Depending on the current drive capability of thecontroller pin, an indeterminate logic level may result ifthere is a logic conflict. This can be avoided by addinga 4.7 kΩ resistor in series with the output of theTC127XA (Figure 5-5). If there are other componentsin the system that require a Reset signal, they shouldbe buffered so as not to load the Reset line. If the othercomponents are required to follow the Reset I/O of themicrocontroller, the buffer should be connected asshown with the solid line.

FIGURE 5-5: Interfacing the TC1270A or TC1271A Push-Pull Output to a Bidirectional Reset I/O pin.

5.5 Migration PathsFigure 5-6 shows the 5-pin SOT-23 footprint of theTC1270A and TC1271A devices. Devices that are inthe 3-pin SOT-23 package could be used in that circuitwith the loss of the Manual Reset functionality.Examples of compatible footprint devices in theSOT-23-3 package are the MCP111, MCP112, TC54,and TC51 devices. This allows the system to bedesigned to offer a “base” functionality and a higherend system with the “enhanced” functionality, whichincludes a manual reset.

FIGURE 5-6: SOT-23 5-pin to 3-pin Comparison.

Note: In this example, VSOURCE must begreater than (VTRIP)

TC127XAVDD RST

VSSR1

VSOURCE

R2

or RST

VSOURCE

R1R1 R2+--------------------× VTRIP=

Where:

VSOURCE = Voltage to be monitoredVTRIP = Threshold Voltage setting

MR

VSS VSS

VDDVDD

RST Reset I/O

TC1270A/71A

VDD

orRST

BufferedReset tosystem

4.7 kΩ

3

2

1

SOT-23-3

1

2

3

5

4

SOT-23-5

NC

VDD

MRRST

VSS VSS

VDD

orRST

RSTorRST


TC1270A/71A
5.6 Reset Signal Integrity During
Power-DownThe TC1270A and TC1271A reset output is valid downto VDD = 1.0V. Below this voltage the output becomesan “open circuit” and does not sink current. This meansCMOS logic inputs to the Microcontroller will be floatingat an undetermined voltage. Most digital systems arecompletely shut down well above this voltage.However, in situations where the Reset signal must bemaintained valid to VDD = 0V, external circuitry isrequired.

For devices where the Reset signal is active-low, apull-down resistor must be connected from theTC1270A RST pin to ground to discharge straycapacitances and hold the output low (Figure 5-7).

Similarly for devices where the Reset signal isactive-high, a pull-up resistor to VDD is required toensure a valid high RST signal for VDD below 1.0V(Figure 5-8).

This resistor value, though not critical, should bechosen such that it does not appreciably load the Resetpin under normal operation (100 kΩ will be suitable formost applications).

FIGURE 5-7: Ensuring a valid active-low Reset pin output state as VDD approaches 0V.

FIGURE 5-8: Ensuring a valid active-high Reset pin output state as VDD approaches 0V.

MR

VSS

VDD

RST

TC1270A

VDD

R1100 kΩ

MR

VSS

VDD

RST

TC1271A

VDD

R1100 kΩ


TC1270A/71A

6.0 STANDARD DEVICES Table 6-1 shows the standard devices and their ordernumber that are available and their respectiveconfiguration.

The configuration includes the:

• Voltage Trip Point (VTRIP)

TABLE 6-1: STANDARD VERSIONS

Device

Reset Threshold (V) Reset Time Out (ms)

Pack

age

Order Number Replaces

Min

imum

Typi

cal

Max

imum

Cod

e

Min

imum

Typi

cal

Max

imum

Cod

e

TC1270A 4.50 4.63 4.75 L 140 280 560 “blank”SOT-23-5 TC1270ALVCTTR —

SOT-143 TC1270ALVRCTR TC1270LERC / TCM811LERC

TC1270A 4.25 4.38 4.50 M 140 280 560 “blank”SOT-23-5 TC1270AMVCTTR —

SOT-143 TC1270AMVRCTR TC1270MERC / TCM811MERC

TC1270A 3.00 3.08 3.14 T 140 280 560 “blank”SOT-23-5 TC1270ATVCTTR —

SOT-143 TC1270ATVRCTR TC1270TERC / TCM811TERC

TC1270A 2.85 2.93 3.00 S 140 280 560 “blank”SOT-23-5 TC1270ASVCTTR —

SOT-143 TC1270ASVRCTR TC1270SERC / TCM811SERC

TC1270A 2.55 2.63 2.70 R 140 280 560 “blank”SOT-23-5 TC1270ARVCTTR —

SOT-143 TC1270ARVRCTR TC1270RERC / TCM811RERC

TC1271A 4.50 4.63 4.75 L 140 280 560 “blank”SOT-23-5 TC1271ALVCTTR —

SOT-143 TC1271ALVRCTR TC1271LERC / TCM812LERC

TC1271A 4.25 4.38 4.50 M 140 280 560 “blank”SOT-23-5 TC1271AMVCTTR —

SOT-143 TC1271AMVRCTR TC1271MERC / TCM812MERC

TC1271A 3.00 3.08 3.14 T 140 280 560 “blank”SOT-23-5 TC1271ATVCTTR —

SOT-143 TC1271ATVRCTR TC1271TERC / TCM812TERC

TC1271A 2.85 2.93 3.00 S 140 280 560 “blank”SOT-23-5 TC1271ASVCTTR —

SOT-143 TC1271ASVRCTR TC1271SERC / TCM812SERC

TC1271A 2.55 2.63 2.70 R 140 280 560 “blank”SOT-23-5 TC1271ARVCTTR —

SOT-143 TC1271ARVRCTR TC1271RERC / TCM812RERC


TC1270A/71A

7.0 CUSTOM CONFIGURATIONSThe following Custom Reset Trip Point is available (seeTable 7-1).

TABLE 7-1: CUSTOM TRIP POINT

Trip Voltage

Selection

VTRIP(MAX)/

VTRIP(MIN)

- % From Regulated Voltage

3.0V(1) 2.85V 5.0%

2.70V 10.0%Note 1: Contact factory for additional information.


TC1270A/71A

8.0 DEVELOPMENT TOOLS

8.1 Evaluation/Demonstration BoardsThe SOT-23-5/6 Evaluation Board (VSUPEV2) can beused to evaluate the characteristics of the TC127XAdevices.

This blank PCB has footprints for:

• Pull-up Resistor• Pull-down Resistor• Loading Capacitor• In-line Resistor

There is also a power supply filtering capacitor.

For evaluating the TC127XA devices, the selecteddevice should be installed into the Option A footprint.

FIGURE 8-1: SOT-23-5/6 Voltage Supervisor Evaluation Board (VSUPEV2).

The SOIC14-EV (102-00094) board has a SOT-23-6footprint, that can be jumpered into any portion of thecircuit. This will allow any footprint that the TC1270Arequires in the SOT-23-5 package.

FIGURE 8-2: SOIC-14 Evaluation Board (SOIC14EV).These boards may be purchased directly from theMicrochip web site at www.microchip.com.


TC1270A/71A

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

5-Pin SOT-23

Part Number Code Part Number Code

TC1270ALVCTTR F1NN TC1271ALVCTTR J1NNTC1270AMVCTTR F2NN TC1271AMVCTTR J2NNTC1270ATVCTTR F3NN TC1271ATVCTTR J3NNTC1270ASVCTTR F4NN TC1271ASVCTTR J4NNTC1270ARVCTTR F5NN TC1271ARVCTTR J5NN

Example:

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

XXNN F125

4-Lead SOT-143

XXNN

Example:

C125

Part Number Code Part Number Code

TC1270ALVRCTR D1NN TC1271ALVRCTR C1NNTC1270AMVRCTR D2NN TC1271AMVRCTR C2NNTC1270ATVRCTR D3NN TC1271ATVRCTR C3NNTC1270ASVRCTR D4NN TC1271ASVRCTR C4NNTC1270ARVRCTR D5NN TC1271ARVRCTR C5NN


TC1270A/71A

5-Lead Plastic Small Outline Transistor (OT or CT) [SOT-23]

Notes:1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 5

Lead Pitch e 0.95 BSC

Outside Lead Pitch e1 1.90 BSC

Overall Height A 0.90 – 1.45

Molded Package Thickness A2 0.89 – 1.30

Standoff A1 0.00 – 0.15

Overall Width E 2.20 – 3.20

Molded Package Width E1 1.30 – 1.80

Overall Length D 2.70 – 3.10

Foot Length L 0.10 – 0.60

Footprint L1 0.35 – 0.80

Foot Angle φ 0° – 30°

Lead Thickness c 0.08 – 0.26

Lead Width b 0.20 – 0.51

φ

Nb

E

E1

D

1 2 3

e

e1

A

A1

A2 c

L

L1

Microchip Technology Drawing C04-091B


TC1270A/71A

4-Lead Plastic Small Outline Transistor (RC) [SOT-143]

Notes:1. § Significant Characteristic.2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 4

Pitch e 1.92 BSC

Lead 1 Offset e1 0.20 BSC

Overall Height A 0.80 – 1.22

Molded Package Thickness A2 0.75 0.90 1.07

Standoff § A1 0.01 – 0.15

Overall Width E 2.10 – 2.64

Molded Package Width E1 1.20 1.30 1.40

Overall Length D 2.67 2.90 3.05

Foot Length L 0.13 0.50 0.60

Footprint L1 0.54 REF

Foot Angle φ 0° – 8°

Lead Thickness c 0.08 – 0.20

Lead 1 Width b1 0.76 – 0.94

Leads 2, 3 & 4 Width b 0.30 – 0.54

D

e

e/2

N

E

E1

21

e1

A

A1b2

A2

3X b

c

LL1

φ

Microchip Technology Drawing C04-031B


TC1270A/71A
9.2 Product Tape and Reel Specifications
FIGURE 9-1: EMBOSSED CARRIER DIMENSIONS (8 MM TAPE ONLY)

FIGURE 9-2: 5-LEAD SOT-23 DEVICE TAPE AND REEL SPECIFICATIONS

TopCoverTape

K0

P

W

B0

A0

TABLE 1: CARRIER TAPE/CAVITY DIMENSIONS

Case Outline

Package Type

Carrier Dimensions

Cavity Dimensions Output

QuantityUnits

Reel Diameter in

mmWmm

Pmm

A0mm

B0mm

K0mm

OT SOT-23 5L 8 4 3.2 3.2 1.4 3000 180RC SOT-143 4L 8 4 3.1 2.69 1.3 3000 180

User Direction of Feed

P, Pitch

Standard Reel Component Orientation Reverse Reel Component Orientation

W, Width

of Carrier

Tape

Pin 1

Pin 1

Device

Marking


TC1270A/71A
FIGURE 9-3: 4-LEAD SOT-143 DEVICE TAPE AND REEL SPECIFICATIONS
Component Taping Orientation for 4-Pin SOT-143 Devices

Pin 1

DeviceMarking

User Direction of Feed

Standard Reel Component Orientationfor TR Suffix Device(Mark Right Side Up)

W

P

Carrier Tape, Number of Components Per Reel and Reel Size:

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

4-Pin SOT-143 8 mm 4 mm 3000 7 in.


TC1270A/71A
NOTES:

TC1270A/71A

APPENDIX A: REVISION HISTORY

Revision A (March 2007)• Original Release of this Document.


TC1270A/71A
NOTES:

TC1270A/71A

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: TC1270A: Voltage Supervisor with Manual Reset

TC1271A: Voltage Supervisor with Manual Reset

VTRIP Options: R = 2.55V (min.) / 2.63V (typ.) / 2.70V (max.)S = 2.85V (min.) / 2.93V (typ.) / 3.00V (max.)T = 3.00V (min.) / 3.08V (typ.) / 3.15V (max.)M = 4.25V (min.) / 4.38V (typ.) / 4.50V (max.)L = 4.50V (min.) / 4.63V (typ.) / 4.75V (max.)

Temperature Range: V = -40°C to +125°C

Package: CT = Plastic Small Outline Transistor, SOT-23, 5-leadRC = Plastic Small Outline Transistor, SOT-143,

4-lead

Tape/Reel Option: TR = Tape and Reel

PART NO. X X

TemperatureVTRIPOptions

Device

Examples:a) TC1270ASVCTTR:

2.85V min. / 2.93V typ. / 3.00V max.voltage trip point, Push-pull active low reset, Reset Delay Timer = 280 ms, 5-LD SOT-23, Tape and Reel, -40°C to +125°C

b) TC1270ALVRCTR: 4.50V min. / 4.63V typ. / 4.75V max.voltage trip point, Push-pull active low reset, Reset Delay Timer = 280 ms, 4-LD SOT-143, Tape and Reel,-40°C to +125°C

c) TC1271ARVCTTR: 2.55V min. / 2.63V typ. / 2.70V max.voltage trip point, Push-pull active high reset, Reset Delay Timer = 280 ms, 5-LD SOT-23, Tape and Reel, -40°C to +125°C

d) TC1271ATVRCTR: 3.00V min. / 3.08V typ. / 3.15V max.voltage trip point, Push-pull active high reset, Reset Delay Timer = 280 ms, 4-LD SOT-143, Tape and Reel,-40°C to +125°C

Range

XX

Package

XX

Tape/ReelOption


TC1270A/71A
NOTES:

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

© 2007 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

DS22035A-page 37

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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