1.Introduction to Philosophy of Testing:If anything can go wrong, it will--A very well known statement known as Murphy's Law. So, to ensure that only fault free systems are delivered, before deploying any system in the field or shipping a product to a customer, it needs to beTested.Testing a system comprises subjecting it to inputs and checking its outputs to verify whether it behaves as per the specifications targeted during design. Let us take the simple example of an electric iron. From our daily life experience, testing in this case would be to plug it in 220V AC and see if is heating. In this simple example also, testing may not be so straight foreword as mentioned above. Test for heating is just verifying its functional specification, that also partially. A near complete test will require the following Safety: All exposed metal parts of the iron are grounded Auto-off on overheating Detailed Functionality Heating when powered ON. Glowing of LED to indicate power ON. Temperature matching with specification for different ranges that can be set using the regulator (e.g., woolen, silk, cotton etc.) Performance Power consumption as per the specifications Time required to reach the desired temperature when range is changed using the regulatorThe story is not over. The list discussed above is the set of tests for ONLYelectrical parameters. Similarly, there will be a full list of tests formechanical parameters, like maximum height from which there is resistance to breaking of plastic parts if dropped on a tiled floor etc.The number of tests performed depends on the time being allocated and which in turn is decided by the target price of the product. Increasing the number of tests lead to more test time, requirement of sophisticated equipments, working hours of experts etc. thereby adding to cost of the product. In case of example of the iron, if it is a cheap one (may be local made) the only test is to verify if it heats, while if it is branded, a lot more tests are done to assure quality, safety and performance of the product.Now let us take an example of testing a NAND gate, shown in Figure 1.

Figure 1. NAND gate

The simple test to verify the proper functionality of the NAND gate would comprise subjecting the gate with inputs listed in Table 1 and then checking if the outputs match the ones listed in the table.Table 1. Test set for NAND gate

Just like the example of the electric iron, this test for the NAND gate is just the starting point. A more detailed test can be enumerated as followsDetailed tests for the NAND gate Digital Functionality...... .. Verify input/output of Table 1 Delay Test........ 0 to 1: time taken by the gate to rise from 0 to 1...........v1=1, v2=1changed tov1=1, v2=0;After this change in input, time taken byo1to changefrom 0 to 1.............v1=1, v2=1changed tov1=0, v2=1;After this change in input, time taken byo1to changefrom 0 to 1.............v1=1, v2=1changed tov1=0, v2=0;After this change in input, time taken byo1to changefrom 0 to 1........ . 1 to 0: time taken by the gate to fall from 1 to 0............. v1=0, v2=0changed tov1=1, v2=1;After this change in input, time taken byo1to changefrom 1 to 0................v1=1, v2=0changed tov1=1, v2=1;After this change in input, time taken byo1to changefrom 1 to 0.................v1=0, v2=1changed tov1=1, v2=1;After this change in input, time taken byo1to changefrom 1 to 0. Fan-out capability:........ Number of gates connected ato1which can be driven by the NAND gate. Power consumption of the gate....... . Static power: measurement of power when the output of the gate is not switching. This power is consumed because of leakage current....... . Dynamic power: measurement of power when the output of the gate switches from 0 to 1 and from 1 to 0. Threshold Level...... . Minimum voltage at input considered at logic 1...... . Maximum voltage at input considered at logic 0...... . Voltage at output for logic 1..... .. Voltage at output for logic 0 Switching noise...... . Noise generated when the NAND gate switches from 0 to 1 and from 1 to 0 Test at extreme conditions...... . Performing the tests at temperatures (Low and High Extremes) as claimed in the specification document.These tests are for the logic level [1,2] implementation of the NAND gate.Figure 2 shows the detailed CMOS level implementation of the gate. Tests for the NAND gate at transistor level would be many fold more than the ones discussed above [3]. They would comprise verifying all parameters of a transistor. Some tests for the NMOS (T3) are enumerated below, Output Characteristics a set of IDSvs VDScurves for different constant values of the gate-source voltage VGS Transfer characteristics a set of IDSvs VGScurves for different values of the substrate-source voltage VBS, at constant VDS Threshold Voltage Test Threshold Voltage obtained in test, matches the specificationsFurther, all the tests for a transistor need to be repeated for all the four transistors involved. Last but not the least, Transistor T1 and T2 are to be matched (i.e., equivalent in terms of parameters) and similarly for T3 and T4. To summarize, as more details of implementation of a gate (or any circuit) is considered, test procedure becomes more complex.Figure 2. CMOS implementation of the NAND gateNow, Figure 3 shows the layout of the gate in a silicon die. Once can easily estimate the number of tests by looking at the increase in complexity from logic gate level details to silicon level details.

Figure 3. Layout of a NAND gate in a silicon dieSo now the question is,given a digital logic gate, what tests are to be performed to assure an acceptable quality of product at reasonable price.Ideally speaking, all testes at silicon level, transistor level and logic level are to be performed. It is to be noted that in a typical digital IC, there are some tens of thousands of logic gates and about a million samples to be tested. So time for complete testing of the ICs would run into years. Thus, test set for the NAND gate should be such that results are accurate (say 99% above) yet time for testing is low (less than a millisecond). Under this requirement, it has been seen from experience over a large number of digital chips that nothing more than validating the logical functionality (Table 1 for the NAND gate) and at proper time (i.e., timing test) can be accomplished. Latter we will see that not even the full logic functionality of a typical circuit can be tested within practical time limits.Now we define DIGITAL TESTING. DIGITAL TESTING isnottesting digital circuits (comprised of logic gates); as discussed, all tests possible for a digital circuit are not applied in practical cases.DIGITAL TESTING is defined as testing a digital circuit to verify that it performs the specified logic functions and in proper time.For the discussion so far, it may appear that testing digital VLSI circuits and other systems like electrical iron are similar. However, there are some fundamental differences that make VLSI circuit testing more important step to assure quality, compared to classical systems like electric iron, fan etc.The intension to make single chip implementation of complex systems has reached a point where effort is made to put millions of transistors on a single chip and increase the operation speed to more than a GHz. This has initiated a race to move into deep sub-micron technology, which also increases the possibility of faults in the fabricated devices. Just when a technology matures and faults tend to decrease, a new technology based on lower sub-micron devices evolves, thereby always keeping testing issues dominant. Figure 4 shows the transistor count (which rises with lowering the sub-micron of the manufacturing technology) versus years. This is unlike traditional systems where the basic technology is matured and well tested, thereby resulting in very less number of faults.In case of detection of faults in a traditional system it is diagnosed and repaired. However, in case of circuits, on detection of a fault the chip is binned as defective and scrapped (i.e., not repaired). In other words, in VLSI testing chips are to be binned as normal/faulty so that only fault free chips are shipped and no repairing is required for faulty ones.

Figure 4. Transistor count versus years (taken from [5])2. Digital Testing In A VLSI Design FlowFigure 5 illustrates a typical digital VLSI design and test flow. This starts with the development of the specifications for the system from the set of requirements, which includes functional (i.e., input-output) characteristics, operating characteristics (i.e., power, frequency, noise, etc.), physical and environmental characteristics (i.e., packaging, humidity, temperature, etc.) and other constraints like area, pin count, etc. This is followed by an architectural design to produce a system level structure of realizable blocks for the functional specifications. These blocks are then implemented at resister transfer level (RTL) using some hardware definition language like Verilog or VHDL. The next step, called logic design, further decomposes the blocks into gates maintaining operating characteristics and other constraints like area, pin count, etc. Finally, the gates are implemented as physical devices and a chip layout is produced during the physical design. The physical layout is converted into photo masks that are used in the fabrication process. Fabrication consists of processing silicon wafers through a series of steps involving photo resist, exposure through masks, etching, ion implantation, etc. Backtrack from an intermediary stage of the design and test flow may be required if the design constraints are not satisfied. It is unlikely that all fabricated chips would satisfy the desired specifications. Impurities and defects in materials, equipment malfunctions, etc. are some causes leading to the mismatches. The role of testing is to detect the mismatches, if any. As shown in Figure 5, the test phase starts in form of planning even before the logic synthesis and hardware based testing is performed after the fabrication. Depending on the type of circuit and the nature of testing required, some additional circuitry, pin out, etc. need to be added with the original circuit so that hardware testing becomes efficient in terms of fault coverage, test time, etc.; this is called design for testability (DFT). After logic synthesis, (binary) test patterns are generated that need to be applied to the circuit after it gets manufactured. Also, the expected responses (golden response) for these test patterns are computed which are matched with the response obtained from the manufactured circuit.

Figure 5. A typical digital VLSI design flowFigure 6 illustrates the basic operations of digital testing on a manufactured circuit. Binary test vectors are applied as inputs to the circuit and the responses are compared with the golden signature, which is the ideal response from a fault-free circuit.Figure 6. Digital VLSI test processThese test patters are generally applied and analyzed using automatic test equipment (ATE). Figure 7 shows the picture of an ATE from Teradyne [4].

Figure 7. Automatic Test Equipment3.Taxonomy of Digital TestingDigital testing can be classified according to several criteria. Table 2 summarizes the most important attributes of various digital testing methods and the associated terminology.Table 2. Taxonomy of digital testingCriterionAttributes of testing methodTerminology

When tested?1. Once after manufacture2. Once before startup of circuit3. Always during the system operation1. Manufacturing Test2. Built in self test (BIST)3. On-line testing (OLT)

Where is the source of Test patterns?1. An external tester2. Within the chip3. No patters applied, only monitoring1. Automatic Test Equipment (ATE) based testing2. BIST3. OLT

Where is the source of Test patterns?

Circuit in which form is being tested?

1. Wafer2. IC3. Board4. System1. Non packaged IC level testing2. Packaged level testing3. Board level testing4. System level testing

How are the test patterns applied?1. In a fixed predetermined order2. Depending on results1. Static Testing2. Adaptive testing

How fast are the test patterns applied?1. Much slower than the normal speed of operation

2.At normal speed of operation1. DC (static) testing2. At-speed testing

Who verifies the test results by matching with golden response?1. On chip circuit2. ATE

1. BIST2. Automatic Test Equipment (ATE) based testing

4. Test EconomicsThe basic essence of economics of a product is minimum investments and maximum returns. To under test economics the investments (price paid) and returns (gains) for a VLSI testing process are to be enumerated. Investments.....1.Man hours for test plan development:Expert test engineers are required to make elaborate test plans......2.CAD tools for Automatic Test Pattern GenerationGiven a circuit, binary input patters required for testing is automatically generated by commercial CAD tools......3.Cost of ATEATE is a multimillion dollar instrument. So cost of testing a chip in an ATE is dependent on......... time a chip is tested,......... the number of inputs/outputs pins......... frequency the test patters are to be applied.....4. DFT or BIST circuitryAdditional circuitry kept on-chip to help in testing results in raise in chip area, thereby by increasing the unit price (because of more use of silicon). Further, power consumption of the chip may also rise due to addition of extra circuits. Also, it may be noted that if individual chips are larger in area, then more number of fabricated chips are found faulty (i.e., yield is less). To cope up with fewer yields, cost of individual unit is increased.At-speed testing is more effective than lowered-speed testing. However, the ATEs that can perform at-speed testing for the latest chips are extremely expensive. It may be noted that generating and capturing high speed patterns using on-chip circuitry is manifold simple and cheaper than doing so using an external tester (ATE). So additional DFT/BIST circuit is required to apply patterns and capture response at high speed. Once the response is captured, they can be downloaded by the ATE at a lower speed for analysis. The BIST/DFT circuitry will reduce the yield of the VLSI chip, thus increasing the cost. As this cost increase is offset by cost reduction in ATE, this additional BIST/DFT circuitry is economically beneficial. Returns.......a) Proper binning of Chips:The more a testing process can be made perfect, the less will be the errors in binning the normal chips and the faulty ones. In case of VLSI testing, it is not of much concern as how many chips are binned as faulty, rather important is how many faulty chips are binned as normal. Faulty chips binned as normal are shipped and that compromises the quality of test solution and the brand name of the company. So, economic return from VLSI testing is the accuracy in shipping functionally perfect chips.From the next lectures, we will go into the details of Digital VLSI Testing. The tentative breakup of the lectures would be the following1.IntroductionIn the last lecture we learnt that Digital VLSI testing is to verify if logic functionality is as per the specifications. For example, for the 2 input NAND gate the test would comprise only the 4 input combinations and verifying the output. The time required to verify anything more than logic functionally is beyond practical limits in terms of ATE time, man hours, cost of the chip etc. Also, the quality of test solution (i.e., proper binning of normal and faulty chips) is acceptable for almost all classes of circuits. This is calledFunctional Testing.Now let us consider a digital circuit with 25 inputs which does bit wise ANDing of the inputs. The black box of the circuit is shown in Figure 1. The complete functional test is given in Table 1.

Figure 1. Circuit for Bit wise ANDingTable 1. Test patterns for functional testing of circuit in Figure 1Test Pattern No.Test Pattern

Output

100000000000000000000000000

200000000000000000000000010

....................

0

22511111111111111111111111111

We need to apply 225test patterns to complete the test. If we apply 1000000 patterns per second (Mega Hz Tester), then time required is 33 Seconds per chip. In a typical scenario about 1 million chips are to be tested in a run, thereby taking about 33000000 Seconds or 550000 Hours or 22916 Days or 62 years. So one can understand the complexity when a circuit has 100+ inputs. So for a typical circuit evenFunctional Testingcannot beperformed due to extremely high testing time.To solve this issue we performStructural Testing,which takes many fold less time compared Functional Testingyet maintaining the quality of test solution. Structural testing, introduced by Eldred, verifies the correctness of the specific structure of the circuit in terms of gates and interconnects. In other words, structural testing does not check the functionality of the entire circuit rather verifies if all the structural units (gates) are fault free. So structural testing is a kind of functional testing at unit (gate) level.In the next section we elaborate the gain in test time for structural testing using the example of the 25 input ANDing circuit. Also, the cost that needs to be paid is illustrated using the same example.2.Structural Testing: An Example Of 25 Input Bit Wise ANDing CircuitTo perform structural testing a white box view of the circuit (i.e., gate level implementation) is required. Following that functional testing would be performed on the individual gates. Figure 2 shows a gate level implementation of the 25 input bit wise ANDing circuit (of Figure 1).Structural testing for the circuit would comprise the patters discussed below:1. Testing of the 5 input AND gate G1 with the input patterns as given in Table 2.Table 2. Test patterns for testing of gate G1Test Pattern (I1,I2,I3,I4,I5)

Output

1000000

2000010

..

0

32111111

2. Repeat similar test patterns for all the 5 input AND Gates G2, G3, G4, G5 and G6.

Figure 2. Gate level implementation for Bit wise ANDing circuitSo number of test patterns required are 6.25So number of test patterns required are 6.25 (=160), which is many fold smaller than those required for functional testing (225). In this case, time required for testing the circuit the using a 1 Mega Hz Tester is 0.000016 seconds and for a million samples is 16 seconds. Now we can easily see the benefits for structural testing over functional testing. However, some piece is to be paid for the benefits obtained, as listed below1. Each individual gate is tested; however, the integration is not tested. From history of several thousand cases of chips being fabricated and tested, it was observed that the quality of test solution given by structural testing is acceptable.2. To test the individual gates, controlling and observing values of intermediary nets in a circuit becomes mandatory, which adds to extra pins and hardware. For example, to test Gate G1 (for circuit shown in Figure 2) we need to apply signals at pins I1 through I5 which are primary inputs and brought out of the chip as pins. But we also need to observe the output at net OG1, which is difficult as it is not a primary output and is internal to the chip. So, for structural testing, involving testing of Gate G1 individually, OG1 is to be brought out of the chip as a special output (test) pin. Similarly for individual testing of the gates G2 through G5, lines OG2 through OG5 are to be made observable by additional pin outs.So for structural testing some internal nets are to be made observable by extra pin outs.3. Now for testing G6, the problem is different. The output of the gate G6 can be observed as it is a primary output. However, to test G6, inputs are to be given through internal nets OG1 through OG5. It may be noted that these nets are outputs of other AND gates and to drive these nets directly to a required value, not only they are to be brought out of the chip as pins but also are to be decoupled from the corresponding AND gates.So for structural testing some internal nets are to be made controllable by extra pin outs and circuitry.Controllability is achieved by adding extra 2-1 Multiplexers on these nets. This is illustrated in Figure 3 (as bold lines boxes). During normal operation of the circuit the Test Mode signal (i.e., connected to select lines of the 2-1 Multiplexers) is made 1; the outputs of the AND gates (G1-G5) are passed to the inputs of the AND gate G6. When G6 is to be tested, Test Mode signal is made 0; inputs to Gate G6 are decoupled from Gates G1 through G5 and now they can be driven directly by additional input pins TI1 through TI5. These additional circuits (Multiplexers and pins) to help in structural testing are called Design for Testability (DFT).Figure 3. Extra pins and hardware for structural testing of circuit of Figure 2.It is to be noted that a circuit with about a million internal lines needs a million 2-1 Multiplexers and same number of extra pins. This requirement is infeasible. So let us see in steps how these problems can be minimized, yet maintaining quality of test solution. In the next section we illustrate using an example, to show internal memory can reduce extra pin outs for DFT.3. Structural Testing With Internal Memory: An Example Of A 32 Bit AdderA 32-bit adder shown is Figure 4 requires 232test patterns for exhaustive functional testing. As discussed in last section, structural testing of the 32-bit adder can reduce the testing time to a great extent. In this case, we consider a full adder as one structural unit (like the AND gates for the circuit in Figure 2). The implementation of the 32-bit adder in terms full adders (i.e., structural units) is also shown in Figure 4. Now we illustrate how structural testing of the 32-bit adder can be done with only 8(=23) test patterns and 3 extra pin outs. The 32-bit adder with DFT circuitry is shown in Figure 5.Figure 4. A 32-bit adderThe DFT circuitry comprises, 2 31-bit shift registers, 31 2-1multiplexers and 3 pin outs. One shift register (called input register) provides inputs to the ``carry input'' bits of the individual adders during test and the other shift register (called output register) latches outputs from the ``carry output'' bits of the individual adders. In the modified 32-bit adder, the carry input to theith(full) adder is multiplexed with thei th-bit of the input shift register, 1 i 31. During normal operation of the 32-bit adder, the multiplexers connect the carry input of theith(full) adder to the carry output of the (i-1)th(full) adder, 1 i 31. However, during test, the multiplexers connect the carry input of theith(full) adder to the output of theith-bit of the input shift register, 1 i 31 . The values in the shift register are fed externally. It may be noted that by this DFT arrangement all the (full) adders can be controlled individually as direct access is provided to the carry inputs of the adders; inputs other than carry are already controllable. Hence, testing in this case would be for each (full) adder individually and that requires 8 test vectors as each of the 32 full adders can be tested in parallel.Correct operations of each of the full adders are determined by looking at the sum and the carry outputs. Sum outputs are already available externally and hence no DFT circuit is required to make them directly observable. For the carry outputs, however, another similar DFT arrangement is required to make them observable externally. This would require the output (31 bit parallel load and) shift register where the carry output bit of the (i-1) thadder is connected to theithinput of the output shift register, 1 i 31. Once the values of all the carry bits are latched in the register, which is done in parallel during test, they are shifted out sequentially. In this case a full adder is tested functionally and structural information is used at the cascade level.

Figure 5. A 32-bit adder with DFT circuitry

Now let us see the gains and costs paid by the DFT circuitry (shift registers) for structural testing Gain:.. ....... Instead of 2 32 test patters for functional testing, only 2 3 patterns are enough for structural testing......... The number of extra pins for structural testing is only 3. It many be noted that if shift register is not used, then extra pins required are 64 as carry output bit of the full adders are to be brought out for observation and carry in bit of the full adders are to be brought out for sending the required test signal (controllability). Price......... 2-1 Multiplexers and registers are required for each internal net to controlled......... Registers required for each internal net to observed......... 3 extra pin outsFrom Section 2 and Section 3 we note that by the use of internal registers, the problem of huge number of extra pins could be solved but it added to requirement of huge size of shift registers (equal to number of internal nets). In a typical circuit there are tens of thousand of internal lines, making the on-chip register size and number of 2-1 multiplexers extremely high. So addition to cost of a chip by such a DFT is unacceptable.So our next target for achieving an efficient structural testing is the one with less number of on-chip components and yet maintaining the quality of test solution. Structural testing with Fault Models is the answer to the requirement. In the next section we will study Fault Models and then see why DFT requirement is low when structural testing is done with fault models.Before going to next section, to summarize, ``structural testing is functional testing at a level lower than the basic input-output functionality of the system''. For the example of the bitwise ANDing circuit, unit for structural testing was gates and for the case of 32-bit adder it was full adders. In general, in the case of digital circuits, structural testing is ``functional testing at the level of gates and flip-flops''. Henceforth in this course, basic unit of a circuit for structural testing would be logic gates and flip-flops.4. Structural Testing with Fault Models

Structural testing with fault models involves verifying each unit (gate and flip flop) is free from faults of the fault model.4.1 What is Fault ModelsA model is an abstract representation of a system. The abstraction is such that modeling reduces the complexity in representation but captures all the properties of the original system required for the application in question.So, fault model is an abstraction of the real defects in the silicon such that........ the faults of the model are easy to represent........ should ensure that if one verifies that no faults of the model are in the circuit, quality of test solution is maintained.In perspective of the present discussion, the following definitions are importantDefect:A defect in a circuit is the unintended difference between the implemented hardware in silicon and its intended design.Error:An error is an effect of some defect.Fault:Abstraction of a defect at the fault modeling level is called a fault.Let us consider an AND G1 of Figure 2, where due to incomplete doping of metal, net I1 is left unconnected with the gate; this is illustrated in Figure 5. This unconnected net I1 is the defect. Error is, when I1=1, I2=1,I3=1,I4=1, I5=1 but OG1=0 (should be 1 in normal case). Fault is, net I1 is stuck at 0 (when gate is modeled at binary logic level).Figure 5: AND gate with one net open

4.2 Widely Accepted Fault ModelsMany fault models were proposed [1,2], but the ones widely accepted are as followsStuck-at fault model:In this model, faults are fixed (0 or 1) value to a net which is an input or an output of a logic gate or a flip-flop in the circuit. If the net is stuck to 0, it is called stuck-at-0 (s-a-0) fault and if the net is stuck to 1, it is called stuck-at-1 (s-a-1) fault. If it is assumed that only one net of the circuit can have a fault at a time, it is called single stuck-at fault model. Without this assumption, it is called multiple stuck-at fault model. This has been observed though fabrication and testing history, that if a chip is verified to be free of single stuck-at faults, then it can be stated with more than 99.9% accuracy that there is no defect in the silicon or the chip is functionally (logical) normal. Further, single-stuck at fault is extremely simple to handle in terms of DFT required, test time etc.; this will be detailed in consequent lectures. So single stuck-at fault model is the most widely accepted model.Delay fault model:Faults under this model increase the input to output delay of one logic gate, at a time.Bridging Fault:A bridging fault represents a short between a group of nets. In the mot widely accepted bridging fault models, short is assumed between two nets in the circuit. The logic value of the shorted net may be modeled as 1-dominant (OR bridge), 0-dominant (AND) bridge. It has been observed that if a circuit is verified to be free of s-a faults, then with high probability it can be stated that there is no bridging fault also.Next we elaborate more on the stuck-at fault model which is most widely accepted because of its simplicity and quality of test solution.4.3Single Stuck-at Fault ModelFor single stuck-at fault model it is assumed that a circuit is an interconnection (called a netlist) of Boolean gates. A stuck-at fault is assumed to affect only the interconnecting nets between gates. Each net can have three states: normal, stuck-at-1 and stuck-at-0. When a net has stuck-at-1 (stuck-at-0) fault it will always have logic 1(0) irrespective of the correct logic output of the gate driving it. A circuit withnnets can have2npossible stuck-at faults, as under single-at fault model it is assumed that only one location can have a stuck-at-0 or stuck-at-1 fault at a time. The locations of stuck-at faults in the AND gate G1 (in the circuit of Figure 2) are shown in Figure 6 with black circles. G1 is a 5 input AND gate thereby having 5 input nets and an output net. So, there are 12 stuck-at faults possible in the gate.Figure 6: AND gate with stuck-at fault locationsNow let us consider another circuit shown in Figure 7 with fanouts, and see the stuck-at fault locations especially in the fanout net.Figure 7: Stuck-at fault locations in a circuit with fanoutsOutput of gate G1 drives inputs of gate G2 and G3. Here, the output net of G1 has three fault locations for stuck-at faults rather than one, as marked in Figure 7 by black circles. One point corresponds to output of gate G1 (OG1) and the other two to the inputs of gate G2 (OG1') and G3 (OG1). In other words, a net having fanout tokgates will havek+1stuck at fault locations; one for the gate output (stem of the fanout) and the others for the inputs of the gates that are driven (branches of the fanout). When the stuck-at fault is at the output of the gate (OG1, in this case) then all the nets in the fanout have the value corresponding to the fault. However, if fault is in one fanout (OG1' or OG1, in this case) then only the corresponding gate being driven by the branch of the fanout is effected by the stuck-at fault and others branches are not effected.Now the question remains, if fanout along with all its branches is a single electrical net, then why fault in a branch does not affect the others. The answer is again by history of testing of chips with single-stuck at fault model. It may be noted that a net getting physically stuck may not occur. When we perform structural testing with single stuck-at fault model, we verify that none of the sites have any stuck-at fault. Assuring this ensures with 99.9% accuracy that the circuit has no defect. Considering different branches of a fanout independent, more locations for stuck-at faults are created. Testing history on stuck-at faults has shown that this increased number of locations is required to ensure the 99.9% accuracy.To summarie, single stuck-at fault model is characterized by three assumptions:1. Only one net is faulty at a time.2. The faulty net is permanently set to either 0 or 1.3. The branches of a fanout net are independent with respect to locations and affect of a stuck-at fault.In general, several stuck-at faults can be simultaneously present in the circuit. A circuit withnlines can have 3n-1 possible stuck line combinations; each net can be: s-a-1, s-a-0, or fault-free. All combinations except one having all nets as normal are counted as faults. So handling multiple stuck-at faults in a typical circuit with some hundreds of thousands of nets is infeasible. As single stuck-at fault model is manageable in number and also provides acceptable quality of test solution, it is the most accepted fault model.Now we illustrate structural testing with single stuck-at fault model.4.4Structural Testing with Stuck-at Fault ModelWe will illustrate structural testing of stuck-at faults of the circuit in Figure 2.First let us consider s-a-0 in net I1, as shown in Figure 8. As the net I1 is stuck-at-0, we need to drive it to 1 to verify the presence/absence of the fault. To test if a net is stuck-at-0(stuck-at-1), obviously it is to be driven to opposite logic value of 1 (0). Now all other inputs (I2 through I5) of G1 are made 1, which propagates the effect of fault to OG1; if fault is present then OG1 is 0, else 1.To propagate the effect of fault to O, in a similar way, all inputs of G2 though G5 are made 1. Now, if fault is present, then O is 0, else 1. So, I1=1, I2=1,.,I25=1, is a test pattern for the stuck-at-0 fault at net I1.

Figure 8. s-a-0 fault in net I1 with input test patternNow let us consider s-a-1 in an internal net (output of G1), as shown in Figure 10. As the net output of G1 is stuck-at-1, we need to drive it to 0 to verify the presence/absence of the fault. So at least on input of G1 is to be made 0; at G1, I1=0 and I2 through I5 are 1. To propagate the effect of fault to O, all inputs of G2 though G5 are made 1. Now, if fault is present, then O is 1, else 0. So, I1=0, I2=1,.,I25=1, is a test pattern for the stuck-at-1 fault at net output of G1. It is interesting to note that same test pattern I1=0, I2=1,.,I25=1 tests both s-a-1 at net I1 and output of G1. In other words, in structural testing with stuck-at fault model, one test pattern can test more than one fault.

Figure 9. s-a-1 fault in net I1 with input test pattern

Now let us consider s-a-1 in an internal net (output of G1), as shown in Figure 10. As the net output of G1 is stuck-at-1, we need to drive it to 0 to verify the presence/absence of the fault. So at least on input of G1 is to be made 0; at G1, I1=0 and I2 through I5 are 1. To propagate the effect of fault to O, all inputs of G2 though G5 are made 1. Now, if fault is present, then O is 1, else 0. So, I1=0, I2=1,.,I25=1, is a test pattern for the stuck-at-1 fault at net output of G1. It is interesting to note that same test pattern I1=0, I2=1,.,I25=1 tests both s-a-1 at net I1 and output of G1. In other words, in structural testing with stuck-at fault model, one test pattern can test more than one fault.

Figure 10. s-a-1 fault in net OG1 with input test patternNow let us enumerate the gains and price paid for structural testing with stuck-at fault model Gains No extra pin outs or DFT circuitry like 2-1 Multiplexers and shift resisters for controlling and observing internal nets Low test time as one test pattern can test multiple stuck-at faults Price Functionality is not tested, even for the units (gates and Flip-flops). However, testing history reveals that even with this price paid, quality of test solution is maintained.To conclude, Table 2 compares Structural and Functional TestingTable 2. Comparison of structural and functional testingFunctional testingStructural Testing

Without fault models.With fault models.

Manually generated design verification test patterns.Automatic test pattern generation (ATPG).

Slow and labor intensive.Efficient and automated.

Fault coverage not knownFault Coverage is a quantified metric.

More Test PatternsLess Test Patterns

Can be applied at the operating speed.Difficult to be applied at the speed the design is expected to work.

1.IntroductionIn the last lecture we learnt that structural testing with stuck-at fault model helps in reduction of the number of test patterns and also there is no requirement of DFT hardware. If there arennets in a circuit then there can be 2nstuck-at faults and one test pattern can verify the presence/absence of the fault. So, the number of test patterns is liner in the number of nets in a circuit. Then we saw that one pattern can test multiple stuck-at faults, implying the total number of test patterns required is much lower than 2n.In this lecture we will see if faults can be reduced, utilizing the fact that one pattern can test multiple faults and retaining any of these faults would suffice. Let us consider the example of an AND gate in Figure 1, with all possible stuck-at-0 faults. To test the fault at I1, input pattern is I1=1,I2=1; if the output is 0, s-a-0 fault in I1 is present, else it is absent. Now, also for the s-a-0 fault in net I2, the pattern is I1=1,I2=1. Same, pattern will test the s-a-0 fault in the output net O. So, it may be stated that although there are three s-a- 0 faults only one pattern can test them. In other words, keeping one fault among these three would suffice and these faults are equivalent.Figure 1. Stuck-at-0 faults in an AND gateIn the next section, we will see in detail how equivalent faults can be found in a circuit and then collapse them to reduce the number of patterns required to test them.2. Fault Equivalence For Single Stuck-At Fault ModelTwo stuck-at faultsf1andf2are called equivalent iff the output function represented by the circuit withf1is same as the output function represented by the circuit withf2.Obviously, equivalent faults have exactly the same set of test patterns. In the AND gate of Figure 1, all stuck-at-0 faults are equivalent as they transform the circuit to O=0 and have I1=1, I2=1 as the test pattern.Now lets us see what stuck-at faults are equivalent in other logic gates. Figure 2 illustrates equivalent faults in AND, NAND , OR , NOR gates and Inverter with the corresponding test patterns. The figure is self explanatory and can be explained from the discussion of AND gate (Figure 1)Figure 2. Equivalent faults in AND, NAND , OR , NOR gates and inverter

However, an interesting case occurs for fanout nets. The faults in the stem and branches are not equivalent. This is explained as follows. Figure 3 shows the stuck-at faults in a fanout which drives two nets and the corresponding test patterns.Figure 3. No equivalence of stuck-at fault in fanout netIt may be noted that s-a-0 fault in the stem and the two branches have the same test pattern (I1=1), however these three faults do not result in same change of the output functions of the stem and the braches. For example, if s-a-0 fault is in the stem, function of stem is I1=0 and for the branch I1' (I1) function is I1'=0 (I1=0). So, fault at stem results in same output functions of the stem and the branches. However, if fault is in branch I1', then function of stem is I1=0/1 (as driven) and for the branch I1' (I1) function is I1'=0 (I1=I1). So output function of I1' is different from I1 and I1. Similar logic would hold for s-a-1 fault.Now we consider a circuit and see the reduction in the number of faults by collapsing using fault equivalence. Figure 4 gives an example of a circuit without any fanout and illustrates the step wise collapsing of faults. In a circuit, collapsing is done level wise as discussed below.

Figure 4. Circuit without fanout and step wise collapsing of equivalent faults. Step1: Collapse all faults at level-1 gates (G1 and G2). In the AND gate G1 (and G2) the s-a-0 faults at output and one input (first) are collapsed; s-a-0 fault is retained only at one input (second). Step-2: Collapse all faults at level-2 gates (G3). In the OR gate G3 the s-a-1 faults at output and one input (from G1) are collapsed; s-a-1 fault is retained only at one input (from G2).Now we consider a circuit with fanout. Figure 5 gives an example of a circuit with a fanout driving two nets and illustrates the step wise collapsing of faults. Step1: Collapse all faults at level-1 gate (G1). In the AND gate G1 the s-a-0 faults at output and one input (first) are collapsed; s-a-0 fault is retained only at one input (second). Step-2: Collapse all faults at level-2 gates (G2). In the OR gate G2 the s-a-1 faults at output and one input (from G1) are collapsed; s-a-1 fault is retained only at one input (from fanout net).Figure 5 Circuit with fanout and step wise collapsing of equivalent faults.Is collapsing by fault equivalence the only way to reduce the number of faults? The answer is no. In the next section we will discuss another paradigm to reduce stuck-at faultsby fault dominanceIf all tests of a stuck-at faultf1detect faultf2thenf2dominatesf1.Iff2dominantsf1thenf2can be removed and onlyf1is retained.Figure 6. Fault collapsing for AND gate using dominanceLet us consider the example of an AND gate with s-a-1 faults in the inputs and output. To test the s-a-1 fault in the input I1 of the gate, test pattern is I1=0,I2=1. Similarly, for the s-a-1 fault in the input I2 of the gate, test pattern is I1=1,I2=0. But for the s-a-1 fault in the output of the gate, test pattern can be one of the three (i) I1=0,I2=0, (ii) I1=1,I2=0 (iii) I1=0,I2=1. So s-a-1 fault at the output dominates the s-a-1 faults at the inputs. So collapsing using dominance would result in dropping the s-a-1 fault at the output and retaining only the faults at in inputs.The basic logic behind collapsing using dominance can be explained in simple logic as follows: If one retains the s-a-1 fault at the output and uses pattern I1=0,I2=0 to test it, then s-a-1 faults in the inputs are left untested. So faults at the inputs cannot be collapsed. However, if s-a-1 faults at the inputs are retained, then patterns 1=1,I2=0 and I1=0,I2=1 are applied, thereby testing the s-a-1 at the output twice. So, s-a-1 fault at the output can be collapsed and retain the ones at the inputs.Figure 7, illustrates dominant faults in AND, NAND , OR , and NOR gates and fault which can be collapsed.

Figure 7. Dominant faults in AND, NAND , OR , and NOR gates

Now we consider the circuits illustrated in Figure 4 and Figure 5 and see further reduction in the number of faults by collapsing using fault dominance. Figure 8 illustrates fault collapsing using dominance for the circuit without fanout. As in case of equivalence, collapsing using dominance is done in level wise as discussed below. Step1: Collapse all faults at level-1 gates (G1 and G2). In the AND gate G1 (and G2) the s-a-1 faults at output is collapsed; s-a-1 faults is retailed only at the inputs. Step-2: Collapse all faults at level-2 gates (G3). In the OR gate G3 the s-a-0 fault at output is collapsed and the s-a-0 faults at the inputs are retained.It may be noted that the s-a-0 faults at inputs of G3 are retained indirectly by s-a-0 faults at the inputs of G1 and G2 (using fault equivalence).

Figure 8. Circuit without fanout and step wise collapsing of faults using dominance.Now we consider the circuit with fanout given in Figure 5 and see reduction in the number of faults by collapsing using fault dominance (in Figure 9). The steps are as follows Step1: Collapse all faults at level-1 gate (G1). No faults can be collapsed. Step-2: Collapse all faults at level-2 gates (G2). In the OR gate G2 the s-a-0 fault at the output is collapsed, as s-a-0 fault at the inputs are retained; s-a-0 fault from the fanout branch is retained explicitly and the one at the output of gate G1 is retained indirectly by s-a-0 faults at the inputs of G1 (using fault equivalence).Figure 9. Circuit with fanout and step wise collapsing of faults using dominance.The following can be observed after faults are collapsed using equivalence and dominance:1. A circuit with no fanouts, s-a-0 and s-a-1 faults is to be considered only at the primary inputs (Figure 8(c)). So in a fanout free circuit test patters are 2. (Number of primary inputs).2. For circuit with fanout, checkpoints are primary inputs and fanout branches. Faults are to be kept only on the checkpoints (Figure 9(c)). So a test pattern set that detects all singlestuck-at faults of the checkpoints detects all single stuck-at faults in that circuit.Points 1 and 2 are termed as check point theorem.

uestion and Answers:1. For what class of circuits, maximum benefit is achieved due to fault collapsing and when the benefits are less? What is the typical number for test patterns required to test these classes of circuits?Answer1.For circuit with no fanouts, maximum benefit is obtained because faults in the primary inputs cover all other internal faults. So total number of test vectors are 2.(number of primary inputs).In a circuit with a lot of fanout branches, minimum benefit is obtained as faults need to be considered in all primary inputs and fanout branches. So total number of test vectors are 2.(number of primary inputs + number of fanout branches)............2. What faults can be collapsed by equivalence in case of XOR gate?Answer 2.From the figure given below it may be noted that all stuck-at faults in the inputs and output of a 2-input XOR gate, results in different output function. So fault collapsing cannot be done for XOR gate using fault equivalence.

1.IntroductionIn the last lecture we learnt how to determine a minimal set of faults for stuck-at fault model in a circuit. Following that a test pattern is to be generated for each fault which can determine the presence/absence of the fault under question. The procedure to generate a test pattern for a given a fault is called Test Pattern Generation (TPG). Generally TPG procedure is fully automated and called Automatic TPG (ATPG). Let us revisit one circuit discussed in last lecture and briefly note the steps involved in generating a test pattern for a fault. Consider the circuit in Figure 1 and s-a-1 fault at the output of gate G1. Three steps are involved to generate a test pattern1. Fault Sensitization: As the output net of G1 is stuck-at-1, we need to drive it to 0 to verify the presence/absence of the fault. So output of G1 is marked 0.2. Fault Propagation: Affect of the fault is to be propagated to a primary output (Output of G6, in this example). In this case, the propagation path is ``output of G1 to output of G6. For enabling this fault to propagate by this path, other inputs to G6 (from gate G2, G3, G4 and G5) are to be made 1. Affect of fault at the primary output is 1 if fault is present and 0 if fault is not present.3. Justification: Determination of values at primary inputs so that Fault sensitization and Fault propagation are successful. To sensitize fault (0 at output of G1), I1=0 and I2 through I5 are 1. To make outputs of gates G2, G3, G4 and G5 1, primary inputs I6 through I25 are made 1.So test pattern is I1=0 and I2 through I25 are 1. It may be noted that there are 2 5 -1 choices to sensitize fault (apply 0 at output of G1); all input combinations of G1 except I1=1, I2=1, I3=1, I4=1 and I5=1. However, to propagate the fault there is only one pattern (primary inputs I6 through I25 are made 1). TPG procedure would generate any one of the patterns given in Table 1Figure 1. s-a-1 fault in net OG1 with input test patternTable 1. Test patterns for the s-a-1 fault in the circuit of Figure 1TestPattern No.Test PatternI1 I2 I3 I4 I5 I6..................I25Output

10 0 0 0 0 11111111111111111111

1 if fault0 if no Fault

20 0 0 0 1 11111111111111111111

1 if fault0 if no Fault

.......................

....................

2251 1 1 1 0 111111111111111111111 if fault0 if no Fault

Now the question is, do we require these three steps for all faults? If this is the case, then TPG would take significant amount of time. However, we know that one test pattern can test multiple faults. In this lecture we will see how TPG time can be reduced using the concept of one TP can test multiple faults.Let us understand the basic idea of TPG time reduction on the example of Figure 1. Let us not try to generate a test pattern for a fault, rather apply a random pattern as see what faults are covered. Table 2 shows two random patterns and the faults they test. For example, the random pattern No. 1 generates a 0 at the output of G1, 1 at the outputs of gates G2 through G5 and 0 at the output of G6. It can be easily verified that this pattern can test s-a-1 fault at two locations................... output of G1.................. output of G6...........In case of faults, output at O is 1 and under normal conditions it is 0.However, the >> random pattern (No.2) can detect a lot more s-a faults in the circuit. It can test s-a-0 faults in all nets of the circuit. For example, let us take s-a-0 fault at output of G3. It can be easily verified that if this pattern is applied, O will be 0 if fault is present and 1 other wise. Similarly, we can verify that all possible s-a-1 faults in the circuit (31 in number) would be tested.Pattern No.Random PatternI1 I2 I3 I4 I5I6I25Faults Detected

11 0 0 0 1 11111111111111111111

s-a-1 at net output of G1s-a-1 at net output of G6

21 1 1 1 1 11111111111111111111s-a-0 faults in all the nets of the circuit

So we can see that by using 2 random patterns we have generated test patterns for 33 faults. On the other hand if we would have gone by the sensitize-propagate-justify approach these three steps would have been repeated 33 times. Now let us enumerate the steps used to generate the random test patters and determine the list of faults detected (called faults covered).............1. Generate a random pattern...........2. Determine the output of the circuit for that random pattern as input...........3. Take fault from the fault list and modify the Boolean functionally of the gate whose input has the fault. For example, in the circuit in Figure 1, the s-a-1 fault at the output of gate G1 modifies the Boolean functionality of gate G6 as1 AND I2 AND I3 AND I4 AND I5(which is equivalent toI2 AND I3 AND I4 AND I5) ............4. Determine output of the circuit with fault for that random pattern as input............5. If the output of normal circuit varies from the one with fault, then the random pattern detects the fault under consideration............6. If the fault is detected, it is removed from the fault list............7. Steps 3 to 6 are repeated for another fault in the list. This continues till all faults are considered............8. Steps 1 to 7 are repeated for another random pattern. This continues till all faults are detected.In simple words, new random patterns are generated and all faults detected by the pattern are dropped. This continues till all faults are detected by some (random) pattern. Now the question arises, How many random patterns are required for a typical circuit? The answer is very high. This situation is identical to the game of Balloon blasting with air gun. If there are a large number of balloons in the front, aim is not required and almost all shots (even without aim) will make a successful hit. However, as balloons become sparse blind hits would rarely be successful. So, the balloons left after blind shooting are to be aimed and shot. The same is true for testing. For initial few random patterns faults covered will be very high. However, as the number of random patterns increase the number of new faults being covered decreases sharply; this phenomenon can be seen from the graph of Figure 2. It may be noted that typically beyond 90% fault coverage, it is difficult to find a random pattern that can test a new fault. So, for the remaining 10% of faults it is better to use the sensitize-propagate-justify approach. These remaining 10% of faults are calleddifficult to test faults.

Figure 2. Typical scenario for fault coverage versus random patternsFrom the discussion we conclude that TPG can be done in two phases1. Use random patters, till a newly added pattern detects a reasonable number of new faults2. For the remaining faults, apply sensitize-propagate-justify approachAlso, it may be noted that determining the output of the circuit for a given input (with and without fault) is the key step for random pattern based TPG. In this lecture we will first algorithms for computing the output of a circuit given an input; this is calledcircuit simulation. Following that we will discuss efficient techniques to determine faults covered by random patterns, calledfault simulation..2. Circuit SimulationWhat is circuit simulation?The imitative representation of the functioning of circuits by means of another alternative, a computer program say, is called simulation. In digital laboratory (of undergraduate courses), breadboards were used to design systems using discrete chips. The same system can be developed using a single VLSI chip. However, we still prefer to do the breadboard design first, as the proof of concept. Breadboard based designs are used as proof of concept because we can predict the result of building the VLSI chip without actually building it. Further, errors can be easily rectified in the breadboard. So we may say that breadboard is a hardware based simulation of the VLSI chip. Breadboard has been used over decades for pre-design validation, however, is too cumbersome for large designs. Today, breadboards have been replaced by computer simulations. A circuit is converted into a computer program which generates the output given the input. Obviously, changes due to errors discovered are simple (than breadboard) as one needs to change only a computer program. There are several schemes of circuit simulation [1,2,3], and here we will see the ones related to fault simulation for the stuck-at fault model.Compiled Code SimulationAs the name suggests, Compiled Code method of simulation involves describing the circuit in a language that can be compiled and executed on a computer. The circuit description can be in a Hardware Description Language such as VHDL or Verilog [4] or simply described in C. Inputs, outputs and intermediary nets are treated as variables in the code which can be Boolean, integer, etc. Gates such as AND, OR, etc., are directly converted into program statements (using bit wise operator). For every input pattern, the code is repeatedly executed. Figure 3(A) shows a simple digital circuit and the corresponding C code required for its simulation is given in Figure 3(B). It may be noted that all 4 inputs, two intermediary nets (OG1 and OG2) and Output are represented as integer variables. All the gates are converted into single statements using bit wise operators.Figure 3(A). A Digital CircuitFigure 3(B). C code for the circuit of Figure 3(A) required for compiled code simulationCompiled code simulation is one of the simplest techniques of all circuit simulators. However, for every change in input the complete code is executed. Generally, in digital circuits, only 1-10% of signals are found to change at any time. For example, let us consider the circuit given in Figure 3(A) where input I1 changes from 1 to 0; this is illustrated in Figure 4. We can easily see that change in input modifies only 3 out of 8 lines. On the other hand a compiled code version would require reevaluation of all the 8 variables. >> we will discuss event-driven simulators which may not require evaluating all gates on changing of an input.Figure 4. Changes in signal values in a circuit for change in inputEvent Driven SimulationEvent-driven simulation is a very effective scheme for circuit simulation as it is based on detection of any signal change (event) to trigger other signal(s). So, an event triggers new events, which in turn may trigger more events; the first trigger is a change in primary input. Let us consider a circuit (the same one as of Figure 4) illustrated in Figure 5. Suppose, all signals are in steady-state by inputs I1=1, I2=1, I3=1,I4=1 when a new pattern I1=0, I2=1, I3=1,I4=1 is applied to primary inputs; in other words I1 changes from 1 to 0. Change in I1 is the first event. Outputs of gates, whose inputs are dependent on events which have changed, become active and are placed in an activity list; I1 drives gate G1 and OG1 becomes a part of activity list. In the >> step (time instant) each gate from the activity list is evaluated to determine whether its output changes; if output changes it becomes a triggering event and all gates driven by this output becomes a part of activity list. In this example, output of G1 changes (from 1 to 0) and this event adds O (output of G3) to activity list. On the other hand, if the output (of the gate under consideration) remains same then it does not correspond to triggering event and it does not generate any new gates for activity list. Here, output of G2 does not change and so it cannot add any gate to activity list. Once a gate from activity list is evaluated it is removed. The process of evaluation stops when the activity list becomes empty. In this example, in step 3, O changes from 1 to 0 and this makes the activity list empty. So, in event driven simulation we performed only three evaluations which are the number of signal changes in the circuit. An event-driven simulator only does the necessary amount of work. For logic circuits, in which typically very few signals change at a time, this can result in significant savings of computing effort.Figure 5. Example of event driven simulation3.Algorithms for Fault SimulationA fault simulator is like an ordinary simulator, but needs to simulate two versions of a circuit (i) without any fault for a given input pattern and (ii) with a fault inserted in the circuit and for the same input pattern. If the outputs under normal and faulty situation differ, the pattern detects the fault. Step (ii) is repeated for all faults. Once a fault is detected it is dropped and is not considered further during fault simulation by >> random pattern. The basic idea is illustrated in Figure 6.

The procedure is simple, but is too complex in terms of time required. Broadly speaking, time required is.Now we discuss algorithms which attempt to reduce this time. Basically such algorithms are based on two factors1. Determine more than one fault that is detected by a random pattern during one simulation run2. Minimal computations when the input pattern changes; the motivation is similar to event driven simulation over complied code simulation.3. 3.1 Serial Fault Simulation4. This is the simplest fault simulation algorithm. The circuit is first simulated (using event driven simulator) without any fault for a random pattern and primary output values are saved in a file. >>, faults are introduced one by one in the circuit and are simulated for the same input pattern. This is done by modifying the circuit description for a target fault and then using event driven simulator. As the simulation proceeds, the output values (at different primary outputs) of the faulty circuit are dynamically compared with the saved true responses. The simulation of a faulty circuit halts when output value at any primary output differs for the corresponding normal circuit response. All faults detected are dropped and the procedure repeats for a new random pattern. This procedure is illustrated in Figure 7. The circuit has two inputs and two primary outputs. For the random input pattern I1=1, I2=1 the output is O1=0, O2=1 under normal condition. Now let us consider a s-a-0 fault in I2. Event driven simulation (with scheduled events and activity list) for the circuit for input pattern I1=1, I2=1 and s-a-0 fault at I2 is shown in Table 3. It may be noted that that event driven simulation for this circuit requires 4 steps (t=0 to t=3). However, at step t=2, we may note that value of O2 is determined as 0, but under normal condition of the circuit O2 is 1. So, the s-a-0 fault in I2 can be detected by input pattern I1=1, I2=1 when O2 is 0. In other words, for input pattern I1=1, I2=1 the s-a-0 fault in I2 is manifested in primary output O2. As the fault is manifested in at least one primary output line, we need not evaluate other outputs (for that input pattern and the fault). In this example, for s-a-0 fault at I2 (after t=3 step of simulation), input pattern I1=1, I2=1 gives O1=0, O2=0; so fault can be detected ONLY at O2. However, we need not do this computation----if only one primary output line differs for an input pattern under normal and fault condition that input pattern can test the fault.5. So, s-a-0 fault at I2 is dropped (i.e., determined to be tested by pattern I1=1, I2=1) after t=2 steps of the event driven simulation of the faulty circuit. To summarize, detection of stuck at faults in a circuit using event driven fault simulation may save computation time, as for many cases all the steps need not be carried out.6. Figure 7. Illustration serial fault simulation7. Table 3. Event driven simulation for circuit of Figure 7 for input pattern I1=1, I2=1 and s-a-0 fault in I2TimeTimeScheduled Event

Activity List

t=0t=0I1=1, I2=1

I2(G1), OG1,I2(G2),O2

t=1I2(G1)=0,I2(G2)=0OG1, OG2,O2

t=2OG1=0,O2=0,OG2=1O1

t=3Not Required as O2=0 in faulty situation while O2=1 in normal condition

8. Now we discuss the cases for the other faults shown in Figure 7.Event driven simulation for the circuit (of Figure 7) for input pattern I1=1, I2=1 and fault s-a-1 in OG2 is shown in Table 4. It may be noted that the fault s-a-1 in OG2 is detected by input pattern I1=1, I2=1 at output O1; in case of fault O1=1, were as in case of normal circuit O1=0. Also, all four steps of the event driven simulation are required to detect the fault. So, detecting s-a faults using event driven fault simulation may not always save computation time, as in the worst case all the steps may be needed.Table 4. Event driven simulation for circuit of Figure 7 for input pattern I1=1, I2=1 and s-a-1fault in OG2TimeTimeScheduled Event

Activity List

t=0t=0I1=1, I2=1

I2(G1), OG1,I2(G2),O2

t=1I2(G1)=0,I2(G2)=0OG1, OG2,O2

t=2OG1=0,O2=0,OG2=1O1

t=3O1=1

Event driven simulation for the circuit (of Figure 7) for input pattern I1=1, I2=1 and fault s-a-0 in I2(G1) is shown in Table 5. Like s-a-0 fault in I2, s-a-0 fault in I2(G1) is detected by I1=1, I2=1 at O2 and the fault simulator requires up to t=2 steps.Table 5. Event driven simulation for circuit of Figure 7 for input pattern I1=1, I2=1 and fault s-a-0 fault in I2(G1)TimeTimeScheduled Event

Activity List

t=0t=0I1=1, I2=1

I2(G1), OG1,I2(G2),O2

t=1I2(G1)=0,I2(G2)=0OG1, OG2,O2

t=2OG1=0,O2=0,OG2=1O1

t=3Not Required as O2=0 in faulty situation while O2=1 in normal condition

Serial fault simulation is simple, however as discussed earlier, fornfaults the computing time is O(). With fault-dropping, this time can be significantly lower, especially if many faults are detected (and dropped) by random patterns used earlier. >> we will see advanced algorithms to reduce the complexity of fault simulation, mainly using two points Determine in one simulation, more than one fault if they can be detected by a given random pattern Use information generated during simulation of one random pattern for the >> set of patterns.Before we go for the advanced algorithms, a small question remains. When we are talking of event driven simulation, there is no question for nets being stuck at 0 or 1. So how can we use standard event driven simulator to simulate circuits having stuck at faults. Let us look at Table 3, t=1. We may note that I2(G1)=0, I2(G2)=0, because of the s-a-0 fault in I2; under normal condition I2(G1)=1, I2(G2)=1. It is very obvious to find how the values are obtained in faulty case. However, we need to see how we can use event driven simulator to simulate circuits with stuck at faults. It is to be noted that we cannot modify the simulator algorithm to handle faults; instead we will modify the circuit. Modifying the circuit for simulating stuck at faults is extremely simple. If a net I say, has a s-a-0 fault, we insert a 2-input AND gate with one input of the gate fixed to 0 and the other input of the gate is driven by I. The gate(s) previously driven by I is now driven by output of the AND gate added. Similarly, for s-a-1 fault a 2-input OR gate with one input of the gate fixed to 1 is added.Figure 8 illustrates insertion of the stuck at faults in the circuit shown in Figure 7. s-a-0 fault at I2 is inserted as follows. A 2-input AND gate with one input connected to 0 and the other to I2 is added. Now the newly added AND gate drives G1, which was earlier driven by I2.Similarly, a 2-input OR gate with one input connected to 1 and the other to OG2, inserts s-a-1 fault at OG2. Now the newly added OR gate drives G3, which was earlier driven by OG2.

Figure 8. Insertion of faults in the circuit of Figure 7 for fault simulation in event driven simulatorTo summarize, with simple modifications of the circuit, an event driven simulator can determine the output of a circuit with s-a-0 and s-a-1 faults. Henceforth, in our lectures we will not modify the circuits by inserting gates for fault simulation of stuck at faults; we will only mark the faults (as before by circles) and assume that the circuit is modified appropriately.3.2 Parallel Fault SimulationAs discussed in the last section, serial fault simulation processes one fault in one iteration. Parallel fault simulation, as the name suggests can processes more than one fault in one pass of the circuit simulation. Parallel fault simulation uses bit-parallelism of a computer. For example, in a 16-bit computer (where a word comprises 16 bits) a logical operation (AND, OR etc.) involving two words performs parallel operations on all respective pairs of 16-bits. This allows a parallel simulation of 16 circuits with same structure (gates and connectivity), but different signal values.In a parallel fault simulator, each net of the circuit is assigned a 1-dimensional array of widthw, wherewis the word size of the computer where simulation is being performed. Each bit of the array for a netIsay, corresponds to signal atIfor a condition (normal or fault at some point) in the circuit. Generally, the first bit is for normal condition and the other bits correspond tow 1stuck at faults at various locations of the circuit.In case of parallel simulation, input lines for any gate comprise binary words of lengthw(instead of single bits) and output is also a binary word of lengthw.The output word is determined by simple logical operation (corresponding to the gate) on the individual bits of the input words. Figure 9 explains this concept by example of an AND gate and an OR gate wherewis taken to be 3. In the example, in gate G1, input word at I1 is 110 and that in I2 is 010. Output word 010 is obtained by bit wise ANDing of the input words at I1 and I2; this is similar to simulating the gate for three input patterns at a time namely, (i) I1=1, I2=0 (ii) I1=1, I2=1 and (iii) I1=0, I2=0.

Figure 9. Example of parallel simulationNow we will discuss how parallel fault simulation can determine status ofw-1faults being covered or not given a random test pattern. Let us consider the same circuit used in Figure 7 for explanation of serial fault simulation. We consider the same three faults namely, (i) s-a-0 at I2, (ii) s-a-0 at I2(G1), (iii) s-a-1 at OG2 and the random pattern I1=1, I2=1. It will be shown how parallel fault simulation can discover coverage for these three faults for the input pattern I1=1, I2=1 in one iteration. As there are three faults we needw=4.Figure 10 illustrates parallel fault simulation for this example.

t may be noted that each net of the circuit has a 4 word array, where the first bit corresponds to normal condition of the circuit, the second for s-a-0 fault at I2(G1), the third bit for s-a-1 fault at OG2, the fourth for s-a-0 at I2.The first bit of the array at I1 is 1, implying that under normal condition I1=1 (i.e., input I1 is 1 by the random pattern). Similarly, input I2 is 1 by the random pattern. The second bit of the array for I1 is 1 because under the s-a-0 fault at I2(G1), I1 has value of 1; similarly the third and fourth bits of the array for I1 are 1. In a similar way, the second and third bits of the array at I2 are 1. However, the fourth bit of the array at I2 is 0, because under the s-a-0 fault at I2, net I2 has value of 0.The array at I2(G1) is a replica of the array at I2, but after changing the second bit to 0 as under s-a-0 fault at I2(G1), net I2(G1) has the value 0. The array at I2(G2) is a replica of the array at I2 as no fault is considered at I2(G2).So, to fill the values of the array in a fanout branch when the values at the stem are known, there are two steps1. Copy the values of array of the stem to the arrays of the branches2. If there is any s-a-0 (or s-a-1) fault is a branch, change the corresponding bit of the array to 0 (or 1).The array at OG1 is obtained by parallel logic AND operation on the words at the input lines I1 and I2(G1). The array at OG2 is obtained by parallel logic NOT operation on the word at the input line I2(G2) and making the third bit as 1 (as it corresponds to s-a-1 fault at OG2).So, to fill the values of the array in the output of a gate when the values at the input are known, there are two steps1. Obtain the values of array by parallel logic operation on the bits of the input words.2. If there is s-a-0 (or s-a-1) fault at the output of the gate, change the corresponding bit of the array to 0 (or 1).In a similar way the whole example can be explained.The array at O1 is 0010. It implies that on the input I1=1 and I2=1 O1 is 0 under normal condition O1 is 0 under s-a-0 fault at I2(G1), O1 is 1 under s-a-1 fault at OG2, O1 is 0 under s-a-0 at I2.It can be seen that only s-a-1 fault at OG2 causes a measurable difference at primary output O1 under normal and faulty condition for input pattern I1=1,I2=1. So pattern I1=1,I2=1 can detect only s-a-1 fault at OG2 (at output O1) but cannot detect s-a-0 fault at I2(G1) and s-a-0 fault at I2.The array at O2 is 1010. It implies that on the input I1=1 and I2=1 O2 is 1 under normal condition O2 is 0 under s-a-0 fault at I2(G1), O2 is 1 under s-a-1 fault at OG2, O2 is 0 under s-a-0 fault at I2.It can be seen that s-a-0 fault at I2(G1) and s-a-0 fault at I2 cause a measurable difference at primary output O2 under normal and faulty condition for input pattern I1=1,I2=1. So pattern I1=1,I2=1 at output O2 can detect s-a-0 fault at I2(G1) and s-a-0 fault at I2 but cannot detect s-a-1 fault at OG2. However, I1=1,I2=1 at output O1 detects s-a-1 fault at OG2. So all the three faults are detected by I1=1,I2=1.Thus, under once scan of the circuit, information about three faults for a random pattern is discovered. It may be noted from Figure 7, that three scans of the circuit were required to find the same fact. So parallel fault simulation, speeds us the serial fault simulation scheme byw-1times.After an iteration of parallel fault simulation, >> set ofw-1faults are considered and the procedure repeated. After all the faults are considered (i.e.,total number of faults/(w-1)iterations) the ones detected by the random pattern are dropped. >> another random pattern is taken and a new set of iterations are started.

So parallel fault simulation speeds up serial fault simulationw-1times, but for a random pattern more than one iterations are required. In the >> section we will see a scheme where in one iteration, information about ALL faults for a random pattern can be generated.3.3 Deductive Fault SimulationForm the discussion in the last section it can be noted that parallel fault simulation can speed up the procedure only by a factor that is dependent on the bit width of the computer being used. In this section we will discuss about deductive fault simulation, a procedure which can determine in a single iteration, detectability/undetectability about all faults by a given random pattern. In the deductive method, first the fault-free circuit is simulated by a random pattern and all the nets are assigned the corresponding signal values. Deductive, as the name suggests, all faults detectable at the nets are determined using the structure of the circuit and the signal values of the nets. Since the circuit structure remains the same for all faulty circuits, all deductions are carried out simultaneously. Thus, a deductive fault simulator processes all faults in a single pass of simulation augmented with the deductive procedures. Once detectability of all the faults for a random pattern is done, the same procedure is repeated for the >> random pattern after eliminating the covered faults.We will explain the procedure by a simple example circuit given in Figure 11.

Figure 11. Example of deductive fault simulation with input I1=0

.....>> we will see the fault deductions at the various nets if I1=1. This situation is illustrated in Figure 12.

Figure 12. Example of deductive fault simulation with input I1=1

o, now the question remains, what are the rules for fault deduction at a 2-input AND gate with one input as 1 and the other 0. The rules are explained using another example in Figure 13.

Figure 13. Example of deductive fault simulation with input I1=0 (Inputs of the AND gate are 1 and 0)