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Transcript of VLSIRESEARCH.comVLSIRESEARCH.com WeSRCH.com CHIPHISTORY.org CHIPHISTORY.org Copyright © 2008 VLSI...
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Copyright © 2008 VLSI Research Inc. All rights reserved. Reprinted with permission from VLSI RESEARCH INC.1
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Shifting Winds of Power
Chief Mountain, Height: 9080ft - 2767m, Waterton-Glacier International Peace Park, Montana
VLSI RESEARCH INCWhere the Chip Making Industry Clicks to Find its Weather
ISS 2008
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50 Years Since The Invention of the IC
• Introduction of the Planar Process and Si wafers.
• Emergence of new companies to exploit the technology.
• Foundation for today’s semiconductor manufacturing.
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History of Wafer Sizes
Wafer Demand(worldwide demand, by wafer size in M wafers/year)
0.0
10.0
20.0
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1960 1963 1966 1969 1972 1975 1978 1981 1984 1987 1990 1993 1996 1999 2002 2005
Mil
lio
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of
Waf
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.75"
1.25"
1.5"
2.0"
3.0"
4.0"
5.0"
6.0"
8.0"
12.0"
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20 Years Since the Introduction of P5000
• First successful multi-process tool.
• Combined the productivity and precision.
• Made Applied the giant it is today.
• Power and process shifted to equipment suppliers.
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Capital Productivity History
Wafer Fab Cost Trends
0.00
0.50
1.00
1.50
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4.00
1965
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Year
Dep
reci
atio
n C
ost
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Sq
uar
e In
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of
Cap
acit
y in
$
P5000 Intro (1987)
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Lessons from History
• Capital cost drives changes in the supply chain.– Cost escalation created Fabless/Foundry
supply.
• Design drives shifts in supply chain.– EDA drove designer efficiency.– Higher efficiency more complex designs.
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New Pressure Fronts in Chip Making
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Average Design Cost per Transistor(across all IC's, not including mask sets)
$-
$0.10
$0.20
$0.30
$0.40
$0.50
$0.60
1992 1994 1996 1998 2000 2002 2004 2006
Do
lla
rs
Copyright © 2007 by VLSI Research Inc. All rights reserved.
Design Cost reductions averaged 19% per year between 1992 and 2000.
This slowed to 5% between 2001 and 2006.
Factors: - Microchip to Nanochip transition. - Failure to foresee need for DFM. - Lack of investment.
Design Cost is No Longer Scaling
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Design Expenditures are Increasing, while New Designs are Declining
Design Activity
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1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007E
# o
f d
esig
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ign
exp
end
itu
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$M)
New Design Completions
Design Expenditure
Design expenditure:- '96 - '01 CAGR 9.5%- '02 - '07 CAGR 12.4%
RESTRICTED DATA: for access and use only w ithin your company. Copyright © 2007 by VLSI RESEARCH INC. All rights reserved.
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As New Designs Decline, so do revenues and ASPs
Average IC Revenues Per Active Design
0
1
2
3
1992 1994 1996 1998 2000 2002 2004 2006
Revenues/Design in $M IC ASP in $
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Specific Challenges for Foundry/Fabless Model
• The economics are stacking against small run designs.– Very expensive to design at 90nm & below.– Foundries are backing away from aggressive
scaling. Slower revenue growth.
• R&D costs escalating rapidly, yet foundries are lacking.
• Sub 100nm Yield Challenges at Foundries.
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Chip Maker Specialization is Increasing
Chip Manufacturing Specialization(Top 25 chipmakers)
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
1996 2006
Specialist
Generalist
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Wall Street Pressures for a Fab-Lite Strategy
• Better financial ratios (ROIC, ROA etc…).
• But where to get leading edge devices?– Nokia moving away from TI.– Opportunity for capable IDMs (IBM alliance or
Intel).
• Even Foundries are moving to fab-lite.– China Strategy.– 200mm expansion.
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Efficient Use of Capital is Critical
Sales Growth vs. Capex
Intel
Samsung
Texas Instruments
Toshiba
Infineon
STMicroelectronics
Hynix
TSMC
IBM Alliance
TSMC (Full Mkt)
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5%
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15%
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25%
30%
35%
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50%
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Sales Growth(2004 - 2007 CAGR)
20
07
Ca
pe
x t
o S
ale
s R
ati
o
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… And Taiwanese DRAM Suppliers Are Not Efficient
Sales Growth vs. Capex
Intel
Samsung
Texas Instruments
ToshibaInfineon
STMicroelectronics
Hynix
TSMC
IBM Alliance
TSMC (Full Mkt)
Taiwanese DRAM Suppliers
0%
10%
20%
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Sales Growth(2004 - 2007 CAGR)
20
07
Ca
pe
x t
o S
ale
s R
ati
o
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Winners Still Focus On Scaling
Silicon Demand(kw pw , 300 mm eq vs. nano manufacturing share of total)
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KW
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60%
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80%
Wafer Starts
Nano Manufacturing Share
RESTRICTED DATA: for access and use only w ithin your company. Copyright © 2007 by VLSI RESEARCH INC. All rights reserved.
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Scaling is Difficult -- But
• It is still the best cost lever.
• Need for higher integration is greater than ever.
• Successful scaling creates opportunities.– Intel is moving to traditional fabless markets.
• Scaling creates barriers.– Foundries have fallen off Moore’s Law.– GPUs going IDM.
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Summary
• Fabless/Foundry is at limits.
• Limit scaling limited financial returns.
• Nimble Logic IDMs can take advantage of weaker Fabless suppliers.
• Capex & R&D efficiency will be critical to pick winners.
• All Capex is not Equal.
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Information is Going to Make the Winners
• Content and Context is important.– Right information, right format, right place.
• How you can align your operations with markets?– DRAM over investment was a result of poor
information.– Dinner with customer CEO does not yield best
information.
• Collaboration/Networking is critical for R&D.
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Market Level Information
• Conferences play critical role.– ISS gives excellent sense where industry is heading.– What is hot and not.
• Market Research – Independent Voice.– Taiwanese would have easily prevented a DRAM glut by
spending ~$2M in market research.– Would have saved them $4B.
• Publications/News.– What is going on day to day.– 90% of Market Intelligence is Public Information.
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Collaboration/Networking
• You can not succeed in today’s economy without extensive network.– It is critical for your business and personal
success.– You have to give in order to receive.
• New platforms allow you to promote and advance your capabilities.
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Those Who Don’t . . .
Get Outsourced
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VLSI RESEARCH INCWhere the Chip Making Industry Clicks to Find its Weather
For a copy of this presentation go to www.WeSRCH.com and click on
WeQUEST on the left of the link bar