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1 Basic MOSFET Structure

In the introduction to a system, we got an overview of various levels of design, viz. Architectural leveldesign, Program level design, Functional level design and Logic level design. However we can't understandthe levels of design unless we are exposed to the basics of operation of the devices currently used to realize

the logic circuits, viz., MOSFET(Metal Oxide Semiconductor Field Effect Transistor). So in thissection, we'll study the basic structure of MOSFET.

The cross-sectional and top/bottom view of MOSFET are as in figures 11 and 12 given below :

Fig 11:Cross-sectional view of MOSFET Fig 12: Top/Bottom View of MOSFET

An n-type MOSFET consists of a source and a drain, two highly conducting n-type semiconductorregions which are separated from the p-type substrate by reverse-biased p-n diodes. A metal or polycrystalline gate covers the region between the source and drain, but is isolated from the semiconductor by

the gate oxide.

2 Types o f MOSFET

MOSFETs are divided into two types viz. p-MOSFETand n-MOSFETdepending upon its type ofsource and drain.

Fig. 21: p-MOSFET Fig. 22: n-MOSFET Fig. 23: c-MOSFET

The combination of a n-MOSFETand a p-MOSFET(as shown in figure 21) is called cMOSFETwhich is the mostly used as MOSFET transistor. We will look at it in more detail later.

3 MOSFET I-V Modell ing

We are interested in finding the output characteristics ( ) and the transfer charcteristics (MOSFET. In other words, we can find out both if we can formulate a mathematical equation of the form :

Intutively, we can say that voltage level specifications and the material parameters cannot be altered by designers. So th

in the designer's hands with which he/she can improve the performance of the device are itsdimensions, W andL (sview of MOSFET fig 2). In fact, the most important parameter in the device simulations is ratio of W and L.

The equations governing the output andtransfer characteristics of an n-MOSFET and p-MOSFET are :

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p-MOSFET:

Linear

Saturation

n-MOSFET:

Linear

Saturation

The outputcharacteristics plotted for few fixed values of for p-MOSFET and n-MOSFET are shown next :

Fig 31: p-MOSFET Fig 32: n-MOSFET

The transfercharacteristics of both p-MOSFET and n-MOSFET are plotted for a fixed value of as shown next :

Fig 33: p-MOSFET Fig 34: n- MOSFET

Note: From now onwards in the lectures, we will symbolize MOSFET by MOS.

4 C-V Characteristi cs o f a MOS Capacitor

As we have seen earlier, there is an oxide layerbelow Gateterminal. Since oxide is a very good insulator, it contributeoxide capacitance in the circuit. Normally, the capacitance value of a capacitor doesn't change with values of voltage aacross its terminals. However, this is not the case with MOS capacitor. We find that the capacitance of MOS capacitor chits value with the variation in Gate voltage. This is because application of gate voltage results in the band bending of

substrate and hence variation in charge concentration at Si-SiO2interface. Also we can see (from fig.42 ) that the splits into two (reason will be explained later), after a certain voltage, depending upon the frequency (high or low) of AC v

applied at the gate. This voltage is called the threshold voltage(Vth) of MOS capacitor.




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Fig 41: Cross-section view of MOSCapacitor Fig 42: plot of MOS Capacitor




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9.1 MotivationIn the previous module, we did a detailed study about the MOSFET. VLSI circuits are very complex circuits i.e we cannocircuits by interconnecting few single MOSFET transistors. A VLSI circuit consists of millions to billions of transistors. F

purpose, we usePhotolithographywhich is a method/technology to create the circuit patterns on a silicon wafer surfa

the process is calledFabrication.In this lecture, we will study in detail photolithography, how it is done and what sort of materials are used for this purpose.

9.2 PhotolithographyPhotolithography is the method that sets the surface dimensions (horizontal) of various parts of devices and circuits. Its is two fold. First goal is to create in and on the wafer surface a pattern whose dimensions are as close to the de

requirements as possible. This is known asresolution of images on the wafer and the pattern dimensions are know

eature or image sizesof the circuit. Second goal is the correct placement called alignment or registration of the cipatterns on the wafer. The entire circuit patterns must be correctly placed on the wafer surface because misaligned mlayers can cause the entire circuit to fail.

Figure 9.1: Clear

Field mask

In order to create patterns on the wafer, the required pattern is first formed in the reticlephotomasks. The pattern on reticle or mask is then transfered into a layer of photoresist. Photoreis a light sensitive material similar to the coating on a regular photographic film. Exposure to lcauses changes in its structure and properties. If the exposure to light causes photoresischange from a soluble to insoluble one, it is known as negative actingand the chemical changcalled

polymerization.Similarly, if exposure to light causes it change from relatively non-sol

to much more soluble, it is known as positive acting and the term describing it is called

hotosolubilisation. The exposure radiation is generally UV andE-beam. Removing the sol

portions with chemical solvents calleddevelopers leaves a pattern on the photoresist depen

upon the type of mask used. A mask whose pattern exists in the opaque regions is called cl

ield mask. The pattern could also be coded in reverse, and such masks are known asd

ield masks.The result obtained from the photomasking process from different combinations of mask and repolarities is shown in the following table:

Figure 9.2: Dark

Field mask

The second transfer takes place from the photoresist layer into the wafer surface layer. The transfer occurs when etcharemove the portion of the wafer's top layer that is not covered by the photoresist. The chemistry of the photoresists is sthat they do not dissolve in the chemical etching solutions; they are etch resistant; hence the name photoresists.The etc

generally used to remove silicon dioxide is hydrogen fluoride (HF).




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The choice of mask and resist polarity is a function of the level of dimensional control and defect protection required to mthe circuit work. For example, sharp lines are not obtainable with negative photoresists while etchants are difficult to hawith positive photoresists.

After the pattern has been taken on resist, the thin layer needs to be etched. Etching process is used to etch into a spelayer the circuit pattern that has been defined during the photomasking process. For example, aluminium connectionsobtained after etching of the aluminium layer.

9.3 Fabrication Process

Why polysilicon gate?

The most significant aspect of using polysilicon as the gate electrode is its ability to be used as a further mask to allow definition of source and drain regions. This is achieved with minimum gate to source/drain overlap, which leads to lower capacitances and improved circuit performance.

Procedure:




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A thick layer of oxide is grown on the wafer surface which is known as field oxide (FOX). It is much thicker than toxide. It acts as shield which protects the underlying substrate from impurities when other processes are being carried ouwafer. Besides, it also aids in preventing conduction between unrelated transistor source/drains. In fact, the thick FOX cana gate oxide for a parasitic MOS transistor. The threshold voltage of this transistor is much higher than that of a regular tr

due to thick field oxide. The high threshold voltage is further ensured by introducing channel-stopdiffusion underneath oxide, which raises the impurity concentration in the substrate in the areas where transistors are not required.

A window is opened in the field oxide corresponding to the area where the transistor is to be made. A thin highly controlle

of oxide is deposited where active transistors are desired. This is called gate oxideor thinox.A thick layer of silicon direquired elsewhere to isolate the individual transistors.

The thin gate oxide is etched to open windows for the source and drain diffusions. Ion implantation or diffusion is useddoping. The former tends to produce shallower junctions which are compatible with fine dimension processes. As the dprocess occurs in all directions, the deeper a diffusion is the more it spreads laterally. This lateral spread determines the between gate and source/drain regions.

Next, a gate delineation mask is used to determine the gate area. There has to be minimum overlap between ga

source/drain regions. This is referred to as self-aligned process because source and drain do not extend under thPolysilicon is then deposited over the oxide.

The complete structure is then covered with silicon dioxide and contact holes are etched using contact window mask dowsurface to be contacted. These allow metal to contact diffusion or polysilicon regions.

Metallization is then applied to the surface using interconnect mask and selectively etched to produce circuit interconnecti

As a final step, the wafer is passivated and openings to the bond pads are etched to allow for wire bonding. Passivation pthe silicon surface against the ingress of contaminants than can modify circuit behavior.




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10.1 Gate MaterialMetals have several advantages when considered as gate electrodes. The use of metal gates would certainly eliminproblems of dopant penetration through the dielectric and subsequent gate depletion. The use of metals with appropriafunctions for NMOS and PMOS devices would led to transistors with symetrical and tailored threshold voltages. Most refmetals are good choices for this application primarily due to their high melting points, which allow them to be used temperatures necessary for source-drain implant activation. However thermodynamic stability of metal-dielectric interfprocessing temperatures are major concerns which need to be addressed in addition to more subtle issues of el

properties, flat band voltage (ultimately threshold voltages) stability and the charge trapping at the interface. The probleusing aluminium is that once deposited, it cannot be subjected to high temperature processes. Copper causes a lotgeneration when used as a gate material.

10.2 Parasitic Capacitances

Though a lot of parasitic capacitances exist in a MOSshown in figure 10.2, but those of prime concern to us are t

to drain capacitance (Cgd) and gate to source capacitancebecause they are common to input and output nodes anmultiplied by gain during circuit operation. Thus they increinput capacitance drastically and decrease the charging rat

Figure 10.2: Parasitic capacitances in MOSFET

10.3 Self-aligned Silicon Gate Technology

When the metal is used as the gate material, then the source and drain are deposited before the gate and thus to align the

gate, mask alignused and erroaligning takes plcase of polysilicoprocess, the egate oxide(not cby polysilicon) is away and the wsubjected to source or ion-which causes

drain deposition athese are formedregions not covepolysilicon andsource and drainextend under thThis is calledaligning process.

Figure 10.3: Cross sectional view of MOSFET under Self-algining process

10.4 Channel Stopper

It is used to prevent the channel formation in the subtrate below the field oxide. For example, for a p-substrate, the cstopper implant would p+ which will increase the magnitude of threshold voltage.Irregular surfaces can cause "step coverage problems" in which a conductor thins and can even break as it crosses a thic

oxide boundary. One of the methods used to remove these irregularities is to pre-etch the silicon in areas where the field to be grown by arround half the final required field oxide thickness. LOCOS (will explain it shortly) oxidation done after thithe planner field oxide/gate oxide interface.

10.5 Polysilicon Deposition

The sheet resistance of undoped polysilicon is 10^8 ohms/cm and it can be reduced to 30 ohm/cm by heavy dopinadvantage of using polysilicon as gate material is its use as further mask to allow precise definition of source and drapolysilicon resistance affects the input resistance of the transistor and thus should be small for improving the RC time coFor this, higher doping concentration is used.




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10.6 Oxide Growth

Oxide gro+wn on silicon may result in an uneven surface due to unequal thickness of oxide grown from same thickness of

silicon. Stress along the edge of an oarea (where silicon has been trenched oxidation to produce a plainer surfacproduce severe damage in the silicrelieve this stress, the oxidation temp

must be sufficiently high to allow the sthe oxide to relieved by viscous flow.LOCOS process, the transistor area is mby SiO2/SiN sandwich and the thick fielis then grown. The oxide grows in bdirections vertically and also laterallythe sandwich and results in an encroainto the gate region called as bird's bea

Figure 10.6: Formation of bird 's beak in MOSFET

This reduces the active area of the transistor and specially the width. Some improvements in the LOCOS process produccrest which reduces the encroachments, but it is non-uniform.

The goal is to oxidize Si only locally, whenevera field oxide is needed. This is necessary forthe following reasons:

-- Local oxide penetrates into the Si, so the Si-SiO2 interface is lower than the source-drainregions to be made later. This could not beachieved with oxidizing all of the Siand thenetching of unwanted oxide.

-- For device performance reasons, this ishighly beneficial, if not absolutely necessary.

10.7 Active Mask or Isolation Mask(thin-ox)

It describes the areas where thin oxides areneeded to implement the transistor gates andallow implantations to form p/n type diffusions.

A thin layer of SiO2is grown and covered withSiNand this is used as mask. The bird's beadmust be taken into account while designingthin-ox.

Figure 10.62: Comparison of the LOCOS process withand without some sacrificial polysilicon




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11. Why polysilicon prefered over aluminium as gate material?

Because-

1) Penetration of silicon substrate: If aluminium metal is deposited as gate, we can't increase the temperature beyond 500 degreecelcius due to the fact that aluminium will then start penetrating the silicon substrate and act as p-type impurity.

2) Problem with non-self alignment: In case of aluminiumgate, we have to first create source and drain and then

gate implant. We can't do the reverse because diffusion isa high temperature process. And this creates parasitioverlap input capacitances Cgdand Cgs(figure 11.11).Cgdis more harmful because it is a feedback capacitance and

hence it is reflected on the input magnified by (k+1) time(recall Miller's theorem), where k is the gain. So aluminum is used, the input capacitance increasesunnecessarily which further increases the charging time othe input capacitance. Therefore output doesn't appeaimmediately.

Figure 11.11: Self-alignment is not possible in case of Al gate due to Cgd

and Cgs

If poly-silicon is used instead, it is possible to first create

gate and then source & drain implant, which eliminates theproblem of overlap capacitances Cgdand Cgs.

Resistivity of poly-silicon is 10^8 ohm/cm. So we need todope poly-silicon so that it resembles a metal likeAl and itresistance is reduced to 100 or 300 ohm (although its stilgreater thanAl).

Figure 11.12 Self-alignment possible in case of poly-silicon

Time for charging capacitance varies as negative exponential of (RC)^(-1)whereR and C are resistance and capacitance of thedevice. As we know the resistance is directly propotional to the length, so poly-silicon length should be kept small so that theresistance is not large, otherwise the whole purpose of decreasing C(hence the time constantRC) will be nullified.

11.2 Channel stopper Implant

As we know millions of transistors are fabricated on a single chip. To seperate (insulate) these from each-other, we grow oxides (called field oxides). So, at very high voltages, inversion may set in the region below the field oxide also, despite the lthickness of these oxides.

To avoid problem, we dimplant in region begrowing the oxide layer sothreshold vofor this regiomuch greater that for the deactive transchannel re

This implant is calledchan

stopper

implant. shown in f

11.21)

Figure 11.21: channel stopper implant before field oxide region is grown (yellow color

region)




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11.3 Local Oxidation o f Silicon (LOCOS)

During etching, anything irregular becomes more irregular. So wegrow oxide fields 50% above and 50% below the wafer. This iscalled LOCal Oxidation of Silicon(LOCOS).

Figure 11.31: Formation of LOCOS

Creation o f LOCOS:

0.45 mU of silicon, when oxidized, becomes 1 mU of SiO2because of changein density. When field oxides are grown, there is an encroachment of theoxide layer in the active transistor region below the gate oxide, because of theaffinity of the SiO2gate oxide for oxygen. The resulting structure resembles abird's beak (as shown in figure 11.32) . This affects the device performance.

Figure 11.32: bird 's beak

If we use Si3N4 as the gate dielectric, it will not let oxygen pass through. Butdue to mismatch of the thermal coefficients of Si and Si3N4, hence theresulting stress produces a non-planar structure called bird's crest(as shownin figure 11.33) .

Figure 11.33: bird 's creast

The thermal coefficients ofSi and SiO2match. So when Si3N4 is used as the gate dielectric, we first grow a thin oxide layerunderneath. The stress, which would otherwise be generated on the account of the difference in the thermal coefficients of Siand SiO2is now reduced. Since SiO2 is now there, bird's beak will be formed.

12.1 Introduction

CMOS fabrication can be accomplished using either of the three technologies:

N-well/P-well technologies

Twin well technology

Silicon On Insulator (SOI)

In this discussion we will focus chiefly on N-well CMOS fabrication technology.

12.2 Twin Well TechnologyUsing twin well technology, we can optimise NMOS and PMOS transistors separately. This means that transistor parameterssuch as threshold voltage, body effect and the channel transconductance of both types of transistors can be tunedindependenly.

n+ or p+ substrate, with a lightly doped epitaxial layer on top, forms the starting material for this technology. The n-well and p-well are formed on this epitaxial layer which forms the actual substrate. The dopant concentrations can be carefully optimizedto produce the desired device characterisitcs because two independent doping steps are performed to create the well regions.

The conventional n-well CMOS process suffers from, among other effects, the problem of unbalanced drain parasitics sincethe doping density of the well region typically being about one order of magnitude higher than the substrate. This problem isabsent in the twin-tub process.




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12.3 Silicon on Insulator (SOI)To improve process characteristics such as speed and latch-up susceptibility, technologists have sought to use an insulasubstrate instead of silicon as the substrate material.

Completely isolated NMOS and PMOS transistors can be created virtually side by side on an insulating substrate (eg. sapphirusing the SOI CMOS technology.

This technology offers advantages in the form of higher integration density (because of the absence of well regions), compavoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional n-well or twin-tub CMprocesses.

But this technology comes with the disadvantage of higher cost than the standard n-well CMOS process. Yet the improvemendevice performance and the absence of latch-up problems can justify its use, especially in deep submicron devices.

12.4 N-well TechnologyIn this discussion we will concentrate on the well established n-well CMOS fabrication technology, which requires that bochannel and p-channel transistors be built on the same chip substrate. To accomodate this, special regions are created wsemiconductor type opposite to the substrate type. The regions thus formed are called wells or tubs. In an n-type substratecan create a p-well or alternatively, an n-well is created in a p-type substrate. We present here a simple n-well CMOS fabricatechnology, in which the NMOS transistor is created in the p-type substrate, and the PMOS in the n-well, which is built-in into

p-type substrate.

Historically, fabrication started with p-well technology but now it has been completely shifted to n-well technology. The main reafor this is that, "n-well sheet resistance can be made lower than p-well sheet resistance" (electrons are more mobile than holes

The simplified process sequence (shown in Figure 12.41) for the fabrication of CMOS integrated circuits on a p-type sisubstrate is as follows:

N-well regions are created for PMOS transistors, by impurity implantation into the substrate

This is followed by the growth of a thick oxide in the regions surround the NMOS and PMOS active regions.

The thin gate oxide is subsequently grown on the surface through thermal oxidation.

After this n+ and p+ regions (source, drain and channel-stop implants) are created.

The metallization step (creation of metal interconnects) forms the final step in this process




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Fig 12.41: Simplified Process Sequence For Fabrication Of CMOS ICs

The integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxsince each processing step requires that certain areas are defined on chip by appropriate masks. A layer is patterned beforenext layer of material is applied on the chip. A process, called lithography, is used to transfer a pattern to a layer. This musrepeated for every layer, using a different mask, since each layer has its own distinct requirements.

12.4 N-well Technology (contd.)We illustrate the fabrication steps involved in patterning silicon dioxide through optical lithography, using Figure 12.42 whshows the lithographic sequences.




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Fig 12.42: Process steps required for patterning of silicon dioxide

12.4 N-well Technology (contd.)




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but their photolithographic resolution is not as high as that of the positive photoresists. Hence, the use of negative photoresisless common in manufacturing high-density integrated circuits.

The unexposed portions of the photoresist can be removed by a solvent after the UV exposure step. The silicon dioxide regnot covered by the hardened photoresist is etched away by using a chemical solvent (HF acid) or dry etch (plasma etch) procOn completion of this step, we are left with an oxide window which reaches down to the silicon surface. Another solvent is usestrip away the remaining photoresist from the silicon dioxide surface. The patterned silicon dioxide feature is shown in Fi

12.43

Fig 12.43: The result of single photolithographic patterning sequence on silicon dioxide

The sequence of process steps illustrated in detail actually accomplishes a single pattern transfer onto the silicon dioxide surfThe fabrication of semiconductor devices requires several such pattern transfers to be performed on silicon dioxide, polysiliand metal. The basic patterning process used in all fabrication steps, however, is quite similar to the one described earlier. note that for accurate generation of high-density patterns required in submicron devices, electron beam (E-beam) lithographused instead of optical lithography.

12.4 N-well Technology (contd.)In this section, we will examine the main processing steps involved in fabrication of an n-channel MOS transistor on a p-

silicon substrate.

The first step of the process is the oxidation of the silicon substrate (Fig 12.44(a)), which creates a relatively thick silicon diolayer on the surface. This oxide layer is called field oxide (Fig. 12.44(b)). The field oxide is then selectively etched to exposesilicon surface on which the transistor will be created (Fig. 12.44(c)). After this the surface is covered with a thin, high-quality olayer. This oxide layer will form the gate oxide of the MOS transistor (Fig. 12.44(d)). Then a polysilicon layer is deposited onthin oxide (Fig 12.44(e)). Polysilicon is used as both a gate electrode material for MOS transistors as well as an interconmedium in silicon integrated circuits. The resistivity of polysilicon, which is usually high, is reduced by doping it with impatoms.




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Deposition is followed by patterning and etching of polysilicon layer to form the interconnects and the MOS transistor gates (12.44(f)). The thin gate oxide not masked by polysilicon is also etched away exposing the bare silicon surface. The drain source junctions are to be formed (Fig 12.44(g)). Diffusion or ion implantation is used to dope the entire silicon surface with a concentration of impurities (in this case donor atoms to produce n-type doping). Fig 12.44(h) shows two n-type regions (soand drain junctions) in the p-type substrate as doping penetrates the exposed areas of the silicon surface. The penetratio

impurity doping into the polysilicon reduces its resistivity. The polysilicon gate is patterned before the doping and it precidefines the location of the channel region and hence, the location of the source and drain regions. Hence this process is calleself-aligning process.

The entire surface is again covered with an insulating layer of silicon dioxide after the source and drain regions are completed12.44(i)). Next contact windows for the source and drain are patterned into the oxide layer (Fig. 12.44(j)). Interconnects are forby evaporating aluminium on the surface (Fig 12.44(k)), which is followed by patterning and etching of the metal layer 12.44(l)). A second or third layer of metallic interconnect can also be added after adding another oxide layer, cutting (via) hodepositing and patterning the metal.




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12.4 N-well Technology (contd.)CVD is again used to deposit and insulating silicon dioxide layer over the entire wafer. After this the contacts are defined anetched away exposing the silicon or polysilicon contact windows. These contact windows are essential to complete the circu

interconnections using the metal layer, which is patterned in the next step.

Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned througetching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very criticaand are ultimately essential for circuit reliability.

The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in nwell), the polysilicon and metal interconnections. The final step is to deposit the passivation layer (for protection) over the chipexcept for wire-bonding pad areas.

This completes the fabrication of the CMOS inverter using n-well technology.




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11. Why polysilicon prefered over aluminium as gate material?

Because-

1) Penetration of silicon substrate: If aluminium metal is deposited as gate, we can't increase the temperature beyond 500 degreecelcius due to the fact that aluminium will then start penetrating the silicon substrate and act as p-type impurity.

2) Problem with non-self alignment: In case of aluminiumgate, we have to first create source and drain and then

gate implant. We can't do the reverse because diffusion isa high temperature process. And this creates parasitioverlap input capacitances Cgdand Cgs(figure 11.11).Cgdis more harmful because it is a feedback capacitance and

hence it is reflected on the input magnified by (k+1) time(recall Miller's theorem), where k is the gain. So aluminum is used, the input capacitance increasesunnecessarily which further increases the charging time othe input capacitance. Therefore output doesn't appeaimmediately.

Figure 11.11: Self-alignment is not possible in case of Al gate due to Cgd

and Cgs

If poly-silicon is used instead, it is possible to first create

gate and then source & drain implant, which eliminates theproblem of overlap capacitances Cgdand Cgs.

Resistivity of poly-silicon is 10^8 ohm/cm. So we need todope poly-silicon so that it resembles a metal likeAl and itresistance is reduced to 100 or 300 ohm (although its stilgreater thanAl).

Figure 11.12 Self-alignment possible in case of poly-silicon

Time for charging capacitance varies as negative exponential of (RC)^(-1)whereR and C are resistance and capacitance of thedevice. As we know the resistance is directly propotional to the length, so poly-silicon length should be kept small so that theresistance is not large, otherwise the whole purpose of decreasing C(hence the time constantRC) will be nullified.

11.2 Channel stopper Implant

As we know millions of transistors are fabricated on a single chip. To seperate (insulate) these from each-other, we grow oxides (called field oxides). So, at very high voltages, inversion may set in the region below the field oxide also, despite the lthickness of these oxides.

To avoid problem, we dimplant in region begrowing the oxide layer sothreshold vofor this regiomuch greater that for the deactive transchannel re

This implant is calledchan

stopper

implant. shown in f

11.21)

Figure 11.21: channel stopper implant before field oxide region is grown (yellow color

region)




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11.3 Local Oxidation o f Silicon (LOCOS)

During etching, anything irregular becomes more irregular. So wegrow oxide fields 50% above and 50% below the wafer. This iscalled LOCal Oxidation of Silicon(LOCOS).

Figure 11.31: Formation of LOCOS

Creation o f LOCOS:

0.45 mU of silicon, when oxidized, becomes 1 mU of SiO2because of changein density. When field oxides are grown, there is an encroachment of theoxide layer in the active transistor region below the gate oxide, because of theaffinity of the SiO2gate oxide for oxygen. The resulting structure resembles abird's beak (as shown in figure 11.32) . This affects the device performance.

Figure 11.32: bird 's beak

If we use Si3N4 as the gate dielectric, it will not let oxygen pass through. Butdue to mismatch of the thermal coefficients of Si and Si3N4, hence theresulting stress produces a non-planar structure called bird's crest(as shownin figure 11.33) .

Figure 11.33: bird 's creast

The thermal coefficients ofSi and SiO2match. So when Si3N4 is used as the gate dielectric, we first grow a thin oxide layerunderneath. The stress, which would otherwise be generated on the account of the difference in the thermal coefficients of Siand SiO2is now reduced. Since SiO2 is now there, bird's beak will be formed.

12.1 Introduction

CMOS fabrication can be accomplished using either of the three technologies:

N-well/P-well technologies

Twin well technology

Silicon On Insulator (SOI)

In this discussion we will focus chiefly on N-well CMOS fabrication technology.

12.2 Twin Well TechnologyUsing twin well technology, we can optimise NMOS and PMOS transistors separately. This means that transistor parameterssuch as threshold voltage, body effect and the channel transconductance of both types of transistors can be tunedindependenly.

n+ or p+ substrate, with a lightly doped epitaxial layer on top, forms the starting material for this technology. The n-well and p-well are formed on this epitaxial layer which forms the actual substrate. The dopant concentrations can be carefully optimizedto produce the desired device characterisitcs because two independent doping steps are performed to create the well regions.

The conventional n-well CMOS process suffers from, among other effects, the problem of unbalanced drain parasitics sincethe doping density of the well region typically being about one order of magnitude higher than the substrate. This problem isabsent in the twin-tub process.




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12.3 Silicon on Insulator (SOI)To improve process characteristics such as speed and latch-up susceptibility, technologists have sought to use an insulasubstrate instead of silicon as the substrate material.

Completely isolated NMOS and PMOS transistors can be created virtually side by side on an insulating substrate (eg. sapphirusing the SOI CMOS technology.

This technology offers advantages in the form of higher integration density (because of the absence of well regions), compavoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional n-well or twin-tub CMprocesses.

But this technology comes with the disadvantage of higher cost than the standard n-well CMOS process. Yet the improvemendevice performance and the absence of latch-up problems can justify its use, especially in deep submicron devices.

12.4 N-well TechnologyIn this discussion we will concentrate on the well established n-well CMOS fabrication technology, which requires that bochannel and p-channel transistors be built on the same chip substrate. To accomodate this, special regions are created wsemiconductor type opposite to the substrate type. The regions thus formed are called wells or tubs. In an n-type substratecan create a p-well or alternatively, an n-well is created in a p-type substrate. We present here a simple n-well CMOS fabricatechnology, in which the NMOS transistor is created in the p-type substrate, and the PMOS in the n-well, which is built-in into

p-type substrate.

Historically, fabrication started with p-well technology but now it has been completely shifted to n-well technology. The main reafor this is that, "n-well sheet resistance can be made lower than p-well sheet resistance" (electrons are more mobile than holes

The simplified process sequence (shown in Figure 12.41) for the fabrication of CMOS integrated circuits on a p-type sisubstrate is as follows:

N-well regions are created for PMOS transistors, by impurity implantation into the substrate

This is followed by the growth of a thick oxide in the regions surround the NMOS and PMOS active regions.

The thin gate oxide is subsequently grown on the surface through thermal oxidation.

After this n+ and p+ regions (source, drain and channel-stop implants) are created.

The metallization step (creation of metal interconnects) forms the final step in this process




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Fig 12.41: Simplified Process Sequence For Fabrication Of CMOS ICs

The integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxsince each processing step requires that certain areas are defined on chip by appropriate masks. A layer is patterned beforenext layer of material is applied on the chip. A process, called lithography, is used to transfer a pattern to a layer. This musrepeated for every layer, using a different mask, since each layer has its own distinct requirements.

12.4 N-well Technology (contd.)We illustrate the fabrication steps involved in patterning silicon dioxide through optical lithography, using Figure 12.42 whshows the lithographic sequences.




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Fig 12.42: Process steps required for patterning of silicon dioxide

12.4 N-well Technology (contd.)




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but their photolithographic resolution is not as high as that of the positive photoresists. Hence, the use of negative photoresisless common in manufacturing high-density integrated circuits.

The unexposed portions of the photoresist can be removed by a solvent after the UV exposure step. The silicon dioxide regnot covered by the hardened photoresist is etched away by using a chemical solvent (HF acid) or dry etch (plasma etch) procOn completion of this step, we are left with an oxide window which reaches down to the silicon surface. Another solvent is usestrip away the remaining photoresist from the silicon dioxide surface. The patterned silicon dioxide feature is shown in Fi

12.43

Fig 12.43: The result of single photolithographic patterning sequence on silicon dioxide

The sequence of process steps illustrated in detail actually accomplishes a single pattern transfer onto the silicon dioxide surfThe fabrication of semiconductor devices requires several such pattern transfers to be performed on silicon dioxide, polysiliand metal. The basic patterning process used in all fabrication steps, however, is quite similar to the one described earlier. note that for accurate generation of high-density patterns required in submicron devices, electron beam (E-beam) lithographused instead of optical lithography.

12.4 N-well Technology (contd.)In this section, we will examine the main processing steps involved in fabrication of an n-channel MOS transistor on a p-

silicon substrate.

The first step of the process is the oxidation of the silicon substrate (Fig 12.44(a)), which creates a relatively thick silicon diolayer on the surface. This oxide layer is called field oxide (Fig. 12.44(b)). The field oxide is then selectively etched to exposesilicon surface on which the transistor will be created (Fig. 12.44(c)). After this the surface is covered with a thin, high-quality olayer. This oxide layer will form the gate oxide of the MOS transistor (Fig. 12.44(d)). Then a polysilicon layer is deposited onthin oxide (Fig 12.44(e)). Polysilicon is used as both a gate electrode material for MOS transistors as well as an interconmedium in silicon integrated circuits. The resistivity of polysilicon, which is usually high, is reduced by doping it with impatoms.




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Deposition is followed by patterning and etching of polysilicon layer to form the interconnects and the MOS transistor gates (12.44(f)). The thin gate oxide not masked by polysilicon is also etched away exposing the bare silicon surface. The drain source junctions are to be formed (Fig 12.44(g)). Diffusion or ion implantation is used to dope the entire silicon surface with a concentration of impurities (in this case donor atoms to produce n-type doping). Fig 12.44(h) shows two n-type regions (soand drain junctions) in the p-type substrate as doping penetrates the exposed areas of the silicon surface. The penetratio

impurity doping into the polysilicon reduces its resistivity. The polysilicon gate is patterned before the doping and it precidefines the location of the channel region and hence, the location of the source and drain regions. Hence this process is calleself-aligning process.

The entire surface is again covered with an insulating layer of silicon dioxide after the source and drain regions are completed12.44(i)). Next contact windows for the source and drain are patterned into the oxide layer (Fig. 12.44(j)). Interconnects are forby evaporating aluminium on the surface (Fig 12.44(k)), which is followed by patterning and etching of the metal layer 12.44(l)). A second or third layer of metallic interconnect can also be added after adding another oxide layer, cutting (via) hodepositing and patterning the metal.




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12.4 N-well Technology (contd.)CVD is again used to deposit and insulating silicon dioxide layer over the entire wafer. After this the contacts are defined anetched away exposing the silicon or polysilicon contact windows. These contact windows are essential to complete the circu

interconnections using the metal layer, which is patterned in the next step.

Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned througetching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very criticaand are ultimately essential for circuit reliability.

The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in nwell), the polysilicon and metal interconnections. The final step is to deposit the passivation layer (for protection) over the chipexcept for wire-bonding pad areas.

This completes the fabrication of the CMOS inverter using n-well technology.




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1.3 MOSFET I-V Modell ing

We are interested in finding theoutputcharacteristics ( ) and thetransfercharcteristics (MOSFET. In other words, we can find out both if we can formulate a mathematical equation of the form :

Intutively, we can say that voltage level specifications and the material parameters cannot be altered by designers. So th

tools in the designer's hands with which he/she can improve the performance of the device are itsdimensions, W(shown in top view of MOSFET). In fact, the most important parameter in the device simulations is ratio of W and L.

The equations governing the output andtransfer characteristics of an n-MOSFET and p-MOSFET are :

p-MOSFET:

Linear

Saturation

n-MOSFET:

Linear

Saturation

The outputcharacteristics plotted for few fixed values of for p-MOSFET and n-MOSFET are shown next :

Fig 1.31: p-MOSFET Fig 1.32: n-MOSFET

The transfercharacteristics of both p-MOSFET and n-MOSFET are plotted for a fixed value of as shown next :

Fig 1.33: p-MOSFET Fig 1.34: n- MOSFET

5.1 Threshold Voltage Calculation




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Threshold voltage is that gate voltage at which the surface band bending is twice ,Where

We know that the depth of depletion region for is between 0 and and is given by,

Chargein depletion region at is given by where

Beyond threshold, the total charge QD in the seminconductor has to balance the charge on gate electrode,

where we define the charge in the inversion layer as a quantity which needs to be determined.

This leads to following expression for gate voltage-

5.2 C-V Characteristi cs

The low frequency and high frequency C-V characteristics curves of a MOS capacitor are shown in fig 5.2.

Fig 5.2 : Low & High Frequency C-V curves

The low frequencyor quasi-static measurement maintains thermal equilibrium at all times. This capacitance is the ratio ofthe change in charge to the change in gate voltage, measured while the capacitor is in equilibrium. A typical measurement isperformed with an electrometer, which measures the charge added per unit time as one slowly varies the applied gate voltage.

The high frequency capacitance is obtained from a small-signal capacitance measurement at high frequency. The biasvoltage on the gate is varied slowly to obtain the capacitance versus voltage. Under such conditions, one finds that the charge inthe inversion layer does not change from the equilibrium value corresponding to the applied DC voltage. The high frequencycapacitance therefore reflects only the charge variation in the depletion layer and the (rather small) movement of the inversion

yer charge.la

5.3 Oxide Charge Correction




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To keep the value of within -1 Volt and +1 Volt, an n-channel device has high doping (similarly, p-channel device

doping).




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15. CMOS Inverter Characterisi tcs

The complementry CMOS inverter is realized by the series connection of a p- and as in fig 15.11.

Inverter chara

In the below graphical representation(fig.2.) The I-V characteristics of the p-device is

about x-axis. This step is followed by taking the absolute values of the p-device, superimposing the two characteristics. Solving Vinn and Vinp and Idsn = Idsp gives thetransfer characteristics of a CMOS inverter as in fig1.

Fig 15.11: CMOS Inverter

Fig 15.12: I-V characteristics of PMOS & NMOS Fig 15.13: Transfer Characteristics of CMOS

15.2 Noise Margins

Noise margin is a parameter closely related to the input-output voltage characteristics. This parameter allows us to determallowable noise voltage on the input of a gate so that the output will not be affected. The specification most comused to specify noise margin (or noise immunity) is in terms of two parameters- The LOW noise margin, NML, and thnoised margin, NMH. With reference to Fig 1. NML is defined as the difference in magnitude between the maximum LOWvoltage of the driving gate and the maximum input LOW voltage recognized by the driven gate. Thus,

The value of NMH is difference in magnitude betweminimum HIHG output voltage of the driving gate aminimum input HIGH voltage recognized by the receivinThus,

Where,

VIHmin = minimum HIGH input VILmax = maximum LOW input VOHmin= minimum HIGH output VOLmax= maximum LOW output voltage.

Fig 15.2: Noise Margin diagram




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15.3: Regions of OperationThe operation of CMOS inverter can be divided into five regions .The behavior of n-and p-devices in each of region mausing

We will describe about each regions in details-

Region A :This region is defined by 0 =< Vin < Vtn in which the n-device is cut off (Idsn =0), and the p-device is inregion. SinceIdsn = IIdsp, the drain-to-source current Idsp for the p-device is also zero. But for Vdsp = Vout VDD, = 0,the output voltage is Vout=VDD.Region B :This region is characterized by Vtn =< Vin < VDD /2in which the p-device is in its nonsaturated region (while the n-device is in saturation. The equivalent circuit for the inverter in this region can be represented by a resistortransistor and a current source for the n-transistor as shown in fig. 6 . The saturation current Idsn for the n-device is o

setting Vgs = Vin . This results in

and Vtn =threshold voltage of n-device,n=mobility of electrons Wn= channel width of n-device &Ln= channel length of n-deviceThe current for the p-device can be obtained by noting that Vgs =( Vin VDD )and Vds = (Vout VDD ). And therefore,

and Vtp =threshold voltage of n-device, p=mobility of electrons, Wp= channel width of n-device & Lp= channel length of n-device. The output voltage Vout can be expressed as-

Region C:In this region both the n- and p-devices are in saturation. This is represented by fig 7 which shows two current

sources in series The saturation currents for the two devices are given by

.This yields,

By setting,

Which implies that region C exists only for one valuWe have assumed that a MOS device in saturationlike an ideal current soured with drain-to-source cur

independent of Vds.In reality, as Vds increases,increases slightly; thus region C has a finite slsignificant factor to be noted is that in region C, wecurrent sources in series, which is an unstable con

Fig 15.32: Equivalent circuitof MOSFET in region C

Thus a small input voltage as a large effect at the output. This makes the output transsteep, which contrasts with the equivalent nMOS inverter characteritics. characteritics. The




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expression of Vth is particularly useful since it provides the basis for defining the gate threshold Vinv which corresponstate where Vout=Vin .This region also defines the gain of the CMOS inverter when used as a small signal amplifier.

Region D:This region is described by VDD/2 = VDD -Vtp , in which the pdevice is cut off(Idsp =0), and the n-device is in the linear mode. Here, Vgsp= Vin - VDD Which is more positive thanVtp.The output in this region is Vout=0From the transfer curve , it may be seen that the transition between the two states is very step.Thischaracteristic is very desirable because the noise immunity is maximized.




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15.4n/p ratio:

The gate-threshold voltage, Vinv, where Vin=Vout is dependent onn/p . Thus, for givenprocess, if we want to change n/pwe need tochange the channel dimensions, i.e.,channel-lengthLand channel-width W. Therefore it can be seen

that as the ration/p is decreased, the transitionregion shifts from left to right; however, the outputvoltage transition remains sharp.

Figure 15.4:n/p graph

16.1 Few Definitions

Before calculating the propagation delay of CMOS Inverter, we will define some basic terms-

Switching speed -limited by time taken to charge and discharge, CL . Rise time, tr :waveform to rise from 10% to 90% of its steady state value Fall time tf, :90% to 10% of steady state valueDelay time, td :time difference between input transition (50%) and 50% output level

The propagation delay tp of a gate defines how quickly it respa change at its inputs, it expresses the delay experienced by awhen passing through a gate. It is measured between thtransition points of the input and output waveforms as shown

figure 16.1 for an inverting gate. The defines the respon

of the gate for a low to high output transition, while ref

high to low transition. The propagation delay as the avethe two

Fig 16.1: Propagation delay graph




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16.2 Quick Estimates:

We will give an example of how to calculate quick estimate. From ffig 16.22, we can write following equations..

Fig 16.21: Example CMOS Inverter

Circuit

From figure 16.21, when Vin = 0 the capacitor CL charges through the P-

MOS, and when Vin = 5 the capacitor discharges through the N-MOS

. The capacitor current is -

Fig 16.22 : Propagation Delay of above

MOS Circuit

From this the delay times can be derived as

The expressions for the propagation delays as denoted in the figure (16.22) can be easily seen to be




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16.3 Rise and Fall Times

Figure 16.21 shows the familiar CMOS inverter with a capacity load CL that represents the load capacitance (input of nexoutput of this gate and routing). Of interest is the voltage waveform Vout(t)when the input is driven by a step waveformas shown in figure 16.22 .

Figure 16.31 shows the trajectory of the n-transistor ope

point as the input voltage, Vin(t), changes from 0Vto

Initially, the end-device is cutt-off and the load capacitorcharged to VDD. This illustrated byX1on the charactecurve. Application of a step voltage (VGS=VDD) at thof the inverter changes the operating point toX2. From onwards the trajectory moves on the VGS=VDDcharacteristic curve towards pointX3at the origin.

Fig 16.31: trjectory of n-transistor operating point Thus it is evident that the fall time consists of two interva

1.tf1=period during which the capacitor voltage, Vout, drops from 0.9VDDto (VDD Vtn)2. tf2=period during which the capacitor voltage, Vout, drops from (VDD Vtn )to 0.1VDD.The equivalent circuits that illustrate the above behavior are show in figure (16.32 & 16.33 ).

Figure 16.32: Equivalent circuit for showing behav. of tf1 Figure 16.33: Equivalent circuit for showing behav. o

As we saw in last section, the delay periods can be derived using the generalequation

From figure (16.32) while in saturation,

Integrating from t= t1, corresponding toVout=0.9 VDD, to t= t2corresponding toVout=(VDD-Vtn)results in,

Fig 16.34: Rise and Fall time graph




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When the n-device begins to operate in the linear reg

discharge current is no longer constant. The time tf1taken to discharge the capacitor voltage from (VDD-Vtn)to 0.1Vbe obtained as before. In linear region,

Thus the complete term for the fall time is,

The fall time tf can be approximated as,

From this expression we can see that the delay is directly proportional to the load capacitance. Thus to achieve highcircuits one has to minimize the load capacitance seen by a gate. Secondly it is inversely proportion to the supply voltag

the supply voltage is raised the delay time is reduced. Finally, the delay is proportional to the n of the driving transincreasing the width of a transistor decreases the delay.

Due to the symmetry of the CMOS circuit the rise time can be similarly obtained as;

For equally sized nandptransistors (wheren=2p)tf=trThus the fall time is faster than the rise time primarily due to different carrier mobilites associated with the p and n devices thus ifwe want tf=tr we need to make n/p =1. This implies that the channel width for the p-device must be increased toapproximately 2 to 3 times that of the n-device.

The propagation delays if calculated as indicated before turn out to be,




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If we consider the rise time and fall time of the input signal aswell, as shown in the fig 16.35 we have,

These are the rms values for the propagation delays.

F igure 16.35: Rise and Fall time graph of Output w.r.t Input

17.1 Introduction

The inverter that uses ap-device pull-up or load that has its gate permanently groun-device pull-down or driver is driven with the input signal. This roughly equivalent of a depletion load is Nmos technology and is thus called Pseudo-NMOS. The ciused in a variety of CMOS logic circuits. In this, PMOS for most of the time will beregion. So resistance is low and hence RC time constant is low. When the driver is on a constant DC current flows in the circuit.

Fig 17.1: CMOS Inverter

Circuit

17.2 Different Configurations with NMOS Inverter

Cascade pseudo NMOS invertor: Saturated n-mosNMOSinvertor:

More saturated NMOS Loadinvertor:




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11.1 MotivationIn VLSI design, as processes become more and more complex, need for the designer to understand the intricacies of thefabrication process and interpret the relations between the different photo masks is really trouble some. Therefore, a set orules, also calleddesign rules, has been defined. They act as an interface or communication link between the circuit designthe process engineer during the manufacturing phase. The objective associated with layout rules is to obtain a circuit withoptimum yield (functional circuits versus non-functional circuits) in as small as area possible without compromising reliabil

the circuit. In addition, Design rules can be conservative or aggressive, depending on whether yield or performance is desGenerally, they are a compromise between the two. Manufacturing processes have their inherent limitations in accuracy. Sneed of design rules arises due to manufacturing problems like -

Photo resist shrinkage, tearing.

Variations in material deposition, temperature and oxide thickness.

Impurities.

Variations across a wafer.

These lead to various problems like :

Transistor problems:Variations in threshold voltage: This may occur due to variations in oxide thickness, ion-implantation and poly layer.Changes in source/drain diffusion overlap.Variations in substrate.

Wiring problems:Diffusion: There is variation in doping which results in variations in resistance, capacitance.Poly, metal: Variations in height, width resulting in variations in resistance, capacitance.Shorts and opens.

Oxide problems:Variations in height.Lack of planarity.

Via problems:Via may not be cut all the way through.Undersize via has too much resistance.Via may be too large and create short.

To reduce these problems, the design rules specify to the designer certain geometric constraints on the layout artwork so patterns on the processed wafers will preserve the topology and geometry of the designs. This consists of minimum-widthand minimum-spacing constraints and requirements between objects on the same or different layers. Apart from following definite set of rules, design rules also come by experience.

11.2 Types of Design Rules

The design rules primary address two 1. The geometrical reproduction of features that can be reproduced by the making and lithographical process 2. The interaction between different layers.

There are primarily two approaches in describing the design rules.




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Figure 11.32 :CMOS Inverter Layout

Figure 11.31 Mead Conway Color coding for layers




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11.4 Stick DiagramsAnother popular method of symbolic design is "Sticks" layout. In this, the designer draws a freehand sketch of a layoutcolored lines to represent the various process layers such as diffusion, metal and polysilicon .Where polysilicon cdiffusion, transistors are created and where metal wires join diffusion or polysilicon, contacts are formed.This notation indicates only the relative positioning of the various design components .The absolute coordinates oelements are determined automatically by the editor using a compactor. The compactor translates the design rules into aconstraints on the component positions ,and solve a constrained optimization problem that attempts to minimize the area

function.The advantage of this symbolic approach is that the designer does not have to worry about design rules, because the comensures that the final layout is physically correct. The disadvantage of the symbolic approach is that the outcothe compaction phase is often unpredictable. The resulting layout can be less dense than what is obtained with the approach. In addition, it does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

For example, stick diagram for CMOS Inverter is shown below.

Figure 11.41: Stick Diagram of a CMOS Inverter

11.1 Background

As we studied in the last lecture, Layout rules are used to prepare the photo mask used in the fabrication of integrated The rules provide the necessary communication link between the circuit designer and process engineer. Design rules rethe best possible compromise between performance and yield.

The design rules primarily address two issues -

1. The geometrical reproductions of features that can be reproduced by mask making and lithographical pro2. Interaction between different layers

Design rules can be specified by different approaches

1. -based design

2. -based design rules

As -based layout design rules were originally devised to simplify the industry- standard -based design rules and t

scaling capability for various processes. It must be emphasized, however, that most of the submicron CMOS process

rules do not lend themselves to straightforward linear scaling. The use of -based design rules must therefore be hand

caution in sub-micron geometries.

In further sections of this lecture, we will present a detailed study about -based design rules.




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11.2 -based Design Rules

Features of -based Design Rules : -based Design Rules have the following features-

is the size of a minimum feature

All the dimensions are specified in integer multiple of .

Specifying particularizes the scalable rules.

Parasitic are generally not specified in

units These rules specify geometry of masks, which will provide reasonable yields

Guidelines for using -based Design Rules:

As, Minimum line width of poly is 2& Minimum line width ofdiffusion is 2

As Minimum distance between two diffusion layers 3

As It is necessary for the poly to completely cross activwise the transistor that has been created crossing of dand poly, will be shorted by diffused path of source and

-based Design Rules (contd...)

Contact cut on metal

Contact window will be of 2 by 2 that isminimum feature size while metal depositionis of 4by 4for reliable contacts.

In Metal

Two metal wires have 3distance between them to overcome

capacitance coupling and high frequency coupling. Metalwires width can be as large as possible to decreaseresistance.

Buttering contact

Buttering contact is used to make poly andsilicon contact.Window's original width is 4, but on




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overlapping width is 2.So actual contact area is 6by 4.

-based Design Rules (contd...)

The distance between two wells depends on the well potentials asshown above. The reason for 8l is that if both wells are at same highpotential then the depletion region between them may touch each othercausing punch-through. The reason for 6l is that if both wells are atdifferent potentials then depletion region of one well will be smaller, soboth depletion region will not touch each other so 6l will be good enough.

The active region has length 10which is distributed over the followings-

2for source diffusion

2for drain diffusion

2for channel length

2for source side encroachment

2for drain side encroachment




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7.1 Motivation fo r Scaling

The reduction of the dimensions of a MOSFET has been dramatic during the last three decades. Starting at a minimum length of 10 mm in 1970 the gate length was gradually reduced to 0.15 mm minimum feature size in 2000, resulting inreduction per year. Proper scaling of MOSFET however requires not only a size reduction of the gate length and width brequires a reduction of all other dimensions including the gate/source and gate/drain alignment, the oxide thickness adepletion layer widths. Scaling of the depletion layer widths also implies scaling of the substrate doping density.

In short, we will study simplified guidelines for shrinking device dimensions to increase transistor density & operating freand reduction in power dissipation & gate delays.

7.2 Types of Scaling

Two types of scaling are common: (i) constant field scaling and

(ii) constant voltage scaling.

Constant field scaling yields the largest reduction in the power-delay product of a single transistor. However, it requires areduction in the power supply voltage as one decreases the minimum feature size.Constant voltage scalingdoes not have this problem and is therefore the preferred scaling method since it provides voltagecompatibility with older circuit technologies. The disadvantage of constant voltage scaling is that the electric field increases asthe minimum feature length is reduced. This leads to velocity saturation, mobility degradation, increased leakage currents andlower breakdown voltages.

After scaling, the different Mosfet parameters will be converted as given by table below :Before Scaling After Constant Field Scaling After Constant Voltage Scaling

L

W

t

xi

VDD

VTh

Na orNd

Cox

IDS

PD

Where s=scaling parameter of MOS

7.3 Short Channel Effect

So far our discussion was based upon the assumptions that channel was long and wide enough, so that edge effects al

four sides was negligible, longitudinal field was negligible and electric field at every point was perpendicular to the surfacecould perform one-dimensional analysis using gradual channel approximation. But in devices where channel is short longfield will not be negligible compared to perpendicular field. So in that case one-dimensional analysis gives wrong results will have to perform dimensional analysis taking into account both longitudinal and vertical fields. (which is out of the scocourse)

When is a channel called a short cha (i) When junction (source/drain) length is of the order of channel (ii) L is not much larger then the sum of the drain and source depletion width.




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We have shown below the comparative graphs of I-V characteristics for both long channel and short channel

MOSFETs. From graph, it can be clearly concluded that when the channel becomes short, the current in saturationbecomes linearly dependent on applied drain voltage rather than being square dependent.

Figure 7.3: Comparison of ID vs VDS characteristics for long and short channel MOSFET dev




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Cascade pseudo NMOS invertor:Saturated n-mosNMOSinvertor:

More saturatedNMOS Load invertor:

17.3 CMOS SummaryLogic consumes no static power in CMOS design style. However, signalshave to be routed to the n pull down network as well as to the p pull upnetwork. So the load presented to every driver is high. This is exacerbatedby the fact that n and p channel transistors cannot be placed close togetheras these are in different wells which have to be kept well separated in orderto avoid latchup.

17.4 Pseudo nMOS Design StyleThe CMOS pull up network is replaced by a single pMOS transistor with its gate

grounded. Since the pMOS is not driven by signals, it is always on'. The effectivegate voltage seen by the pMOS transistor is Vdd. Thus the overvoltage on the p

channel gate is always Vdd-VTp. When the nMOS is turned on', a direct pathbetween supply and ground exists and static power will be drawn. However, thedynamic power is reduced due to lower capacitive loading.

17.5 Static Characterist icsAs we sweep the input voltage from ground to , weencounter the following regimes of operation:

nMOS off

nMOS saturated, pMOS linear




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nMOS linear, pMOS linear

nMOS linear, pMOS saturated

17.6 Low input

When the input voltage is less than VTn.

The output is high and no current is drawn from the supply.As we raise the input just above VTn, the output starts falling.In this region the nMOS is saturated, while the pMOS is linear.

17.7 nMOS saturated, pMOS linearThe input voltage is assumed to be sufficiently low so that the output voltageexceeds the saturation voltage Vi - VTn. Normally, this voltage will be higher thanVTp, so the p channel transistor is in linear mode of operation. Equating currents

through the n and p channel transistors, we get

defining and we get

17.7 nMOS saturated, pMOS l inear (contd..)




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The solutions are:

substituting the values of V1 and V2 and choosing the sign which puts V0 in the

correct range, we get

As the input voltage is increased, the output voltage will decrease.

The output voltage will fall below Vi - VTnwhen

The nMOS is now in its linear mode of operation. The derived equation doesnot apply beyond this input voltage.




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First we will show you how the fan-in and fan-out depends on propagation delay and then wanalyze how to make Fan-in large.

The propagation delay of a CMOS gate deteriorates rapidly as a function of the fan-in . firstlarge number of transistor (2N) increases the overall capacitance of the gate. Secondly a s

connection of transistor either in the PUN or PDN slows the gate as well, because the effe(dis)charging resistance is increased .

Fan-outhas a lager impact on the gate delay in complementary CMOS than some otherstates. In complementary cstyle, each input connects to both an NMOS and a PMOS device and presents a load tdriving gate equal to the sum of the gates capacitances.

Thus we can approximateinfluence of fan in and fan-opropagation delay complementary CMOS gate as

Where a1, a2 and a3weighing factor which are a funof technology

Fig 18.1: Dependence of Propagation delay on Fan-in

18. 2 Design techniques for large fan in

1. Transistor Sizing: Increasing the transistor sizes increases the available (dis)chacurrent. But widening the transistor results in large parasitic capacitor. This does not only the propagation delay of the gate but also present a larger load to the preceding gate.

2. Progressive Transistor Sizing: Usually we assume that all the intrinsic capacitancesseries connected array

transistors, can be lumped into a single load capacitance CL and no capacitance is presethe internal nodes of network.




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Under these assumptions making all transistors in a series equal in size makes sense. This model is an over-simplificationbecome more and more incorrect for increasing fan in. referring tcircuit below we can see that the capacitor associated wit

transistor as we go down the chain increases and so the tranhas to discharge an increasing current as we go down the c

While transistor MN has to conduct the discharge current only ocapacitance CL.M1 has to carry the discharge current from thecapacitance Ctot=C1+ C2 + ....+CL, which is substantially laConsequently a progressive scaling of the transistors is bene

M1>M2>M3>....>MN. This technique has for instance provbe advantageous in the decoders of memories where gates with fan in are common. The effect of progressive sizing caunderstood by the circuit in fig 18.21.

Spice simulation Example:Taking CL=15fF; N=5;C1=C2=C3=C4=10fF.

Fig 18.21: Illustration ofProgressive TransistorSizing

When all transistors are of minimum size SPICE predic

propagation delay of 1.1nsecs. The transistors M5 toM1 aremade progressively wider in such a way that the width of the tran

is proportional to the total capacitor it has to discharge. M5minimum size, WM4=WM5(CL+ C4WM3=WM5(CL+C3+C4)/CL and so on. The resulting circu

tpHLof 0.81nsecs or a reduction of 26.5%.




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3. Transistor Ordering: Some signals in complex combinational logic blocks might be more

critical than others .no all inputs of a gate arrive at the same time (may bdue to propagation delays of thepreceding blocks). An input signal to gate is called critical if it is the last sigof all input to assume a stable value. path through the logic which determinthe ultimate speed of the structures iscalled the critical path. Putting the cripath transistor closer to the output ofgate can result in a speed up. Referr

the figure given below signal In1isassumed to be the critical signal. Supwe assume signal In2and In3are higand In1undergoes a 0to 1transition

Assume also that CLis initially charghigh in 1st case no path to ground ex

until M1 is turned on .the delay betwthe arrival of In1and the output istherefore determined by the time it ta

to discharge CL+C1+ C2. In the 2case C1and C2are already discharwhen In1changes. Only CLhas to bdischarged, resulting in a faster respotime.

Fig18.21: Two examples circu its for critical path Using SPICE thetPHL for a 4-input gate was calculated.

With the critical input connected to the bottommost transistor the tpd =717ns and connected to the uppermost transistor tpd = 607 ns, an improvement of 15%.




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The pass transistor MP is driven by the periodicclock signal and acts as an access switch to either

charge up or down the parasitic capacitance, Cxdepending on the input signal Vin. Thus there are 2possible operations when the clock signal is activeare the logic 1 transfer( charging up the

capacitance Cx to logic high level) and the logic 0transfer( charging down the capacitance Cx to alogic low level). In either case, the output of

Fig 19.21: Pass Transistor Logic Circuit

the depletion load of the nMOS inverter obviouslyassumes a logic low or high level, depending on the

voltage Vx.The pass transistor MP provides the only current path to the intermediate capacitive node X. whenclock signal becomes inactive (clk=0) the pass transistor ceases to conduct and the charge is

stored in the parasitic capacitor Cx continues to determine the output level of the inverter.Logic 1 Transfer:Assume that the Vx = 0initially. A logic "1"level is applied to the inputterminal which corresponds to Vin=VOH=VDD. Now the clock signal at the gate of the passtransistor goes from0to VDDatt=0. It can be seen that the passtransistor starts to conduct and operate in saturation throughout this cycle since VDS=VGS.

Consequently VDS>VGS-Vtn.Analysis: The pass transistor operating in saturation region starts to charge up the capacitor Cxthus:

Contd...

The previous equation for Vx(t)can be solved as-

The variation of the node voltage Vx(t)is plotted asa function of time in fig. 19.22. The voltage rises from

its initial value of 0 and reaches Vmax =VDD-Vtnafter a large time. The pass transistor will turn offwhen Vx = Vmax. Since Vgs= Vtn . Therefore Vxcan never attain VDD during logic 1 transfer. Thuswe can use buffering to overcome this problem.

Logic 0 Transfer:Assume that the Vx=1initially.A logic0 level is

Fig 19.22: Node Voltage Vx vs t




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applied to the input terminal which corresponds to Vin=1. Now the clock signal at the gate of thepass transistor goes from 0 to VDD at t=0. It can be seen that the pass transistor starts toconduct and operate in linear mode throughout this cycle and the drain current flows in theopposite direction to that of charge up.

Analysis: We can write -

The above equation for Vx(t) can be solved as -

Plot of Vx(t) is shown in figure 19.23.

Fig 19.22: Node Voltage Vx vs t

19.3 Dynamic Logic Circuits In case of static CMOS for a fan-in of N, 2N transistors are required. In order to reducevarious other design logics were used like pseudo-NMOS logic and pass transistor However the static power consumption in these cases increased. An alternative to these dlogics is Dynamic logic, which reduces the number of transistors at the same time keecheck on the static power consumption.

Principle: A block diagram of a dynamic logic circuit is as shown in fig 19.31. This uses Nblock to implement its logicThe operation of this circuit can be explained in two m1) Prec2) EvaluationIn the precharge mode, the CLK input is at logic 0. This f

the output to logic 1, charging the load capacitance to VSince the NMOS transistor M1 is off the pull-path is disabled. There is no static consumption in this cathere is no direct between supply and ground.

In the evaluation mode, the CLK input is at logic 1. Nowoutput depends on the PDN block. If there exists a path thPDN to ground (i.e. the PDN network is ON), the capacitwill discharge else it remains at logic1.As there exists onlpath between the output node and a supply rail, which canbe ground, the load capacitor can discharge only once and happens, it cannot charge until the next precharge oper

Hence the inputs to the gate can make at most one tran




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during evaluationAdvantages of dynamic logic circ1) As can be seen, the number of transistors required herN+2 as compared 2Nin the Static CMOS circuits.

Fig 19.31: Dynamic CMOS2) This circuit is still a ratioless circuit as in Static case. Hprogressive and ordering of the transistors in the PDN block is impo3) As can be seen, the static power loss is negligible.

Block Diagram

Disadvantages of dynamic logic circuits:

1) The penalty paid in such circuits is that theclock must run everywhere to each suchblock as shown in the diagram.2) The major problem in such circuits is thatthe output node is at Vdd till the end of theprecharge mode. Now if the CLK in the next

block arrives earlier compared to the CLK inthis block, or the PDN network in this blocktakes a longer time to evaluate its output,then the next block will start to evaluateusing this erroneous value

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