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SEMISTER VIII – BIOMEDICAL ENGINEERING

Syllabus

Solutions

Layout

Problems

VHDL programs

*For complete understanding of the subject one must refer to the prescribed

reference books.

A.E

Copyrights reserved

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1. P-well CMOS process in detail

As the name suggests p well needs to be fabricated.

Therefore we need N- type silicon substrate.

Step 1:

First we need to have N type silicon substrate. This is done during CZ process.

When single crystal is obtained during CZ process, it is doped with n type impurity (eg.

Phosphorous) and cut into wafer. Thus we get n-type silicon substrate.

Step 2:

Next step is to form a p well inside a N-type silicon substrate.

Therefore the silicon substrate or wafer undergoes oxidation.

Silicon substrate is heated at high temperature in presence of oxygen and a layer of SiO2

is formed all over the silicon substrate.

Then p-well is to be formed inside the n-type silicon substrate. Thus SiO2 layer is to be

etched out to diffuse p-type impurity.

Using a mask and photoresist a window is formed in SiO2 for p-type diffusion and a p-

well is formed.

Step 3:

Using a mask, thick oxide is removed for PMOS fabrication.

Step 4:

Next step is to form gate for NMOS as well as PMOS. A thin layer SiO2 or thinox is

deposited all over the surface of the silicon wafer.

Thinox should define the area for the gate.

Thinox is removed from where it is not required using a mask.

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Step 5:

A layer of polysilicon is deposited over Si wafer surface.

Polysilicon acts as the gate for NMOS and PMOS.

Hence polysilicon is removed from where it is not required.

Step 6:

During this step PMOS is to be fabricated.

For this p-type impurity is to be diffused which should not affect the p-well.

Hence p-well is covered with photoresist.

p-type impurity is diffused into n-type Si substrate. Eg. Boron.

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Step 7:

During this step NMOS transistor is formed.

The PMOS transistor should not get affected. Hence it is covered with a photoresist.

p-well is exposed to n-type impurity. It is diffused to form n-type drain and source.

Step 8 :

Again silicon wafer is exposed to oxidation.

Another SiO2 is deposited to isolate few components.

Mask is used to remove unwanted components.

Step 9:

Si wafer is exposed to aluminum metal.

It is deposited all over the surface for contact cut. And using a mask, the metal is

removed from where interconnections are not requires.

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2. Explain twin tub fabrication process in detail (jun 11)

TWIN TUB

To avoid latch up, this is one of the method for CMOS fabrication.

Here the substrate over which CMOS is to be fabricated can be any type. i.e it can be n-

type silicon substrate or p-type silicon substrate.

• A n-type silicon substrate with lower doping or high resistivity is taken. • Further this n+ Si substrate is grown further over the n-type silicon substrate.

• Silicon substrate is subjected to oxidation & SiO2 layer is formed

• It is etched out using a mask and two windows are formed one for n-well and another

for p-well

• Covering 1st window using a photoresist mask,p-type material is diffused to form p-well.

• Similarly 2nd window is covered and n-well is formed.

• Thin layer of SiO2 thin ox is deposited on the well to locate the gates for NMOS and

PMOS. A mask is used to remove the excess thin ox where it is not required.

• Polysilicon is deposited over the thin ox and excess of it is removed from where it is not

required. P-well is covered with a photoresist mask and p-type diffusion is done to n-

well to form PMOS.

• Similarly n-well is covered with a photoresist mask and n-type diffusion is done to p-well

to form NMOS.

• Silicon wafer obtained in the previous process is again subjected to oxidation and a thick layer of SiO2 is formed for isolation. It is etched out to expose the drain. The wafer is subjected to aluminum metal. It is deposited all over the wafer surface for contact cuts.

3. What is Scaling (jun 11)

SCALING

INTRODUCTION:

The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology requires that the packing density of MOSFETs used in the circuits is as high as possible and, consequently, that the sizes of the transistors are as small as possible. The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as scaling.

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It is expected that the operational characteristics of the MOS transistor will change with the reduction of its dimensions. Also, some physical limitations eventually restrict the extent of scaling that is practically achievable. There are two basic types of size-reduction strategies: Full scaling (Constant-field scaling) and Constant Voltage Scaling. Scaling of MOS transistors is concerned with systematic reduction of overall dimensions of the devices as allowed by the available technology, while preserving the geometric ratios found in the larger devices. The proportional scaling of all devices in a circuit would certainly result in a reduction of the total silicon area occupied by the circuit, thereby increasing the overall functional density of the chip. To describe device scaling, we introduce a constant scaling factor S >1. All horizontal and vertical dimensions of the large-size transistor are then divided by this scaling factor to obtain the scaled device. The extent of scaling that is achievable is obviously determined by the fabrication technology and more specifically, by the minimum feature size.

FULL SCALING (CONSTANT-FIELD SCALING) :-

This scaling option attempts to preserve the magnitude of internal electric fields in the MOSFET, while the dimensions are scaled down by a factor of S. To achieve this goal, all potentials must be scaled down proportionally, by the same scaling factor. Note that this potential scaling also affects the threshold voltage VTHO. Finally, the Poisson equation describing the relationship between charge densities and electric fields dictates that the charge densities must be increased by a factor of S in order to maintain the field conditions. Table lists the scaling factors for all significant dimensions, potentials, and doping densities of the MOS transistor.

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Now consider the influence of full scaling described here upon the current-voltage characteristics of the MOS transistor. It will be assumed that the surface mobility is not significantly affected by the scaled doping density.

1) The gate oxide capacitance per unit area, on the other hand, is changed as follows.

The aspect ratio W/L of the MOSFET will remain unchanged under scaling. Consequently, the transconductance parameter [kn] will also be scaled by a factor of S. Since all terminal voltages are scaled down by the factor S.

2) The linear-mode drain current of the scaled MOSFET can now be found as:

3) The saturation-mode drain current is also reduced by the same scaling factor.

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4) The power dissipation of the MOSFET. Since the drain current flows between the source and the drain terminals, the instantaneous power dissipated by the device (before scaling) can be found as:

Notice, that full scaling reduces both the drain current and the drain-to-source voltage by a factor of S, hence, the power dissipation of the transistor will be reduced by the factor S2. This significant reduction of the power dissipation is one of the most attractive features of full scaling. Note that with the device area reduction by S2, we find the power density per unit area remaining virtually unchanged for the scaled device.

CONSTANT-VOLTAGE SCALING :- While the full scaling strategy dictates that the power supply voltage and all terminal voltages be scaled down proportionally with the device dimensions, the scaling of voltages may not be very practical in many cases. In particular, the peripheral and interface circuitry may require certain voltage levels for all input and output voltages, which in turn would necessitate multiple power supply voltages and complicated level shifter arrangements. For these reasons, constant-voltage scaling is usually preferred over full scaling. In constant-voltage scaling, all dimensions of the MOSFET are reduced by a factor of S, as in full scaling but the power supply voltage and the terminal voltages, on the other hand, remain unchanged. The doping densities must be increased by a factor of S2 in order to preserve the charge-field relations.

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The gate oxide capacitance per unit area Cox is increased by a factor of S, which means that the transconductance parameter is also increased by S. Since the terminal voltages remain unchanged.

1) The linear mode drain current of the scaled MOSFET :-

2) The saturation-mode drain current will be increased by a factor of S after constant

voltage scaling. This means that the drain current density (current per unit area) is increased by a factor of S3, which may cause serious reliability problems for the MOS transistor.

3) The power dissipation. Since the drain current is increased by a factor of S while the drain-to-source voltage remains unchanged, the power dissipation of the MOSFET increases by a factor of S.

Finally, the power density (power dissipation per unit area) is found to increase by a factor of S3

after constant-voltage scaling, with possible adverse effects on device reliability.

To summarize, constant-voltage scaling may be preferred over full (constant-field) scaling in many practical cases because of the external voltage-level constraints. It must be recognized, however, that constant-voltage scaling increases the drain current density and the power density by a factor of S3. This large increase in current and power densities may eventually cause serious reliability problems for the scaled transistor, such as electromigration, hot-carrier degradation, oxide breakdown, and electrical over-stress.

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4. n- c ha nne l D e ple t i on T y pe .M OS F ET Basic Construction : A s lab of p-type si l icon substrate is formed from si l icon. The substrate is the foundat ion over which the device is constructed, n -type material is dif fused into the substrate co form the dra in and the source the n -channel MOSFET. The drain and the source regions are l inked to each other by an n -channel as shown in the figure). This n-type channel is formed during the fabrication process.

There are 3 metallic terminals taken out. One is for the gate and the other two are the drain

and the source.

The gate- terminal has a polysilicon oxide layer below it. This layer is an insulating layer. Hence

there is no electrical connection between the gate terminal and the channel of the MOSFET.

Also this gives rise to a very high input impedance of the device and the gate current is almost

zero.

Basic Operation and Characteristics

The MOSFET is to be operated in the reverse bias mode. Hence the drain terminal is given some

positive potential with respect to the source.

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Case (i) Vgs = 0

Initially let the gate to source voltage be zero. And the voltage VDS is increased in the positive

direction. As a result, the free electrons in the n-channel set attracted to the positive drain

terminal.

And as the conventional current direction is that of holes. The conventional current ID, flows in

the opposite direction i.e. as shown in the figure.

The current flowing is IDss i.e- saturation current. This is shown in the figure

Case (i) Vgs > 0

If voltage Vg s is made posit ive more than 0 volt, say V = 1 V.

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The s il icon substrate is rich in holes but a lso it has got few electrons. This posit ive voltage applied to the gate attracts these e lectrons. Thus the number of e lectrons in the channel increases. With pos itive V DS voltage, these e lectrons get attracted to the dra in and the dra in current flows. Here as the e lectrons in the channel are more, the dra in current is also more. I f Vg s is made even more posit ive say V g s = 2 V, even more electrons get attracted to the gate terminal. Hence the dra in current is a lso more. This is shown in f igure.

Case (iii) Vgs < 0

If voltage Vgs is made negative.

The gate voltage repels the electrons present in the channel and the holes present in the p-type

Si substrate get attracted to the gate terminal. This is shown in figure.

The drain current flows but it is less than that of case (i) and case (ii).

If voltage Vgs is made more negative, more and more electrons get repelled from the channel,

lesser number of electrons remain in the channel, and the drain current reduces further.

for Vgs = 0, the current ID = IDSS

for Vgs > 0, the current ID < IDSS

for Vgs < 0, the current ID > IDSS

Drain current ID remains constant after a particular value of VDS and this is true for every value

of Vgs. As VD increases, more .and more reverse bias is increased and the depletion layer also

increases in its thickness.

At one point, pinch off occurs and a constant ID flows through the channel.

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5. CZ process of wafer preparation

The technique was developed by Czochralski and the process is mainly used to grow

silicon crystals from which silicon wafers are produced.

The process is characterized by a liquid-solid mono component growth system.

This technique involves the solidification of atoms from a liquid phase at an interface.

The apparatus used for CZ crystal growth is also known as PULLER.

The speed of growth is determined by the number of sites on the face of the crystal and

the specifics of heat transfer at the interface.

The puller has four main parts.

1. Furnace:

It includes a fused silica crucible, a graphite susceptor, a rotation mechanism, a

heating element and a power supply.

The crucible contains the melt (molten silicon).

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It should be unreactive to silicon and have thermal stability. The graphite susceptor

is used to support the silica crucible.

The susceptor is placed on a pedestal whose shaft is connected to a motor that

provides rotation.

To melt the charge, radio frequency heating or resistance heating is used and finally

is connected to a dc power supply.

2. Crystal pulling mechanism:

This mechanism should control the pull rate and crystal rotation.

That is the seed crystal is simultaneously puiled up and rotated to meet proper

growth.

3. Ambient control:

This includes an inert gas source (e.g., Argon) a flow control and an exhaust

system. The gas source must meet the purity requirements.

4. Control system:

The control system includes control of process parameters like temperature,

crystal diameter, pull rate, rotation speed. Programmed process steps are

provided through microprocessor based control and infrared sensors are used to

judge any change.

Working:

Polycrystalline silicon is placed in the crucible and the furnace is heated to melt

silicon.

A suitably oriented seed crystal is placed over the crucible in the seed holder.

The seed is dipped into the melt.

Some part the seed melts and some touch the liquid surface. The seed is then

slowly pulled up.

So freezing at the solid-liquid interface occurs and single crystal is formed. The

seed crystal in this form is known as ingot.

In the growth process, a known amount of dopant is added to the melt to obtain

desired doping concentration in the grown crystal.

Boron is usually added for p-type material and phosphorus for n-type material.

The ingot so obtained is hard and brittle.

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To give a shape to the ingot to form wafers, it is treated with a series of

mechanical and chemical processes.

The material used for cutting and shaping silicon is usually diamond. After

cutting and polishing the silicon wafers are packaged to be used to fabricate

integrated circuits.

The two- ends of ingot is known as seed and tang.

The first step in silicon shaping operations is the removal of seed and tang ends

using a circular saw.

In the left over crystal resistivity and perfection analysis is carried on.

The portions that fail to show acceptable resistances and perfections are also

cut off. These cut off portions can be recycled and can also be used for other

purposes.

At the time of crystal-growth, the growing process is not uniform so that there is

a variation in diameter along the length of the ingot. This is because of the

inability to control the growth rate properly.

After the crystal is grown, the seed is removed and the surface is grinded so that

the diameter of the material is defined.

A rotating cutting tool makes multiple passes down a rotating ingot until the

chosen diameter is attained. After that one or more flats are ground along the

length of the ingot.

There are usually two flats known as primary (major) and secondary (minor) flat.

The primary flat helps to form an array of square die (chip) on the wafer and the

secondary flat helps to identify the orientation and conductivity type of the

material.

After grinding the ingot is sliced into wafers by diamond saws.

The surface orientation, thickness, taper (variation in thickness) and bow

(curvature) are determined from slicing. The wafers are usually 10 to 30 cm in

diameter and 400 to 600 micro meter thick.

The surface of the wafer is then polished to a mirror finish using chemical and

mechanical polishing to obtain a smooth, defect free surface.

Wafer polishing can be done on a single wafer in a batch processing manner.

The polishing pad is made up of artificial fabric.

The wafers are mounted on a fixture, pressed against this pad under high

pressure and are rotated.

A mixture of polishing slurry and water, dripped on to the pad does the

polishing.

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The wafers are now ready for the fabrication of integrated circuits. The

schematic for the wafer shaping operations are shown in Fig.

6. Design rules and Layout

Layout Design Rules

The physical mask layout of any circuit to be manufactured using a particular process

must conform to a set of geometric constraints or rules, which are generally called

layout design rules.

These rules usually specify the minimum allowable line widths for physical objects on-

chip such as metal and polysilicon interconnects or diffusion areas, minimum feature

dimensions, and minimum allowable separations between two such features.

If a metal line width is made too small, for example, it is possible for the line to break

during the fabrication process or afterwards, resulting in an open circuit. If two lines are

placed too close to each other in the layout, they may form an unwanted short circuit by

merging during or after the fabrication process. The main objective of design rules is to

achieve, for any circuit to be manufactured with a particular process, a high overall yield

and reliability while using the smallest possible silicon area.

Note that there is usually a trade-off between higher yield, which is obtained through

conservative geometries, and better area efficiency, which is obtained through

aggressive, high-density placement of various features on the chip.

The layout design rules which are specified for a particular fabrication process normally

represent a reasonable optimum point in terms of yield and density. It must be

emphasized, however, that the design rules do not represent strict boundaries which

separate "correct" designs from "incorrect" ones. A layout which violates some of the

specified design rules may still result in an operational circuit with reasonable yield,

whereas another layout observing all specified design rules may result in a circuit which

is not functional and/or has very low yield.

To summarize, we can say, in general, that observing the layout design rules significantly

increases the probability of fabricating a successful product with high yield. The design

rules are usually described in two ways:

(i) Micron rules, in which the layout constraints such as minimum feature sizes and

minimum allowable feature separations are stated in terms of absolute

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dimensions in micrometers, or,

(ii) Lambda rules, which specify the layout constraints in terms of a single

parameter (X) and thus allow linear, proportional scaling of all geometrical

constraints.

Lambda-based layout design rules were originally devised to simplify the industry

standard micron-based design rules and to allow scaling capability for various processes.

It must be emphasized, however, that most of the submicron CMOS process design rules

do not lend themselves to straightforward linear scaling.

The use of lambda-based design rules must therefore be handled with caution in submicron

geometries. In the following, we present a sample set of the lambda-based layout design rules

devised for the MOSIS (MOS Implementation System) CMOS process and illustrate the

implications of these rules on a section of a simple layout which includes two transistors.

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7. Explain Latch up in CMOS (Dec11, May 12)

Latch up in CMOS

• When CMOS fabrication process follows p-well or n-well process, a problem called latch

up occurs.

• Latch up is mainly because of parasitic transistors or large number of junctions which

are formed in these CMOS structures.

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• Latch up is a condition in which parasitic components give rise to the establishment of

low resistance conducting paths between VDD and ground which results in some failure.

• Refer figure.

• There are two parasitic transistors formed, one is vertical pnp transistor Q1 and

another is a lateral npn transistor, Q2.

• The vertical transistor Q1 has its emitter formed by the p-plus diffusion (source/drain)

used in PMOS transistor. The base is formed by the n-well while the collector is formed by the

p-substrate.

• For the lateral transistor Q2, the emitter is formed by the n-plus diffusion (source/drain)

used in NMOS transistor. The base is p-type silicon substrate and the collector is the n-well.

• R well is the resistance offered by the n-well.

• Rsub is the resistance offered by the p-type silicon substrate.

• These parasitic transistors Q1, Q2 and the resistors R-well and R-substrate give rise to a

circuitry as shown in figure (b).

• latch up may be induced by glitches on the supply rails or by incident radiation.

Sometimes it is possible because of noise that the o/p terminal voltage drops about 0,7 V below

the ground or Vss, i.e. the ground is at a higher potential and the current in the channel for

NMOS flows' such that more and more e- flow towards the ground.

• This gives rise to emitter current for the transistor Q2 and the emitter terminal of Q2

becomes negative so that VBE drop of Q2 is established such that Q2 turns on and the current

flows through Rsub and R well.

• The voltage drop across Rwell give rise to turning on of the transistor Q1.

• This establishes a low resistance path between the supply rails and there is an unwanted

current flow between the supplies.

• This is called latch up.

• The circuit is as good as a SCR (Silicon Controlled Rectifier).

• The latch up condition is maintained till the current flows.

• The current can be reduced by reducing the resistance R-substrate. This can be done

during fabrication only, lower the Rsub value, lower the voltage drop across Rsub, and the

turning on of Q2 is not ensured. Hence latch up can be avoided.

• Similar latch up is possible for CMOS using p-well process.

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8. MOSFET Capacitances

The majority of the topics covered in this chapter has been related to the steady-state

behavior of the MOS transistor. The current-voltage characteristics investigated here can

be applied for investigating the DC response of MOS circuits under various operating

conditions.

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In order to examine the transient (AC) response of MOSFETs and digitalcircuits

consisting of MOSFETs, on the other hand, we have to determine the nature and the

amount of parasitic capacitances associated with the MOS transistor.

The on-chip capacitances found in MOS circuits are in general complicated functions

of the layout geometries and the manufacturing processes.

Most of these capacitances are not lumped, but distributed, and their exact calculations

would usually require complex, three-dimensional nonlinear charge-voltage models. In

the following, we will develop simple approximations for the on-chip MOSFET

capacitances that can be used in most hand calculations.

These capacitance models are sufficiently accurate to represent

the crucial characteristics of MOSFET charge-voltage behavior, and the equations

are all based on fundamental semiconductor device theory, which should be familiar to

most readers.

We will also stress the distinction between the device-related capacitances

and the interconnect capacitances. The capacitive contribution of metal interconnections

between various devices is a very important component of the total parasitic capacitance

observed in digital circuits.

Figure shows the cross-sectional view and the top view (mask view) of a typical

n-channel MOSFET. Until now, we concentrated on the cross-sectional view of the

device, since we were primarily concerned with the flow of carriers within the MOSFET.

As we study the parasitic device capacitances, we will have to become more familiar

with

the top view of the MOSFET. In this figure, the mask length (drawn length) of the gate

is indicated by LM, and the actual channel length is indicated by L.

The extent of both the

gate-source and the gate-drain overlap are LD; thus, the channel length is given by

L = LM – 2. LD

Note that the source and drain overlap region lengths are usually equal to each other

because of the symmetry of the MOSFET structure.

Typically, LD is on the order of 0.1 gm. Both the source and the drain diffusion regions

have a width of W.

The typical diffusion region length is denoted by Y. Note that both the source diffusion

region and the drain diffusion region are surrounded by a p+ doped region, also called

the channel-stop implant.

As the name indicates, the purpose of this additional p+ region is to prevent the

formation of any unwanted (parasitic) channels between two neighboring n+ diffusion

regions, i.e., to ensure that the surface between two such regions cannot be inverted.

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Hence, the p+ channel-stop implants act to electrically isolate neighboring devices built

on the same substrate. We will identify the parasitic capacitances associated with this

typical MOSFET structure as lumped equivalent capacitances observed between the

device terminals since such a lumped representation can be easily used to analyze the

dynamic transient behavior of the device.

Based on their physical origins, the parasitic device capacitances can be classified into

two major groups: oxide-related capacitances and junction capacitances. First, the

oxide-related capacitances will be considered.

It was shown earlier that the gate electrode overlaps both the source region and the

drain region at the edges.

The two overlap capacitances that arise as a result of this structural

arrangement are called CGD (overlap) and CGS (overlap), respectively.

Assuming that both the source and the drain diffusion regions have the same width W,

the overlap capacitances can be found as

CGS (overlap) C0x . W. LD

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CGD(overlap) C0x * W. LD

Cox = εox / tox

Note that both of these overlap capacitances do not depend on the bias conditions, i.e.,

they are voltage-independent.

Now consider the capacitances which result from the interaction between the gate

voltage and the channel charge.

Since the channel region is connected to the source, the drain, and the substrate, we

can identify three capacitances between the gate and these regions, i.e., Cgs, C d and C

b respectively.

Notice that in reality, the gate-to-channel capacitance is distributed and voltage-

dependent.

Then, the gate-to-source capacitance Cgs is actually the gate-to-channel capacitance

seen between the gate and the source terminals; the gate-to-drain capacitance C ad is

actually the gate-to-channel capacitance seen between the gate and the drain

terminals.

A simplified view of their bias-dependence can be obtained by observing the conditions

in the channel region during cut-off, linear, and saturation modes.

In cut-off mode the surface is not inverted. Consequently, there is no conducting

channel that links the surface to the source and to the drain.

Therefore, the gate-to-source and the gate-to-drain capacitances are both equal to zero:

Cgs=Cgd=0.

The gate-to-substrate capacitance can be approximated by

Cgb = Cox .W.L

In linear-mode operation, the inverted channel extends across the MOSFET, between

the source and the drain This conducting inversion layer on the surface effectively

shields the substrate from the gate electric field; thus, Cgb = 0.

In this case, the distributed gate-to-channel capacitance may be viewed as being shared

equally between the source and the drain, yielding:-

Cgs = Cgd = CX W- L

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9. Difference between pmos and nmos

NMOS PMOS

A NMOS transistor is made up of n-type source

and drain and a p-type substrate.

In a NMOS, carriers are electrons.

When negative voltage is applied to the gate the

electrons in the p-substarte are attracted towards

the gate.

This allows forming an n-type channel between

the source and the drain and a current is carried

by electrons from source to the drain through an

induced n-type channel.

NMOS are relatively faster than PMOS since

electrons travel twice as fast as holes

A PMOS transistor is made up of p-type source

and drain and a n-type substrate.

In PMOS, carriers are hole.

When positive voltage is applied to the gate the

holes in the n-substrate are attracted toward the

gate.

A p-type channel is formed between the source

and the drain with opposite polarities ans a

current is carried by holes from source to the

drain through an induced p-type channel.

PMOS are slower than NMOS

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10. Explain architecture of CPLD XC-9500 (jun 11)

CPLD

The basic approach in the construction of a CPLD is illustrated in figure.

As shown, it consists of several PLDs (in general of GAL type) fabricated on a single chip,

with a programmable switch matrix used to connect them together and to the I/O pins.

Moreover, CPLDs normally contain a few additional features, like JTAG support and

interface to other logic standards (1.8 V, 2.5 V, 5 V, etc.).

Regarding figure, as an example we can mention the Xilinx XC9500 CPLD. It consists of n

PLDs, each resembling a 36V18 GAL device (therefore similar to the 16V8 architecture of

figure A3, but with 36 inputs and 18 outputs, instead of 16 inputs and 8 outputs, thus

with 18 Macrocells each), where n = 2, 4, 6, 8, 12, or 16.

Several companies manufacture CPLDs, like Altera, Xilinx, Lattice, Atmel, Cypress, etc.

Xc 9500 Input/output-Block Architecture

• The structure of the XC9500 I/O block (IOB) is shown in Figure.

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• There are seven choices of output-enable signals for the three state driver buffers. It can

be always on, always off, controlled by the "product term PTOE from the corresponding macro

cell, or controlled by any of up to four global output enables. The global output enables are

selectable as active high or active-mw versions of the external GTS pins.

The XC9500’s IOB is a good example of an important trend in CPLD and FPGA I/O

architectures—providing many “analog” controls in addition to "logic” ones like output

enables. Three different analog controls are provided.

Slew-rate control. The rise and fall time of the output signals can be set to be fast or

slow. The fast setting provides the fastest possible propagation deGyrwhile the slow

setting helps to control transmission-line ringing and system noise at the expense of a

small additional delay.

Pull-up resistor. When enabled, the pull-up resistor prevents output pins from floating

as the CEI n is pmvf.re-d-up. This is useful if the outputs are used to drive active-low

enable inputs of other logic that is not supposed to be enabled during power up.

User-programmable ground. This feature actually reallocates an I/O pin to be a ground

pin, not a signal pm at all. This is useful in high-speed, high-slew-rate applications. Extra

ground pins are needed(toli5utte the high -dynamic currents that flow when multiple

outputs switch simultaneously.

In addition to these features, the XC9500 family provides compatibility with both 5*V

and 3.3-V external devices. The input buffer and the internal logic pin from a 5-V power

supply (Vout)* Depending on the operating voltage of external devices, the output

driver uses either a 5-V or a 3.3-V supply (Vcao). Notice that the pull-up resistor pulls to

the I/O supply voltage, Vdd diodes D1 and D2 are used to clamp voltages above or

below ground that can occur due to transmission-line ringing.

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11. FPGA architecture

Field Programmable Gate Array (FPGA) devices were introduced by Xilinx in the mid-1980s.

They differ from CPLDs in architecture, storage technology, number of built-in features, and

cost, and are aimed at the implementation of high performance, large-size circuits.

The basic architecture of an FPGA is illustrated in figure.

It consists of a matrix of CLBs (Configurable Logic Blocks), interconnected by an array of switch

matrices.

The internal architecture of a CLB (figure) is different from that of a PLD.

First, instead of implementing SOP expressions with AND gates followed by OR gates (like in

SPLDs), its operation is normally based on a LUT (lookup table).

Moreover, in an FPGA the number of flip-flops is much more abundant than in a CPLD, thus

allowing the construction of more sophisticated sequential circuits.

Besides JTAG support and interface to diverse logic levels, other additional features are also

included in FPGA chips, like SRAM memory, clock multiplication (PLL or DLL).

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Another fundamental difference between an FPGA and a CPLD refers to the storage of the

interconnects.

While CPLDs are non-volatile (that is. they make use of antifuse, EEPROM. Flash, etc.), most

FPGAs use SRAM, and are therefore volatile.

This approach saves space and lowers the cost of the chip because FPGAs present a very large

number of programmable interconnections, but requires an external ROM.

There are however, non-volatile FPGAs (with antifuse), which might be advantageous when

reprogramming is not necessary.

12. MOSFET OPERATIONS

The electrons enter the structure through source and leave through drain and are

controlled by the gate voltage.

This control by the gate voltage and the subsequent operation of the device is shown in

the following figures:

Case (a) (0 < VGS < Vt)-

For Fig. (a) With a small positive gate voltage the holes-get depleted from the

semiconductor surface and a depletion region is formed.

No channel exists and the drain current is zero.

The depletion region is uniform throughout.

Case (b) (VG = VT)-

From Fig. (b) The gate voltage is increased to a value VT and surface inversion occurs.

This results in the formation of a channel between the source and drain.

Again no current flows as drain bias is kept at a zero potential.

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Case (c) (VGS > VT)-

As drain bias is increased in a small positive value, current conduction takes place as

shown in fig (C) gale voltage is increased beyond threshold voltage.

The drain current is proportion to the applied drain bias and this operating mode of the

MOSFET is known as linear region.

The voltage drop In the channel at the source gate side is constant and at the gate-draln

side has changed due to the application of drain bias.

This results In the decrease in number of carriers from the channel at the gate drain side

and hence the shape of the channel and the depletion region also gets changed.

Below the drain the depletion region starts increasing due to the application of positive

drain.

Case (d) (VG > VT and VD = VDSAT)-

Keeping the gate voltage constant When the drain voltage is increased to a value Vdsat

(Saturation dram voltage), the charge in The channel at drain end reduces to zero as

.shown in Fig (d).

This is known as pinch-off point of the channel.

At this point the MOSFET is said to be operating at the edge of saturation.

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Case (e) (VG > VT and VD > VDSAT)-

Increasing the drain voltage beyond Vdsat, the channel near the drain vanishes and a

depletion regioo is formed and is shown in Fig. (e).

The increased voltage drop appears at The channel end and a high electric field exist

between the channel end and the drain.

Though no channel exists in this region (between channel end and drain) the electrons

entering the shortened channel from the source are steered by this high electric field

into the drain and the drain current increases but very slowly.

The operating region of the MOSFET is known as saturation mode as further increase in

drain voltage does not increase the drain current and the drain current is said to

saturate.

Surface inversion

As a result of the increasing surface potential, due lo increase in positive gate bias, The

downward bending of the energy bands will increase as well.

The mid-gap energy level E, becomes smaller than the Fermi level Efp on the surface,

which means that the substrate semiconductor in this region becomes n-type.

Within (his thin layer, the electron density is larger than the majority hole density, since

the positive gate potential attracts additional minority carriers (electrons) from the bulk

substrate to the surface.

The n-type region created near the surface by the positive gate bias is called the

inversion layer, and this condition is called surface inversion.

This thin inversion layer on the surface with a large mobile electron concentration can

be utilized for conducting current between two terminals of the MOS transistor.

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The source and substrate are at ground potential.

The drain to source voltage is initially zero.

If a positive voltage is applied to the gate, and electric field Is established which is

directed perpendicular through the oxide, The field will induce negative charges

(minority carries in p-type substrate) near the semiconductor surface.

Since the p-type substrate contain very few electrons, the surface charges are the

electrons obtained from the source and drain and thus an inversion layer is formed.

This inversion layer is formed only when certain gate voltage is applied.

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This value of gate voltage at which inversion of semiconductor surface takes place is

known as threshold voltage. Vt.

As gate voltage (Vgs) increases beyond VT the charges in the inversion layer increase

and the channel conductivity increases.

When a positive potential is applied between the drain and the source (Vos), a current is

produced in the channel between source and drain.

The drain current is enhanced by the positive gate voltage and so the device is known as

enhancement type MOSFET.

The band diagram, of the MOS structure under the gate at surface inversion is shown in

Fig.

The intrinsic level bends a total of 2 ΦF at inversion, where is the fermi potential.

The surface is said to be inverted when the density of mobile electrons on the surface

becomes equal to the density of holes in the bulk (p-type) substrate.

This condition requires that the surface potential has the same magnitude, but of

reverse polarity, as the bulk Fermi potential Φ,f.

Once the surface is inverted, any further' increase in the gate voltage leads to an

increase of mobile electron concentration on the surface, but not to an increase of the

depletion depth.

Thus, the depletion region depth achieved at the onset of surface inversion is also equal

to the maximum depletion depth, Xdm, which remains constant for higher gate voltage.

Using the inversion condition = - Φ,f, the maximum depletion region depth at the onset

of surface inversion can be found from xd as follows

13. CHANNEL HOT-ELECTRON (CHE) EFFECT:

Advances in VLSI fabrication technologies are primarily based on the reduction of device

dimensions, such as the channel length(L), the junction depth (xd), and the gate oxide

thickness (tox), without proportional scaling of the power supply voltage (constant-voltage

scaling). This decrease in critical device dimensions to submicron ranges, accompanied by

increasing substrate doping densities, results in a significant increase of the horizontal and

vertical electric fields in the channel region.

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Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may,

however, be injected into the gate oxide, and cause permanent changes in the oxide interface

charge distribution, degrading the current-voltage characteristics of the MOSFET

Since the likelihood of hot-carrier induced degradation increases with shrinking device

dimensions, this problem was identified as one of the important factors that may impose strict

limitations on maximum achievable device densities in VLSI Circuits.

The channel hot-electron (CHE) effect is caused by electrons flowing in the channel

region, from the source to the drain. This effect is more pronounced at large drain-to source

voltages, at which the lateral electric field in the drain end of the channel accelerates the

electrons. The electrons arriving at the Si-SiO2 interface with enough kinetic energy to

surmount the surface potential barrier are injected into the oxide. Electrons and holes

generated by impact ionization also contribute to the charge injection. Note that the channel

hot-electron current and the subsequent damage in the gate oxide are localized near the drain

junction.

The hot-carrier induced damage in nMOS transistors has been found to result in either trapping

of carriers on defect sites in the oxide or the creation of interface states at the silicon-oxide

interface, or both. The damage caused by hot-carrier injection affects the transistor

characteristics by causing degradation in transconductance, a shift in the threshold voltage, and

a general decrease in the drain current capability. This performance degradation in the devices

leads to the degradation of circuit performance over time.

14. Noise Immunity and Noise Margins

To illustrate the effect of noise on the circuit reliability, we consider the circuit consisting of

three cascaded inverters, as shown in Fig.

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Assume that all inverters are identical, and that the input voltage of the first inverter is

equal to VOH, i.e., a logic "1."

By definition, the output voltage of the first inverter will be equal to VOL' corresponding

to a logic "0" level. Now, this output signal is being transmitted to the next inverter

input via an interconnect, which could be a metal or polysilicon line connecting the two

gates.

Since on-chip interconnects are generally prone to signal noise, the output signal of the

first inverter will be perturbed during transmission. Consequently, the voltage level at

the input of the second inverter will be either larger or smaller than VOL.

If the input voltage of the second inverter is smaller than VOL' this signal will be

interpreted correctly as a logic "0" input by the second inverter. On the other hand, if

the input voltage becomes larger than VIL as a result of noise, then it may not be

interpreted correctly by the inverter.

Thus, we conclude that VIL is the maximum allowable voltage at the input of the second

inverter, which is low enough to ensure a logic "1" output.

Now consider the signal transmission from the output of the second inverter to the

input of the third inverter, assuming that the second inverter produces an output

voltage level of VOH.

As in the previous case, this output signal will be perturbed because of noise

interference, and the voltage level at the input of the third inverter will be different

from VOH.

If the input voltage of the third inverter is larger than VOW, this signal will be interpreted

correctly as a logic "1 " input by the third inverter. If the voltage level drops below VIH

due to noise, however, the input cannot be interpreted as a logic "1."

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Consequently, VIH is the minimum allowable voltage at the input of the third inverter

which is high enough to ensure a logic "0" output.

These observations lead to the definition of noise tolerances for digital circuits, called

noise margins and denoted by NM. The noise immunity of the circuit increases with NM.

Two noise margins will be defined: the noise margin for low signal levels (NML) and the

noise margin for high signal levels (NMH).

NML = VIL - VOL NMH = VOH –VIH

Figure shows a graphical illustration of the noise margins.

In an ideal inverter NMH = NML = VDD/2.

The significance of the noise margin is that an unwanted signal of amplitude less than

NM will not alter the logic state.

Thus noise margin are the amount of variation in the signal level that can be allowed

when the signal is transmitted from the output of one inverter to the input of 2nd

inverter.

There is a voltage range between VIL and VIH, corresponding to input voltage values

that may not be processed correctly either as a logic "0" input or as a logic "1" input by

the inverter. This region is called the uncertain region or, alternatively, the transition

region.

The noise margins also help absorb parameter variations that occur between individual

logic gates.

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15. Modeling styles in VHDL

Digital systems can be represented at different levels of abstraction. Depending on the levels of abstraction they are divided into different modeling styles. 1)Behavioral modeling 2)Dataflow modeling 3)structural modeling

Behavioral Modeling:

The highest level of abstraction is the behavioral level that describes a system in terms

of what it does or how it behaves rather than in terms of its components and

interconnections between them.

Hence we can say that it defines the circuit in terms of a textual language rather than a

schematic of international symbols.

It specifies the behavior of an entity as a set of statements that is executed sequentially

in the specified order.

It describes the system in terms of its architectural features.

The functional or algorithmic aspects of a design are expressed in sequential VHDL

process.

The concept of time may be expressed precisely rather with actual delays between

related events such as the propagation delays within gates or wires.

Example of 2:4 decoder using case statement Library IEEE; Use IEEE.std_logic_1164.all; Entity dec_24 is Port sel:in bit_vector(1downto0); Y :out bit_vector(3downto0); End dec_24; Architecture behave_dec is Process(sel) Begin

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Case sel is When”00”=>Y<=”1110”; When”01”=>Y<=”1101”; When”10”=>y<=”1011: When “11”=>y<=”0111” When others=>Y<=”1111” End case; End process; End behave_dec;

Dataflow Modeling:

A dataflow model specifies the functionality of the entity without explicitly specifying its

structure.

In this level of abstraction circuit is described in terms of how data moves through the

system.

The operation is defines in terms of a collection of data transformations expressed as

concurrent signal assignment statements or block statements.

Each of the statements can be activated when any of its input signals changes its values.

The built operation used in this are AND, OR, XOR, NOR etc.

example Entity and_gate is Port (A,B : in BIT ; __ inputs Y : out BIT); __ outputs And_gate; Srchitecture and2_gate of and_gate is Begin Y<=A and B after 5ns; End and2_gate; The statement 5ns is optional it introduces 5ns delay between input and output

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Structural Modeling:

A digital system is a set of interconnected components and rather than focusing on what

each component does, we are concerned with simply describing how components are

connected.

Behavioral model of each component are already assumed to exist in the local working

directory or in the library.

Such a description is known as structural model.

Such models may describe only the structure of a system without regard to the

operation of the individual component.

It facilitates the use of hierarchy and abstraction in modeling the complex digital system.

16. Architecture of VHDL

Architecture contains only concurrent statements. It specifies behaviour, functionality interconnection or relationship or relationship between inputs and outputs .An architecture body using any of the following modelling styles the internal details of entity. 1)As a set of concurrent assignment statements(to represent dataflow) 2)As a set of interconnected components (to represent dataflow) 3)As a set of sequential components (to represent structures) 4)As any combination of above three. The syntax for architecture is given below. ARCHITECTURE architecture_name OF entity_name Declarations BEGIN Concurrent statements; END architecture_name; To design any system, first you have to write the entity .In the architecture, you write Architecture_name for the entity. In detection part types , signals , constants,function Definitions, procedure definations,component definations etc.can be declared. The Variables can also be declared here. VHDL variables are similar to signals, except that they usually do not have physical significane in a circuit. A variable declaration is similar to a signal declaration ,except that the ‘variables’ keywordis used as shown below.

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VARIABLE variable_names : VARIABLE_TYPE; Example ARCHITECTURE gate OF or_gate is BEGIN PROCESS (a,b) BEGIN If a=’0’ and b= ‘0’ then c<=’0’; else c<=’1’; end if; END PROCESS; END gate; Archicture Bodies There are three types of architecture bodies as 1)Behavioural 2)Dataflow 3)Structural Behavior:

It is the high description of the design which contains set of assignment statements

In the logic optimization is not considered. The behaviour code of any may not be synthesizable as some of non-synthesizable construct may be used in program.

ARCHITECTURE gate OF or_gate IS BEGIN If a=’0’ and b=’0’ then c<=’0’; else c<=’1’; end if END process; END GATE;

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Here by reading like English statement you can conclude that when both inputs are low(a,) then the output c is low otherwise if one of the inputs is nonzero then output is Equal to high in this way it shows only functionality Data Flow:

In this modeling styles, the flow of data through the entity is expressed primarily using concurrent signal assignment statements.

The dataflow model for the or_gate is described

Using a signal concurrent signal assignment statement .in a signal assignment statement

The symbol<= implies an assignment of a value of signal.

The value of the expression the right-hand-side of the statements computed and is assigned to the signal on the Left-hand-side called a target signal.

A concurrent signal assignment is executed only when a signal in the expression on the right-hand-side have an event on it, that is, the value of the signal changes. In signal statement you can use after clause to specify the delay. E.g c<=aor b after 4ns.

It means signal is scheduled to get new value after 4ns

The after clause may be used to generate a clock signal. Example ARCHICTECTURE gate OF or_gate IS BEGIN C<=a or b ; END gate; This type of architecture body has following features

a) Design hierarchy b) Components for libraries are connected c) Each components is stimulated separately In the structural modeling an entity modeling an entity is described as a set of interconnection. Example: ARCHITECTURE is gate OF or_gate is COMPONENT or_gate PORT (x,y) IN STD_LOGIC; Z STD_LOGIC; END COMPONENT;

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BEGIN U1 : or_gate PORT HAP(X=> a, y=>b, z=>c); The name of the architecture body is gate. The entity for or_gate specifies the surface port; for the architecture body. The architecture body is composed of two parts: the declarative part(before the keyword begin) and the statement parts (after the key word begin) . the component may be either be predefined components in library or they may later be bound to other components in a library. The declared components instantiated in the statement UI is the component label for this component instantiation x is connected to signal a y is connected to signal b, z is connected to c in or_gate(entity) portmap.Note that in that case in signal the port map of the component instantiation and the port signals in the components declaration are in a design library Syntax CONFIGURATION configuration name OF entity name IS FOR architecture_name FOR instantiation : component name Use library name : entity_name; END for; END for; END configuration_name; associated by position. A component Configuration It is used to select the particular architecture to entity from many architecture and to bind components used to represent structure in that architecture body, to entities to represent entity architecture pair or by a configuration, which reside

17. Ion implantation

It is a process by which energetic impurity atoms can be introduced into a single crystal silicon

substrate. This method is used to deliver a wide range of doses i.e. from 1011 to 1017 ions/cm2.

Here the dopant atoms are vaporized, accelerated and directed at a silicon substrate. They

enter the crystal lattice, collide with Si atoms and gradually lose energy. Finally they come to

rest at some depth within the lattice.

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The basic requirement is to deliver a beam of ions of a particular type and energy to the silicon

wafer. There is a high voltage enclosure containing a gas source.

The gas is used as carrier to carry ions to be implemented. Usually nitrogen is used as a carrier

gas. The carrier gas is fed into the ion source where a heated filament causes the molecules to

break up into charged fragments.

A voltage of about 20kV causes the ions to move out of the ion source into the analyzer. The

pressure is maintained so as to minimize the scattering of ions by gas molecules. The magnetic

field is chosen such that only ions with the desired charge to mass ratio can travel through

without being blocked by the analyzer walls. The ion beam is then deflected vertically and

horizontally using X and Y planes as per the requirements.

ADVANTAGES:

1. Speed at which ions strike the Si wafer can be controlled

2. It provides precise control over the doping

3. Ion beam can be measured

DISADVANTAGES

1. A high voltage is required

2. Lattice damage occurs because of the collision between the ions and the lattice atoms

3. This method is expensive

18. Thermal Oxidation -

Thermal oxidation has been a principal technique in silicon IC technology. Schematic cross

section of a resistance heated oxidation furnace is shown in Fig.

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The reactor for thermal oxidation consists of a resistance heated furnace, a cylindrical

fused quartz tube and a source of pure dry oxygen or water vapour.

The loading end of the furnace tube enters into a vertical flow hood where a flow of

filtered air is maintained.

This reduces dust and particulate matter in the air surrounding the wafers and thus

protects the waters from contamination at the time of loading.

A cylindrical fused quartz tube contains the wafers which are held vertically in a slotted

quarts boat and are exposed to a source of oxygen.

Silicon is usually oxidized at a high temperature of 900°C to 1200°C with a gas flow rate

of 1 cm/s. Microprocessors are used to control the flow rate, mounting of wafers and

the system temperature.

The chemical reactions for oxidation of silicon are :

Si (s) + O2 SiO2 (s) in oxygen

Si (s) + H2O SiO2 (s) + 2 H2 in water-vapour.

SiO2 formation involves sharing of valence electrons between silicon and oxygen

(covalent bond).

SiO2 grows in both the directions upwards as well as downward approximately with

same thickness.

Thermal oxidation ensures that the Si - SiO2 interface has low-charge density levels.

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The densities and molecular weights of silicon and silicon dioxide can be used to obtain

the relation between the thickness of oxide and the silicon consumed in the process of

formation of oxide.

19. DIFFUSION

Diffusion is the process of introducing controlled amounts of dopants into semiconduc-tors.

Using diffusion conductivity of silicon is being altered by producing either n-type or p-type region.

Selectively producing u-type and p-type regions require that diffusion to be carried out at an elevated temperature and by placing the dopant atoms on the surface of the semiconductor. So we have a high concentration of the dopant at the surface and it gradually decreases as one move inside the semiconductor.

Diffusion is generally carried out in a furnace similar to that used in thermal placing the wafers inside it and passing an inert gas that contains the desired dopant through it at an increased temperature in the range of 800 — 1200*C.

p-type semiconductor is usually obtained by diffusion of solid, liquid or gaseous source of boron into silicon and n-type semiconductor by diffusion of solid, liquid or gaseous source of arsenic or phosphorous into silicon.

Diffusion Mechanics

At elevated temperatures point defects like vacancies or interstitials are generated tr. the crystal lattice.

Diffusion occurs by the movement of dopant atoms through these vacancies. The migration of the dopant atom occurs when the host (silicon) atom leave the Lattice site by gaining high energy at high temperatures as shown in Fig.

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If the migrating atom is a host atom, the diffusion is referred to as self-diffusion, if it is an impurity atom the diffusion is called impurity diffusion.

The movement of impurity atom other than oscillating between two lattice sites is produced by diffusing, the vacancy away from the site that the impurity atom had just occupied or the impurity atom has to move to a second vacancy that is the nearest.

This is referred to as diffusion assisted by a double vacancy. An interstitial atom moving from one place to another without occupying a lattice site is known as interstitial diffusion mechanism.

This happens when the interstitial atom is smaller than the host atom and cannot form covalent bonds with silicon.

There is another mechanism in which a self-interstitial atom displaces an impurity atom which in turn becomes an interstitial atom.

The impurity atom displaces another host atom and the second host atom becomes a self-interstitial. This is known as interstitialcy mechanism.

The common dopants like boron and phosphorus diffuse by vacancy and interstitialcy mechanism with the interstitialcy component dominating most of the times. In arsenic and antimony diffusion takes place mostly by vacancy mechanism.

Diffusion Equation

If F is flux of the number of atoms passing through a unit area in a unit time and C is the dopant concentration per unit volume then

where D is the diffusion constant, dC/dx is the concentration gradient,

Using one-dimensional continuity equations we have

Equation is known as Fick’s diffusion law.

20. Data types in VHDL

All the objects in vhdl can declared using type specification . Vhdl has a wide range of types that

can be used. A type declaration statement is

TYPE type_name is type _mark;

Two main types are

1)scalar

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2)composite

1-scalar data types

Scalar data types describe objects that can hold at most one value at a time. The type itself can

contain multiple values.

1 integer types

2 real types

3 enumerated types

4 physical types

1)Integer types :

a) they are like mathematic integers . An integer types defines a type whose set of values fall

within a specified integer range .

E.g type MUX_bus range 0 to 15;

type W_length is range 31 down to 0;

b) integer is the only predefined integer type that covers the range from -(2^31 -1) to +(2^31-

2)Real types :

a) they are used to declare objects that emulate mathematical real numbers. It has a set of

values in the given range of real numbers.

E.g type real_data is range 0.0 to 35.7;

b) the predefined real data types cover the range -1.0e38 to +1.0e38 and it must provide at

least six decimal digit of precision .

3)Enumerated types :

a) the declaration defines a Set of user defined values consisting of identifiers and character

literals .

E.g : type micro_or is (load, store, add, sub, mul, div);

Hence micro_or is enumerated type and supports the value load , store , add , sub , etc.

type MUL is ( 'U' , '0' , ' 1 ' , 'Z' ) ;

Similarly MUL is an Enumerated type that has set of ordered values 'U' , '0', ' 1', 'Z'. The order in

which values appear in an enumeration type declaration defines their ordering i.e

Store< div is true

Sub > mul is false

E.g

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type two_state is ('0' , '1');

_______

_______

Variable clock : two_state;

_______

Clock : = 0;

C) the predefined enumeration type character bit, Boolean and std_logic type.

1) the values belonging to the type character constitute 191 characters of the ISO 8 bit coded

character set. These values are called character literals and always written between two single

quotes (' ').

E.g 'A' , '_' , ' 3'

The predefined type bit has the literals '0' and '1'.

2) while the Boolean has the literals false or true .

E.g variable e_flag : boolean := true.

3) Type std_logic defined std_logic_1164 of IEEE library is an enumerated type . It is defined as

type std_logic is ('U' , 'X','0','1','Z','W','L','H','_');

'U'= uninitialized ; 'X'=unknown

'0'=logic 0 ; '1'= logic 1

'Z'= high impedance ; 'W '= weak unknown. ' L'= weak logic 0;

'H'= high logic 1

'_' = don't care

4)Physical types :

A physical type contains values that represent measurement of some physical quantity , like

time , length , voltage or current . Values of this type are expressed as integer multiple of a base

unit.

E.g constant set_up : time : = 2ns

type current is range 0 to 1E9

Units

nA nano amps

microA=1000na Micro amps

mA=1000microA Mili amps

Amp =1000mA Amps

end units;

2- Composite Types :

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A composite type represents a collection of values . There are two types :

1 array types.

2 Record types.

An array types represents a collection of values all belonging to a single type ; on the other

hand , a record type represents a collection of values that may belong to different types .

1) Array type :

An object of an array type consists of elements that have same type .

E.g signal A: std_logic_vector (7down to o);

type address_word is array (0to 63) of bit ;

type ROM is array (0 to 125) of data_word ;

2) Record types :

An object of record type is composed of elements of same or different types .

E.g

type sc_type is range 0 to 10

type module is

record

size : integer range 10to150

Critical_dly : time ;

No_inputs : sc_type ;

No_outputs : sc_type ;

end record ;

21. Explain features of VHDL (jun 11)

1-it supports hierarchy.it uses set of components and interconnects them, each component can

also be modeled as a set interconnected sub components.

2- it supports both synchronous and asynchronous timing models.

3-it supports various digital modeling techniques like finite state machine (FSM), algorithmic

description and Boolean expressions.

4-it does not restrict the user to one type of description only and supports three basic different

description styles like structural, data flow and behavioral . These types can be mixed together

to describe the design in VHDL.

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5- it can be used at different complexity levels from single transistor design up to complete

system design .

6- it is a universal modeling language, used for modeling and simulation of electromechanical

hydraulic and other systems.

7- it provides the library of components which can be used directly without writing code for it

to make the description simpler .

8- Concurrency, timing and clocking can be modeled in this language , propagation delay , min

max delays , set up and hold time can be simulated easily .

9-it facilitates device independent design and portability .

10- it is not technology specific I.e it can work with Xilinx , Lattice , Atmel series of CPLDs or

FPGAs.

11- it is not a case sensitive language.

12-test benches can be written using the same language to test the designs.

22. What photolithography steps are necessary to prepare silicon wafer for etching?

Photolithography is the process of transferring geometric shapes on a mask to the surface of a

silicon wafer. The steps involved in the photolithography process are:-

1.wafer cleaning;

2.barrier layer formation;

3.photoresist application;

4.soft baking;

5.mask alignment;

6.exposure and development;and

7.Hard-baking.

Wafer cleaning, Barrier layer formation and Photoresist application

In the first step, the wafers are chemically cleaned to remove particulate matter on the surface as well as any traces of organic, ionic, and metallic impurities.

After cleaning, silicon dioxide, which serves as a barrier layer, is deposited on the surface of the wafer. After the formation of the SiO2 layer, photoresist is applied to the surface of the wafer.

High-speed centrifugal whirling of silicon wafers is the standard method for applying photo resist coatings in IC manufacturing. This technique, known as “Spin Coating,”

Produces a thin uniform layer of photo resist on the wafer surface.

Positive and Negative Photoresist

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There are two types of photoresist: positive and negative.

For positive resists, the resist is exposed with UV light wherever the underlying material is to be removed.

In these resists, exposure to the UV light changes the chemical structure of the resist so that it becomes more soluble in the developer.

The exposed resist is then washed away by the developer solution, leaving windows of the bare underlying material. In other words, “whatever shows, goes.”The mask,

Therefore, contains an exact copy of the pattern which is to remain on the wafer.

Negative resists behave in the opposite manner.

Exposure to the UV light causes the negative resist to become polymerized, and more difficult to dissolve.

Therefore, the negative resist remains on the surface wherever it is exposed, and the developer solution removes only the unexposed portions.

Masks used for the negative photoresists, therefore, contain the inverse(or photographic “negative”) of the pattern to be transferred.

The figure below shows the pattern differences generated from the use of positive and negative resist.

Negative resists were popular in the early history of integrated circuit processing, but positive resist gradually became more widely used since they offer better process controllability for small geometry features.

Positive resists are now the dominant type of resist used in VLSI fabrication processes.

Soft-Baking

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Soft-baking is the step during which almost all of the solvents are removed from the photoresist

coating.

Soft-baking plays a very critical role in photo-imaging.

Oversoft-baking will degrade the photosensitivity of resists by either reducing the developer solubility or actually destroying a portion of the sensitizer.

Mask Alignment and Exposure

One of the most important steps n the photolithography process is mask alignment.

A mask or “photomask” is a square glass plate with a patterned emulsion of metal film on one side.

The mask is aligned with the wafer, so that the pattern can be transferred onto the wafer surface.

Each mask after the first one must be aligned to the previous pattern.

Once the mask has been accurately aligned with the pattern on the wafer’s surface, the photoresist is exposed through the pattern on the mask with a high intensity ultraviolet light.

There are three primary exposure methods:contact,proximity, and projection. They are shown in figure below.

Contact Printing

In contact printing, the resist-coated silicon wafer is brought into physical contact with the glass photomask.

The wafer is held on vacuum chuck, and the whole assembly rises until the wafer and mask contact each other.

The photoresist is exposed with UV light while the wafer is in contact position with the mask.

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Because of the contact between the resist and mask, very high resolution is possible in contact printing(e.g. 1-micron features in 0.5 microns of positive resist).

The problem with contact printing is that debris, trapped between the resist and the mask,

Can damage the mask and cause defects in the pattern.

Proximity Printing

The proximity exposure method is similar to contact printing except that a small gap, 10 to 25 microns wide, is maintained between the wafer and mask during exposure.

This gap minimizes mask damage .Approximately 2 to 4 micron resolution is possible with proximity printing.

Projection Printing

Projection printing, avoids mask damage entirely.

An image of the patterns on the mask is projected onto the resist-coated wafer, which is many centimeter’s away.

In order to achieve high resolution, only a small portion of the mask is imaged.

This small image field is scanned or stepped over the surface of the wafer.

Projection printers that step the mask image over the wafer surface are called step-and-repeat systems.

Step-and-repeat projection printers are capable of approximately 1-micron resolution.

Development

One of the last steps in the photolithographic process is development.

The figure below shows response curves for negative and positive resist after exposure and development.

At low exposure energies, the negative resist remains completely soluble in the developer solution.

As the exposure is increased above the threshold energy Et, more of the resist film remains after development.

At exposures two or three times the threshold energy, very little of the resist film is dissolved.

For positive resist, the resist solubility in its developer is finite even at zero exposure energy.

The solubility gradually increases until, at some threshold, it becomes completely soluble.

These curves are affected by all the resist processing variables: initial resist thickness, developer chemistry, developing time, and others.

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Hard Baking

It is the final step in the photolithographic process.

This step is necessary to harden the photoresist and improve adhesion of the photoresist to the wafer surface.

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Layout

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