Sessional I, VLSI Design, 12th

Sept, 2014 / Vth

Sem B.E (E&C) Section: A, B, C, D Time: 1 Hour Note: All questions are compulsory and assume any missing data suitably Marks: 20

1. (a) Show that (W/L)P= 2.5(W/L)n for symmetric CMOS inverter. State your assumptions. (CO4)

(b) In CMOS inverter, if VDD = 1.5V, Vtn =| Vtp |= 0.4V, Kn = 200 A/V2 and Kp = 100 A/V

2: The peak

current of 35A occurs at 0.6V. Find (i) (W/L)n (ii) (W/L)p (CO4) [1+3]

2. Explain the following: (i) pinch-off voltage (CO3) (ii) MOS transistor figure of merit (CO3)

(iii) Diffusion (CO8) (iv) Thick oxide patterning (CO8) [4]

3. Give optimal transistor-level schematic with aspect ratio for following functions using depletion NMOS

and CMOS gate based approach : (i) Three variable majority function (ii) CABF (CO5) [4]

4. An enhancement type NMOS transistor M2 with Vtn = 0.7V has its source terminal grounded and a 2V

DC is applied to the drain. A gate voltage VG is applied through a voltage divider network and pass

transistor. Find the region of operation of the transistor M2. If the NMOS device shown in figure has nCox

= 100 A/V2, W = 10 m, and L = 1 m, find the value of source current for M2. (CO3) [4]

5. Choose the correct answer/ Give objective answer [4]

1. .. type of MOSFET is normally OFF device. (CO3)

2. . device is slower (NMOS/PMOS) (CO3)

3. For an inverter, the point at which Vout = Vin, is called . (CO4) .

4. The number of transmission gates required to design 4:1 MUX is (CO5)

5. For the below shown case, specify the Zpu/Zpd ratio required for NMOS Inverter 2 driven by NMOS

Inverter1 through MOS transistor switch for proper inverter behavior. . (CO4)

6. The Depletion MOSFET differs from an Enhancement MOSFET, in the presence of . (CO3)

[a] pn bulk diode [b]Insulated gate [c]thin oxide [d] channel implant

7. A circuit designer intending to operate a MOSFET in saturation is considering the effect of changing the

device dimensions and operating voltages on the drain current ID. Specifically, by what factor does ID change in each of the following cases? (neglecting channel length effect) (CO3)

(i) The VGS-VT is doubled (ii) The drain-to-source voltage is doubled. ..

*********

Scheme of Evaluation

1(a) For symmetric CMOS inverter, the resistance of n-type and p-type need to be equal. Considering Idsn= Isdp, it can be shown that (W/L)P= 2.5(W/L)n . mark Assumptions made: n = 2.5 p and Vtn = |Vtp| . mark

(b) In CMOS inverter, given that VDD = 1.5 V, Vtn = | Vtp | = 0.4 V, Kn = 200 A/V2 and Kp = 100 A/V

2.

The peak current of 35A occurs at 0.6V.

CMOS inverter circuit diagram

Vgsn = 0.6 V, | Vgsp | = 0.9 V

Vgsn - Vthn = 0.2 V and |Vgsp| - |Vthp |= 0.5 V . 1 mark

=

2

( )

2 i.e., 35 A =

200E6

2

Wn

Ln(0.2)2

= . . 1 mark

=

2

(|Vgsp| |Vthp |)2 i.e., 35 A =

100E6

2

Wp

Lp(0.5)2

= . . 1 mark

2. (i) pinch-off voltage : The physical pinch-off of the channel takes place when Vds = Vp = Vgs Vth Fig showing the channel pinch-off is desirable

(ii) MOS transistor figure of merit is defined as =

=2

( ) =1

is the measure of speed of operation of MOSFET(for digital circuits). (iii) Diffusion: explanation

(iv) Thick oxide patterning : explanation with fig.

[1x4= 4 marks] 3. (i) Three variable majority function: F = ab + bc + ca

i.e., F = ab + bc + ca i.e., As F(L) = ab + bc + ca , it is convenient to implement F and then implement F, as complemented variable inputs are not required.

(a) NMOS implementation (b) CMOS implementation of F [1+1=2 marks] (Note : other correct implementations, if any may be considered, Deduct mark if function F is

implemnted directly)

3. (ii) CABF

(a) NMOS implementation (b) CMOS implementation of F [1+1=2 marks]

4. Given that nCox = 100 A/V2, W = 10 m, and L = 1 m,

Vtn = 0.7 V, VG = 2 V - 0.7 V = 1.3V [1]

Vgs2 - Vthn = 1.3 V 0.7 V = 0.6 V

Vds2 = 2 V and Vds2 > Vgs2 - Vthn

M2 operates in saturation [1]

Id2 = Is2 =Kn

2

Wn

Ln(Vgsn Vthn)

2 [1]

Id2 = Is2 =100E 6

2(

10

1) (0.6)2

= [1]

5.

1. Enhancement type of MOSFET

2. PMOS device

3. Inverter threshold or switching threshold voltage

4. 6 or 8 transmission gates

5. Zpu/Zpd ratio for NMOS Inverter 2 is 4:1

6. [d] channel implant

7. (i) When Vgs-Vth is doubled IDS increases by 4 times

(ii) wHEN drain-to-source voltage is doubled IDS is not affected (neglecting channel length effect) [0.5 X 8 = 4]

***