VLSI-SEMINARS2

8/9/2019 VLSI-SEMINARS2

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MANUFACTURINGTEST

PRINCIPLES(VLSI UNIT-5)

Prepared byTamilarasu T

[email protected] ECE(2010 batch)

SSM College Of Engineering


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INTRODUCTION Faults should be detected during

manufacturing level itself.

Digital circuits classification:

1. Combinational circuits

2. Sequential circuits

Here we are going to discuss differentmethods of testing.


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TESTING COMBINATIONAL

CIRCUITS

Present output depends on present

input only. For testing of n input circuits, 2^n

combinations are needed.

For large values of n it seems to bedifficult.


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COMBINATIONAL LOGIC:


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TESTING SEQUENTIALCIRCUITS:

Present output not only depends on

present input but also depends on pastinput & output.

Due to feedback paths, testing is some

what complicated.


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SEQUENTIAL LOGIC:


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FAULT MODEL:

Models bridge the gap between the physicalreality and mathematical abstraction.

DEFECTS:

Unintended differences between theimplemented hardware & its intended design

ERROR:

A wrong output signal produced by adefective system is called errorFAULTS A representation of defects is called faults.


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TYPICAL DEFECTS IN VLSI:

Age defects Material defects

Surface impurities

Dielectric breakdown


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STUCK AT FAULTS

This fault is modeled by assigningvalues (0 or 1) to a signal line in thecircuit

These faults can be simultaneouslypresents in the circuits

A circuit with n combinations will have(3^n)-1 possible stuck linecombinations


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TYPES OF STUCK AT FAULTS

1.

Stuck-at-1 (s-a-1)2. Stuck-at-0 (s-a-0)


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S-A-0

This fault is modeled by assigning 0 toa signal line in the circuit.


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S-A-1

This fault is modeled by assigning 1 to asignal line in the circuit.


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O.C & S.C FAULTS

These faults are due to physical faultswhich in turn cause physical change inthe circuit


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REASONS FOR S.C FAULTS:

Under etching

Spiking Diffusion shorts

Contact opens

Gate to source/drain short Mask misalignment


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REASONS FOR O.C FAULTS:

A bad contact

Metal missing Poor wire bonding

Metal migration


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ILLUSTRATION FOR O.C CMOS-NOR


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QUESTIONS: A circuit with n combinations will

have .. possible stuck linecombinations.

Define faults.

Reasons for o.c faults.

Define stuck at faults.


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CONT. & OBS.:CONTROLABILITY Difficulty of setting particular logic signal to a

zero or one. RANGE: one to infinite

OBSERVABILITY Difficulty of observing particular logic signal to a

zero or one.

RANGE: zero to infinite


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SCOAP algorithm Sandia Controllability/Observability AnalysisProgram.

Proposed by Goldstein. The 1-Controllability is the probability of a

signal value on line being set to 1 by arandom vector.

The 0-Controllability is the probability of asignal value on line being set to 0 by arandom vector.


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NUMERICAL MEASURES for

SCOAP:1. CC0(n)

2.

CC1(n)3. CO(n)

4. SC0(n)

5. SC1(n)6. SO(n)


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Different Cases of

controllabilityOutput is controlled by OUTPUT COTROLLABILITY

Setting one value Min(input controllabilities) +1

Setting all values sum(input controllabilities) +1

Multiple inputs min(all input controllabilities) +1


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SCOAP controllability AND gate

a b Z

0 0 0

0 1 0

1 0 0

1 1 1


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SCOAP controllability OR gate

a b Z

0 0 0

0 1 1

1 0 1

1 1 1


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SCOAP

controllability NOR gate

a b Z

0 0 1

0 1 0

1 0 0

1 1 0


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SCOAP

controllability NAND gate

a b Z

0 0 1

0 1 1

1 0 1

1 1 0


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SCOAP controllability XOR gate

a b Z

0 0 0

0 1 1

1 0 1

1 1 0


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SCOAP controllability X-NOR gate

a b Z

0 0 1

0 1 0

1 0 0

1 1 1


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SCOAP controllability NOT gate

a Z

1 0

0 1


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OBSVERABILITYLOGIC GATES OBSERVABILITY CALCULATION

OR co(a)=co(z)+cc0(b)+1

co(b)=co(z)+cc0(a)+1 AND co(a)=co(z)+cc1(b)+1

co(b)=co(z)+cc1(a)+1

XOR co(a)=co(z)+min(cc0(b),cc1(b))+1

co(a)=co(z)+min(cc0(b),cc1(b))+1


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OBSVERABILITY

LOGIC GATES OBSERVABILITY CALCULATION

NOR co(a)=co(z)+cc0(b)+1


NAND co(a)=co(z)+cc1(b)+1


XOR co(a)=co(z)+min(cc0(b),cc1(b))+1

co(a)=co(z)+min(cc0(b),cc1(b))+1


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OBSVERABILITY

LOGIC GATE OBSERVABILITY CALCULATION

NOT co(a)=co(z)+1


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QUESTIONS Define observability & controllability.

SCOAP controllability of NAND gate.


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AUTOMATIC TEST PATTERN

GENERATION ATPG algorithms inject a fault into a ckt.

Uses a variety of mechanisms to activate the

fault. Non controlling values is given for other

inputs

Its to view the fault propagation. Finally detect the fault by comparing with

expected output.


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DD--calculuscalculusATPG algorithm.

Developed by Rother.

The symbol D(detect) indicates thevalue of fault.

The node values are defined by1,0,X,D,Dbar,


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Rouths algebra:SYMBOL MEANING GOOD MACHINE FAILING

MACHINE

D (1/0) 1 0

Dbar (1/0) 0 1

0 (0/0) 0 0

1 (1/1) 1 1

X (X/X) X X


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DD--calculus for AND gatecalculus for AND gate AND 0 1 X D Dbar

0 0 0 0 0 0

1 0 1 X D Dbar

X 0 X X X X

D 0 D X D 0

Dbar 0 Dbar X 0 Dbar


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DD--calculus for OR gatecalculus for OR gateOR 1 0 X D Dbar

1 1 1 1 1 1

0 1 0 X D Dbar

X 1 X X X X

D 1 D X D 1

Dbar 1 Dbar X 1 Dbar


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DD--calculus for NOT gatecalculus for NOT gateA Abar

0 1

1 0

X X

D Dbar

Dbar D


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PODEM algorithm Path oriented decision making algorithm. Solves the problem of reconvergent. Allows multipath sensitization. Similar to D-calculus major difference is it is

reversible during incorrect decision.

BASIC STEPS1. Objective2. Back trace3. Implication4. D-frontier


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Find using Rouths algebra:

SYMBOL MEANING GOOD MACHINE FAILING

MACHINE

D

0

X


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QUESTIONS:EXPAND THE FOLLOWING:

1. PODEM

2. ATPG

3. D-calculus.


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FAULT SIMULATION

To verify the correctness of the design

It verifies the test

TYPES

1. Serial fault simulation

2. Parallel fault simulation3. Concurrent fault simulation

4. Non deterministic fault simulation


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SERIAL FAULT

SIMULATION

Simulate circuit using true value mode for all

vectors. Primary output values are saved is a file.

Faulty circuits are simulated one by one.

This can be done by inserting faults at line or

node Then output of former & latter are compared


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No. of simulation cycles (Sy)

are given by

Sy = (2N/2)Y+N

= NY+N

=N(Y+1)

=NY (app)N -no.of test vectorsY-no. of nodes


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PARALLEL FAULT

SIMULATION

It uses the bit parallelism of logical operations in adigital computer

It allows simultaneous simulation with identicalconnectivity, but possibly different values

Performance: (W-1) times faster than former one.

W-bits in the machine word size

Here,Sy = (Yn /M)


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CONCURRENT FAULT

SIMULATION

Here simulating whole circuit with faultmodels are avoided

First simulate the good circuit

Then inject fault and re simulate partof circuit that behaves differently


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NON-DETERMINISTICSIMULATION

Previous models are deterministic faultsimulation

Here simulation is done by usingprobabilistic fault simulation

We simulate a subset or sample offaults and extrapolate fault coveragefrom the sample


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DELAY FAULT TESTING

Due to combinational delay in the circuit

Specific delay faults are:

1. Transition faults

2. Gate delay faults

3. Line delay faults4. Path delay faults.


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STASTICAL FAULT ANALYSIS Technique that statistically determines

1. controllabilities,

2. observabilities,

3. detection probabilities &

4.

fault converge from true value ofsimulation.


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FAULT SAMPLING

Subset of faults is randomly picked from theset of all faults

This subset is usually a small fraction of thecomplete faulty set

Faults in sample are simulated & the samplecoverage is used as an estimate of the fault

coverage in the complete fault set Increasing sample value decreases the error

bound


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CONCLUSIONFinding defects at manufacturing level

itself will give us a better result. Using

above techniques faults free circuits canbe obtained at manufacturing level.


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REFERENCEVLSI design by R.Uma.


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