Vlsi Record

8/2/2019 Vlsi Record

1/184

INDEX

EXP NO DATE NAME OF THEEXPERIMENT

PAGENO

MARKS STAFFSIGNATURE

09.01.2011 VERIFICATION OF LOGICGATES

(STUDY EXPERIMENT)

02

1 23.01.2011 ADDERS ANDSUBTRACTORS

08

2 29.01.2011 ENCODER ANDDECODER

57

3 29.01.2011 MULTIPLEXER ANDDEMULTIPLEXER

68

4 06.02.2011 DESIGN OF FLIPFLOPS 80

5 12.02.2011 DESIGN OF SHIFTREGISTERS

99

6 26.02.2011 SYNCHRONOUS ANDASYNCHRONOUS

COUNTER

114

7 06.03.2011 DESIGN OF MOORE ANDMEALY FSM

123

8 06.03.2011 STATIC AND ROLLINGDISPLAY 132

9 12.03.2011 FREQUENCY DIVIDER 137

10 12.03.2011 DESIGN OF ARITHMETICAND LOGIC UNIT

141

11 20.03.2011 BARREL SHIFTER 147

12 26.03.2011 TRAFFIC LIGHTCONTROLLER

151

13 02.04.2011 DESIGN OF MEMORIES 159

14 02.04.2011 DESIGN OF MAC UNIT 166

15 09.04.2011 SWITCH LEVEL DESIGN 170

Sathyabama University -Department of VLSI DesignPage 1


2/184

DATE: 09-01-11

VERIFICATION OF LOGIC GATES

AIM:

To develop the source code for logic gates by using VHDL/VERILOG and obtain the simulation, synthesis,place and route and implement into FPGA.

ALGORITHM:

Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.

LOGIC DIAGRAM:

AND GATE: OR GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGIC DIAGRAM TRUTH TABLE:

NOT GATE:

NAND

GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGIC DIAGRAM TRUTH TABLE

NOR GATE: XOR GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGIC DIAGRAM TRUTH TABLE

XNOR GATE:

LOGIC DIAGRAM: TRUTH TABLE:


A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

A B Y=AB

0 0 0

0 1 0

1 0 0

1 1 1

A B Y=(AB)

0 0 1

0 1 11 0 1

1 1 0

A Y=A

0 1

1 0

A B Y=(A+B)

0 0 1

0 1 0

1 0 0

1 1 0

A B

0 0 0

0 1 1

1 0 1

1 1 0

A B

0 0 1

0 1 0

1 0 0

1 1 1


3/184

VHDL SOUCE CODE:

--Design : VERIFICATION OF LOGIC GATES--Description : To implement LOGIC GATES--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logicgates isPort ( a : in std_logic;

b : in std_logic;c : out std_logic_vector(6 downto 0));

end logicgates;

architecture dataflow of logicgates is

beginc(0)


4/184

ARCHITECTURE testbench OF logicgatestest_vhd ISCOMPONENT logicgatesPORT(

a : IN std_logic;b : IN std_logic;c : OUT std_logic_vector(6 downto 0));

END COMPONENT;

SIGNAL a : std_logic := '0';SIGNAL b : std_logic := '0';

SIGNAL c : std_logic_vector(6 downto 0);

BEGIN

uut: logicgates PORT MAP(a => a,b => b,c => c

);

tb : PROCESSBEGIN

a


5/184

Synthesis RTL Schematic:

Synthesis report:

=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : logicgates.ngrTop Level Output File Name : logicgatesOutput Format : NGCOptimization Goal : Speed

Keep Hierarchy : NODesign Statistics# IOs : 9Cell Usage :# BELS : 7# INV : 1

# LUT2 : 6

# IO Buffers : 9# IBUF : 2# OBUF : 7=========================================================================

Device utilization summary:---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 3 out of 3584 0% Number of 4 input LUTs: 6 out of 7168 0% Number of bonded IOBs: 9 out of 97 9%



6/184

=========================================================================TIMING REPORT

Clock Information:------------------No clock signals found in this design

Timing Summary:---------------

Speed Grade: -5

Minimum period: No path foundMinimum input arrival time before clock: No path foundMaximum output required time after clock: No path foundMaximum combinational path delay: 7.985ns

Timing Detail:--------------All values displayed in nanoseconds (ns)

=========================================================================Timing constraint: Default path analysis

Total number of paths / destination ports: 13 / 7-------------------------------------------------------------------------Delay: 7.985ns (Levels of Logic = 3)

Source: a (PAD)Destination: y2 (PAD)

Data Path: a to y2Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 7 0.715 1.201 a_IBUF (a_IBUF)LUT2:I0->O 1 0.479 0.681 y31 (y3_OBUF)OBUF:I->O 4.909 y3_OBUF (y3)

----------------------------------------Total 7.985ns (6.103ns logic, 1.882ns route)(76.4% logic, 23.6% route)

=========================================================================CPU : 11.83 / 12.59 s | Elapsed : 12.00 / 12.00 s

Place and root report:

Constraints file: logicgates.pcf.Loading device for application Rf_Device from file '3s400.nph' in environmentC:/Xilinx.

"logicgates" is an NCD, version 3.1, device xc3s400, package tq144, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)Device speed data version: "ADVANCED 1.35 2005-01-22".Device Utilization Summary:

Number of External IOBs 9 out of 97 9%Number of LOCed IOBs 0 out of 9 0%



7/184

Number of Slices 3 out of 3584 1%Number of SLICEMs 0 out of 1792 0%

Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)

Starting Placer

Phase 1.1Phase 1.1 (Checksum:989697) REAL time: 3 secsPhase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 3 secsPhase 3.2Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secsPhase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 3 secsPhase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 3 secsPhase 6.8.Phase 6.8 (Checksum:98a1bf) REAL time: 3 secs

Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 3 secPhase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secsPhase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 3 secsWriting design to file logicgates.ncdTotal REAL time to Placer completion: 3 secsTotal CPU time to Placer completion: 1 secs

Starting Router

Phase 1: 19 unrouted; REAL time: 3 secs

Phase 2: 19 unrouted; REAL time: 3 secsPhase 3: 0 unrouted; REAL time: 3 secsPhase 4: 0 unrouted; REAL time: 3 secs

Total REAL time to Router completion: 3 secsTotal CPU time to Router completion: 1 secsGenerating "PAR" statistics.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 4 secsTotal CPU time to PAR completion: 2 secsPeak Memory Usage: 74 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file logicgates.ncdPAR done!----------------------------------------------------------------------------------------------------------------------

CONCLUSION:

Thus the outputs of Basic Logic Gates are verified by simulating and synthesizing the VHDL andVERILOG code.



8/184

EXP NO: 01 DATE: 23-01-11

ADDERS AND SUBTRACTORS

AIM:

To develop the source code for adders and subtractors by using VHDL/VERILOG and obtain the simulation &synthesis.

ALGORITM:


BASIC ADDERS & SUBTRACTORS:

HALF ADDER:


VHDL SOURCE CODE:

--Design : HALF ADDER--Description : To implement HALF ADDER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hadd isPort ( a : in std_logic;

b : in std_logic;sum : out std_logic;carry : out std_logic);

end hadd;architecture dataflow of hadd isbeginsum


9/184

end dataflow;

Behavioral Modeling:


entity haddbehavioral isPort ( a : in std_logic;

b : in std_logic;sum : out std_logic;carry : out std_logic);

end haddbehavioral;architecture Behavioral of haddbehavioral isbeginp1:process (a,b)beginsum


10/184

b : in std_logic;z : out std_logic);

end and2;architecture dataflow of and2 isbeginz


11/184

xorx1(s,a,b);anda1(ca,a,b);

endmoduleTEST BENCH(VHDL):

LIBRARY ieee;USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;

ENTITY test_bench_vhd ISEND test_bench_vhd;

ARCHITECTURE behavior OF test_bench_vhd IS

COMPONENT haddPORT(

a : IN std_logic;b : IN std_logic;sum : OUT std_logic;

carry : OUT std_logic);

END COMPONENT;

--InputsSIGNAL a : std_logic := '0';SIGNAL b : std_logic := '0';

--OutputsSIGNAL sum : std_logic;SIGNAL carry : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: hadd PORT MAP(

a => a,b => b,sum => sum,carry => carry

);

tb : PROCESSBEGIN

a


12/184

Simulation output:


Synthesis report:

=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0% Number of 4 input LUTs: 2 out of 7168 0% Number of bonded IOBs: 4 out of 97 4%=========================================================================TIMING REPORTClock Information:------------------No clock signals found in this design

Timing Summary:---------------Speed Grade: -5




13/184

HALF SUBTRACTOR:

LOGIC DIAGRAM: TRUTH TABLE

VHDL SOURCE CODE:

--Design : HALF SUBTRACTOR--Description : To implement HALF SUBTRACTOR

--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hsub_dataflow is

Port ( a : in std_logic;b : in std_logic;diff : out std_logic;

borrow : out std_logic);end hsub_dataflow;architecture dataflow of hsub_dataflow isbegindiff


14/184

beginabar:= not a;diff


15/184

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xor2 is

Port ( a : in std_logic;b : in std_logic;z : out std_logic);

end xor2;architecture dataflow of xor2 isbegin

z


16/184

module hs_struct(a, b, dif, bor);input a;input b;output dif;output bor;

wire abar;xorx1(dif,a,b);

notn1(abar,a);anda1(bor,abar,b);

endmodule

TEST BENCH(VHDL):

LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;

ENTITY test_vhd ISEND test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)COMPONENT hsub_dataflowPORT(

a : IN std_logic;b : IN std_logic;diff : OUT std_logic;borrow : OUT std_logic);

END COMPONENT;

--InputsSIGNAL a : std_logic := '0';SIGNAL b : std_logic := '0';

--OutputsSIGNAL diff : std_logic;SIGNAL borrow : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: hsub_dataflow PORT MAP(

a => a,b => b,diff => diff,borrow => borrow

);

tb : PROCESSBEGIN

a


17/184

a


18/184




FULL ADDER:


VHDL SOURCE CODE:

--Design : FULL ADDER--Description : To implement FULL ADDER


Dataflow Modeling:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fadd_dataflow is

Port ( a : in std_logic;b : in std_logic;c : in std_logic;sum : out std_logic;carry : out std_logic);

end fadd_dataflow;architecture dataflow of fadd_dataflow issignal p,q,r,s:std_logic;beginp


19/184

sum


20/184

x2: xor2 port map (p,c,sum);a1: and2 port map (a,b,q);a2: and2 port map (b,c,r);a3: and2 port map (c,a,s);o1: or3 port map (q,r,s,carry);end structural;

and2 component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 is

Port ( a : in std_logic;b : in std_logic;z : out std_logic);

end and2;

architecture dataflow of and2 isbeginz


21/184

VERILOG SOURCE CODE:

Dataflow Modeling:

module fulladddataflow(a, b, cin, sum, carry);input a;input b;input cin;

output sum;output carry;

assign sum=a^b^cin;assign carry=(a & b) | (b & cin) | (cin & a);endmodule


module fuladbehavioral(a, b, c, sum, carry);input a;input b;input c;output sum;

output carry;reg sum,carry;reg t1,t2,t3;always @ (a or b or c) beginsum = (a^b)^c;t1=a & b;t2=b & c;t3=a & c;carry=(t1 | t2) | t3;end

endmodule

Structural Modeling:

module fa_struct(a, b, c, sum, carry);input a;input b;input c;output sum;output carry;

wire p,q,r,s;xorx1(p,a,b),x2(sum,p,c);anda1(q,a,b),a2(r,b,c),a3(s,a,c);oro1(carry,q,r,s);

endmodule

TEST BENCH(VHDL):

LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;



22/184

USE ieee.numeric_std.ALL;

ENTITY test1_vhd ISEND test1_vhd;

ARCHITECTURE behavior OF test1_vhd IS

-- Component Declaration for the Unit Under Test (UUT)COMPONENT fadd_dataflow

PORT(a : IN std_logic;b : IN std_logic;c : IN std_logic;sum : OUT std_logic;carry : OUT std_logic);

END COMPONENT;

--InputsSIGNAL a : std_logic := '0';SIGNAL b : std_logic := '0';SIGNAL c : std_logic := '0';


BEGIN-- Instantiate the Unit Under Test (UUT)uut: fadd_dataflow PORT MAP(

a => a,b => b,c => c,sum => sum,carry => carry

);

tb : PROCESSBEGIN

a


23/184


Synthesis report:

=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------



=========================================================================TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.



24/184




FULL SUBTRACTOR:


VHDL SOURCE CODE:

--Design :FULL SUBTRACTOR--Description : To implement FULL SUBTRACTOR--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

Dataflow Modeling:


use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fsub_dataflow is

Port ( a : in std_logic;b : in std_logic;c : in std_logic;diff : out std_logic;borrow : out std_logic);

end fsub_dataflow;architecture dataflow of fsub_dataflow issignal abar:std_logic;begin


A B C DIFFERENCE BORROW

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1


25/184

abar


26/184

port(a,b,c:in std_logic;z:out std_logic);

end component;signal p,q,r,s,abar:std_logic;beginx1:xor2 port map (a,b,p);x2:xor2 port map (p,c,diff);n1:not1 port map (a,abar);a1:and2 port map (abar,b,q);

a2:and2 port map (b,c,r);a3:and2 port map (c,abar,s);o1:or3 port map (q,r,s,borrow);end structural;


Dataflow Modeling:

module fulsubdataflow(a, b, cin, diff, borrow);input a;input b;input cin;output diff;output borrow;

wire abar;assign abar= ~ a;assign diff=a^b^cin;assign borrow=(abar & b) | (b & cin) |(cin & abar);

endmodule


module fulsubbehavioral(a, b, cin, diff, borrow);input a;input b;input cin;output diff;output borrow;

reg t1,t2,t3;reg diff,borrow;reg abar;always @ (a or b or cin) beginabar= ~ a;diff = (a^b)^cin;t1=abar & b;t2=b & cin;t3=cin & abar;borrow=(t1 | t2) | t3;end

endmodule



27/184


module fs_struct(a, b, c, diff, borrow);input a;input b;input c;output diff;output borrow;

wire abar,p,q,r,s;

notn1(abar,a);xorx1(p,a,b),x2(diff,p,c);anda1(q,abar,b),a2(r,abar,c),a3(s,a,c);oro1(borrow,q,r,s);

endmodule

TEST BENCH(VHDL):


ENTITY tst_vhd ISEND tst_vhd;

ARCHITECTURE behavior OF tst_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fsub_dataflowPORT(a : IN std_logic;b : IN std_logic;c : IN std_logic;diff : OUT std_logic;borrow : OUT std_logic);

END COMPONENT;



BEGIN

-- Instantiate the Unit Under Test (UUT)uut: fsub_dataflow PORT MAP(

a => a,



28/184

b => b,c => c,diff => diff,borrow => borrow

);

tb : PROCESSBEGIN

a


29/184

* Final Report *=========================================================================Device utilization summary:---------------------------


Number of Slices: 1 out of 3584 0% Number of 4 input LUTs: 2 out of 7168 0%

Number of bonded IOBs: 5 out of 97 5%

=========================================================================TIMING REPORT





FULL ADDER USING TWO HALF ADDERS:


VHDL SOURCE CODE:

--Design : FULL ADDER USING TWO HALF ADDERS--Description : To implement FULL ADDER USING TWO HALF ADDERS--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i


library IEEE;use IEEE.STD_LOGIC_1164.ALL;


A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


30/184

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fadd2 is


end fadd2;

architecture structural of fadd2 iscomponent haddport(a,b:in std_logic;sum,carry:out std_logic);end component;component or2port(a,b:in std_logic;

z:out std_logic);end component;signal p,q,r:std_logic;beginh1:hadd port map (a,b,p,q);h2:hadd port map (p,c,sum,r);

o1:or2 port map (r,q,carry);end structural;

hadd component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hadd is

Port ( a : in std_logic;b : in std_logic;sum : out std_logic;

carry : out std_logic);end hadd;architecture dataflow of hadd isbeginsum


31/184



module fa_2ha(a, b, c, sum, carry);input a;input b;input c;output sum;

output carry;wire p,q,r;ha_dataflowh1(a,b,p,q),h2(p,c,sum,r);oro1(carry,q,r);endmodule

module ha_dataflow(a, b, s, ca);input a;input b;output s;output ca;

assign#2 s=a^b;assign#2 ca=a&b;

endmodule

TEST BENCH(VHDL):



ARCHITECTURE behavior OF tst_vhd IS-- Component Declaration for the Unit Under Test (UUT)COMPONENT fadd2PORT(

a : IN std_logic;b : IN std_logic;c : IN std_logic;sum : OUT std_logic;carry : OUT std_logic);

END COMPONENT;



BEGIN



32/184

-- Instantiate the Unit Under Test (UUT)uut: fadd2 PORT MAP(

a => a,b => b,c => c,sum => sum,carry => carry

);

tb : PROCESSBEGIN

a


33/184

=========================================================================Device utilization summary:---------------------------



=========================================================================TIMING REPORT





FULL SUBTRACTOR USING TWO HALF SUBTRACTORS:


VHDL SOURCE CODE:

--Design : FULL SUBTRACTOR USING TWO HALF SUBTRACTORS--Description : To implement FULL SUBTRACTOR USING TWO HALF SUBTRACTORS--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i



A B C DIFFERENCE BORROW

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1


34/184

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fsub2 is

Port ( a : in std_logic;b : in std_logic;c : in std_logic;diff : out std_logic;

borrow : out std_logic);end fsub2;architecture structural of fsub2 iscomponent hsub_dataflowport(a,b:in std_logic;diff,borrow:out std_logic);end component;component or2port(a,b:in std_logic;

z:out std_logic);end component;signal p,q,r:std_logic;begin

h1:hsub_dataflow port map (a,b,p,q);h2:hsub_dataflow port map (p,c,diff,r);o1:or2 port map (r,q,borrow);end structural;

hsub component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hsub_dataflow is

Port ( a : in std_logic;

b : in std_logic;diff : out std_logic;borrow : out std_logic);

end hsub_dataflow;architecture dataflow of hsub_dataflow isbegindiff


35/184

oro1(borrow,q,r);

endmodule

module hs_dataflow(a, b, dif, bor);input a;input b;output dif;output bor;

wire abar;assign#3 abar=~a;assign#3 dif=a^b;assign#3 bor=b&abar;

endmodule

TEST BENCH(VHDL):



ARCHITECTURE behavior OF tst_vhd IS

-- Component Declaration for the Unit Under Test (UUT)COMPONENT fsub2PORT(

a : IN std_logic;b : IN std_logic;c : IN std_logic;diff : OUT std_logic;borrow : OUT std_logic

);END COMPONENT;



BEGIN

-- Instantiate the Unit Under Test (UUT)uut: fsub2 PORT MAP(

a => a,b => b,c => c,diff => diff,borrow => borrow

);

tb : PROCESS



36/184

BEGINa


37/184

Number of 4 input LUTs: 2 out of 7168 0% Number of bonded IOBs: 5 out of 97 5%

=========================================================================TIMING REPORT




Minimum period: No path found

Minimum input arrival time before clock: No path foundMaximum output required time after clock: No path foundMaximum combinational path delay: 7.824ns

RIPPLE CARRY ADDER (Binary adder):

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : RIPPLE CARRY ADDER--Description : To implement RIPPLE CARRY ADDER--Author : Jeyakannan.N--Reg no : 3082611


A(0) B(0) A(1) B(1) A(2) B(2) A(3) B(3)

S(0) S(1) S(2) S(3)

Cin


38/184

--Version : Xilinx- 7.1i


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity rca is

Port ( a : in std_logic_vector(3 downto 0);b : in std_logic_vector(3 downto 0);c : in std_logic;s : out std_logic_vector(3 downto 0);cout : out std_logic);

end rca;architecture structural of rca iscomponent fadd_behvport(a,b,c:in std_logic;sum,carry:out std_logic);end component;signal c0,c1,c2:std_logic;begin

f1:fadd_behv port map (a(0),b(0),c,s(0),c0);f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);end structural;

fadd_behv component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fadd_behv is


end fadd_behv;architecture Behavioral of fadd_behv isbeginp1:process(a,b,c)variable r,s,t:std_logic;beginr:= a and b;s:= b and c;t:= c and a;sum


39/184

module rcastructural(a, b, c, s, cout);input [3:0] a;input [3:0] b;input c;output [3:0] s;output cout;

wire c1,c2,c3;fulladddataflowf1(a[0],b[0],c,s[0],c1),

f2(a[1],b[1],c1,s[1],c2),f3(a[2],b[2],c2,s[2],c3),f4(a[3],b[3],c3,s[3],cout);

endmoduleFULL ADDER SOURCE CODE:

module fulladddataflow(a, b, cin, sum, carry);input a;input b;input cin;output sum;output carry;

assign sum=a^b^cin;assign carry=(a & b) | (b & cin) | (cin & a);

endmodule

TEST BENCH(VHDL):




-- Component Declaration for the Unit Under Test (UUT)COMPONENT rcaPORT(

a : IN std_logic_vector(3 downto 0);b : IN std_logic_vector(3 downto 0);c : IN std_logic;s : OUT std_logic_vector(3 downto 0);cout : OUT std_logic);

END COMPONENT;--InputsSIGNAL c : std_logic := '0';SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');--OutputsSIGNAL s : std_logic_vector(3 downto 0);SIGNAL cout : std_logic;

BEGIN-- Instantiate the Unit Under Test (UUT)uut: rca PORT MAP(

a => a,b => b,



40/184

c => c,s => s,cout => cout

);tb : PROCESSBEGINa


41/184

Clock Information:------------------No clock signals found in this designTiming Summary:---------------

Speed Grade: -5Minimum period: No path foundMinimum input arrival time before clock: No path found

Maximum output required time after clock: No path foundMaximum combinational path delay: 11.747ns

FAST ADDERS:

CARRY SELECT ADDER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : CARRY SELECT ADDER--Description : To implement CARRY SELECT ADDER



42/184




use IEEE.STD_LOGIC_UNSIGNED.ALL;entity csa is

Port ( a : in std_logic_vector(7 downto 0);b : in std_logic_vector(7 downto 0);c : in std_logic;su : inout std_logic_vector(3 downto 0);sd : inout std_logic_vector(3 downto 0);s : out std_logic_vector(7 downto 0);cout : out std_logic);

end csa;architecture structural of csa iscomponent rcaport(a,b:in std_logic_vector(3 downto 0);

c:in std_logic;s:out std_logic_vector(3 downto 0);cout:out std_logic);

end component;component mux2port(a,b,s:in std_logic;

z:out std_logic);end component;signal c1,c2,c3:std_logic;beginr1:rca port map (a(3 downto 0),b(3 downto 0),c,s(3 downto 0),c1);r2:rca port map (a(7 downto 4),b(3 downto 0),'0',su(3 downto 0),c2);r3:rca port map (a(7 downto 4),b(3 downto 0),'1',sd(3 downto 0),c3);

m1:mux2 port map (su(0),sd(0),c1,s(4));m2:mux2 port map (su(1),sd(1),c1,s(5));m3:mux2 port map (su(2),sd(2),c1,s(6));m4:mux2 port map (su(3),sd(3),c1,s(7));m5:mux2 port map (c2,c3,c1,cout);end structural;

rca component source code:



end rca;architecture structural of rca iscomponent fadd_behvport(a,b,c:in std_logic;sum,carry:out std_logic);



43/184

end component;signal c0,c1,c2:std_logic;beginf1:fadd_behv port map (a(0),b(0),c,s(0),c0);f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);end structural;

mux2 component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux2 is

Port ( a : in std_logic;b : in std_logic;s : in std_logic;z : out std_logic);

end mux2;architecture behv of mux2 is

beginprocess(a,b,s)beginif (s='0') thenz


44/184

module rcast(a, b, c, s, ca);input [3:0] a;input [3:0] b;input c;output [3:0] s;output ca;

wire c1,c2,c3;fulladddataflow

f1(a[0],b[0],c,s[0],c1),f2(a[1],b[1],c1,s[1],c2),f3(a[2],b[2],c2,s[2],c3),f4(a[3],b[3],c3,s[3],ca);

endmodule

mux2 component source code:

module mux2(i0, i1, s0, y);input i0;input i1;input s0;output y;

wire s0bar,p,q;notn1(s0bar,s0);anda1(p,i0,s0bar),a2(q,i1,s0);oro1(y,p,q);

endmodule

TEST BENCH(VHDL):



ARCHITECTURE behavior OF test_vhd IS-- Component Declaration for the Unit Under Test (UUT)COMPONENT csaPORT(

a : IN std_logic_vector(7 downto 0);b : IN std_logic_vector(7 downto 0);c : IN std_logic;su : INOUT std_logic_vector(3 downto 0);sd : INOUT std_logic_vector(3 downto 0);s : OUT std_logic_vector(7 downto 0);cout : OUT std_logic);

END COMPONENT;

--Inputs



45/184

SIGNAL c : std_logic := '0';SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');

--BiDirsSIGNAL su : std_logic_vector(3 downto 0);SIGNAL sd : std_logic_vector(3 downto 0);

--Outputs

SIGNAL s : std_logic_vector(7 downto 0);SIGNAL cout : std_logic;

BEGIN-- Instantiate the Unit Under Test (UUT)uut: csa PORT MAP(

a => a,b => b,c => c,su => su,sd => sd,s => s,cout => cout

);

tb : PROCESSBEGINa


46/184


Synthesis report:



47/184

=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400tq144-5

Number of Slices: 21 out of 3584 0% Number of 4 input LUTs: 37 out of 7168 0%

Number of bonded IOBs: 34 out of 97 35%

=========================================================================TIMING REPORT





CARRY SKIP ADDER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:



48/184

--Design : CARRY SKIP ADDER--Description : To implement CARRY SKIP ADDER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity cskadd is


end cskadd;architecture structural of cskadd iscomponent rca

port(a,b:in std_logic_vector(3 downto 0);c:in std_logic;

s:out std_logic_vector(3 downto 0);cout:out std_logic);

end component;component skipport(a,b:in std_logic_vector(3 downto 0);

c:in std_logic;z:out std_logic);

end component;component or2port(a,b:in std_logic;

z:out std_logic);

end component;signal c1,c2,c3,x1,x2:std_logic;beginr1:rca port map (a(3 downto 0),b(3 downto 0),c,s(3 downto 0),c1);r2:rca port map (a(7 downto 4),b(7 downto 4),c2,s(7 downto 4),c3);s1:skip port map (a(3 downto 0),b(3 downto 0),c,x1);s2:skip port map (a(7 downto 4),b(7 downto 4),c2,x2);o1:or2 port map (c1,x1,c2);o2:or2 port map (c3,x2,cout);end structural;




end rca;



49/184

architecture structural of rca iscomponent fadd_behvport(a,b,c:in std_logic;sum,carry:out std_logic);end component;signal c0,c1,c2:std_logic;beginf1:fadd_behv port map (a(0),b(0),c,s(0),c0);f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);

f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);end structural;

or2 component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or2 is

Port ( a : in std_logic;b : in std_logic;

z : out std_logic);end or2;architecture dataflow of or2 isbeginz


50/184

r2(a[8:5],b[8:5],c2,sum[8:5],c3);skpckts1(a[4:1],b[4:1],cin,x1),s2(a[8:5],b[8:5],c2,x2);oro1(c2,x1,c1),o2(cout,x2,c3);

endmodule


module rcast(a, b, c, s, ca);input [3:0] a;input [3:0] b;input c;output [3:0] s;output ca;

wire c1,c2,c3;fulladddataflowf1(a[0],b[0],c,s[0],c1),f2(a[1],b[1],c1,s[1],c2),f3(a[2],b[2],c2,s[2],c3),

f4(a[3],b[3],c3,s[3],ca);endmodule

skpckt component source code:

module skpckt(x, y, z, sk);input [3:0] x;input [3:0] y;input z;output sk;

wire [3:0]p;wire sk1;xor

x1(p[0],x[0],y[0]),x2(p[1],x[1],y[1]),x3(p[2],x[2],y[2]),x4(p[3],x[3],y[3]);anda1(sk1,p[0],p[1],p[2],p[3]),a2(sk,sk1,z);

endmodule

TEST BENCH(VHDL):



ARCHITECTURE behavior OF test_vhd IS-- Component Declaration for the Unit Under Test (UUT)COMPONENT cskaddPORT(

a : IN std_logic_vector(7 downto 0);



51/184

b : IN std_logic_vector(7 downto 0);c : IN std_logic;s : OUT std_logic_vector(7 downto 0);cout : OUT std_logic);

END COMPONENT;--InputsSIGNAL c : std_logic := '0';SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');

SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');--OutputsSIGNAL s : std_logic_vector(7 downto 0);SIGNAL cout : std_logic;

BEGIN-- Instantiate the Unit Under Test (UUT)uut: cskadd PORT MAP(

a => a,b => b,c => c,s => s,cout => cout

);

tb : PROCESSBEGINa


52/184


Synthesis report:=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------



=========================================================================TIMING REPORT



Timing Summary:---------------

Speed Grade: -5




53/184

CARRY LOOK AHEAD ADDER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : CARRY LOOK AHEAD ADDER--Description : To implement CARRY LOOK AHEAD ADDER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i



entity calkadd isPort ( a : in std_logic_vector(7 downto 0);b : in std_logic_vector(7 downto 0);c : in std_logic;s : out std_logic_vector(7 downto 0);cout : out std_logic);

end calkadd;architecture structural of calkadd iscomponent fulladdport(a,b,c:in std_logic;s,ca:out std_logic);end component;signal c0,c1,c2,c3,c4,c5,c6:std_logic;beginf1:fulladd port map (a(0),b(0),c,s(0),c0);f2:fulladd port map (a(1),b(1),c0,s(1),c1);f3:fulladd port map (a(2),b(2),c1,s(2),c2);f4:fulladd port map (a(3),b(3),c2,s(3),c3);f5:fulladd port map (a(4),b(4),c3,s(4),c4);f6:fulladd port map (a(5),b(5),c4,s(5),c5);f7:fulladd port map (a(6),b(6),c5,s(6),c6);f8:fulladd port map (a(7),b(7),c6,s(7),cout);end structural;



54/184

fulladd component source code:


entity fulladd isPort ( a : in std_logic;

b : in std_logic;c : in std_logic;s : out std_logic;ca : out std_logic);

end fulladd;architecture dataflow of fulladd issignal l,m,g,p:std_logic;beginl


55/184

endmodule

TEST BENCH(VHDL):

LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;



-- Component Declaration for the Unit Under Test (UUT)COMPONENT calkaddPORT(

a : IN std_logic_vector(7 downto 0);b : IN std_logic_vector(7 downto 0);c : IN std_logic;

s : OUT std_logic_vector(7 downto 0);cout : OUT std_logic);

END COMPONENT;

--InputsSIGNAL c : std_logic := '0';SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');

--OutputsSIGNAL s : std_logic_vector(7 downto 0);SIGNAL cout : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: calkadd PORT MAP(

a => a,b => b,c => c,s => s,cout => cout

);

tb : PROCESSBEGINa


56/184

Simulation output:


Synthesis report:





57/184


=========================================================================TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.



Minimum period: No path foundMinimum input arrival time before clock: No path found

Maximum output required time after clock: No path foundMaximum combinational path delay: 17.102ns

RESULT:

Thus the OUTPUTs of Adders,Subtractors and Fast Adders are verified by synthesizing and simulating theVHDL and VERILOG code.



58/184

EXP NO: 02 DATE: 29-01-11

ENCODERS AND DECODERS

AIM

To develop the source code for encoders and decoders by using VHDL/VERILOG and obtain thesimulation & synthesis.ALGORITHM


ENCODER

LOGIC DIAGRAM TRUTH TABLE:

VHDL SOURCE CODE

--Design : ENCODER--Description : To implement ENCODER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder_dataflow is

Port ( d : in std_logic_vector(7 downto 0);z : out std_logic_vector(2 downto 0));

end encoder_dataflow;


D0 D1 D2 D3 D4 D5 D6 D7 X Y Z

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1


59/184

architecture dataflow of encoder_dataflow isbeginz(2)


60/184

or4 component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or4 is

Port ( a : in std_logic;

b : in std_logic;c : in std_logic;d : in std_logic;z : out std_logic);

end or4;architecture dataflow of or4 isbeginz


61/184

TEST BENCH(VHDL):


ENTITY test_vhd IS

END test_vhd;

ARCHITECTURE behavior OF test_vhd IS-- Component Declaration for the Unit Under Test (UUT)COMPONENT encoder_dataflowPORT(

d : IN std_logic_vector(7 downto 0);z : OUT std_logic_vector(2 downto 0));

END COMPONENT;--InputsSIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');--Outputs

SIGNAL z : std_logic_vector(2 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: encoder_dataflow PORT MAP(

d => d,z => z

);

tb : PROCESSBEGIN

d


62/184


Synthesis report:




=========================================================================TIMING REPORT







63/184

DECODERS:


VHDL SOURCE CODE:

--Design : DECODER--Description : To implement DECODER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder_dataflow is

Port ( a : in std_logic;b : in std_logic;e : in std_logic;z : out std_logic_vector(3 downto 0));

end decoder_dataflow;

architecture dataflow of decoder_dataflow issignal abar,bbar:std_logic;beginabar


64/184


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder_behv is

Port ( a : in std_logic;b : in std_logic;

e : in std_logic;z : out std_logic_vector(3 downto 0));

end decoder_behv;architecture Behavioral of decoder_behv isbeginp1:process(a,b)beginif (e='1') thenz(0)


65/184

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity nand3 is

Port ( a : in std_logic;b : in std_logic;c : in std_logic;

z : out std_logic);end nand3;architecture dataflow of nand3 isbeginz


66/184

z[0] = ~ ((~a) & (~b) & en);z[1] = ~ ((~a) & b & en);z[2] = ~ (a & (~b) & en);z[3] = ~ (a & b & en);

endendmodule


module decod_struct(a, b, e, z);input a;input b;input e;output [3:0] z;

wire abar,bbar;notn1(abar,a),n2(bbar,b);and

a1(z[0],abar,bbar,e),a2(z[1],abar,b,e),a3(z[2],a,bbar,e),a4(z[3],a,b,e);endmodule

TEST BENCH(VHDL):




-- Component Declaration for the Unit Under Test (UUT)COMPONENT decoder_dataflowPORT(

a : IN std_logic;b : IN std_logic;e : IN std_logic;z : OUT std_logic_vector(3 downto 0));

END COMPONENT;

--InputsSIGNAL a : std_logic := '0';SIGNAL b : std_logic := '0';SIGNAL e : std_logic := '0';

--OutputsSIGNAL z : std_logic_vector(3 downto 0);

BEGIN



67/184

-- Instantiate the Unit Under Test (UUT)uut: decoder_dataflow PORT MAP(

a => a,b => b,e => e,z => z

);

tb : PROCESSBEGINa


68/184

=========================================================================TIMING REPORT


Clock Information:

------------------No clock signals found in this design



RESULT:Thus the OUTPUTs of Encoder and Decoder are verified by synthesizing and simulating the VHDL and

VERILOG code.



69/184

EXP NO: 03 DATE: 29-01-11

MULTIPLEXER AND DEMULTIPLEXERAIM

To develop the source code for multiplexer and demultiplexer by using VHDL/VERILOG and obtain thesimulation & synthesis.

ALGORITHM

Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.

Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.

MULTIPLEXER:

LOGIC DIAGRAM:TRUTH TABLE:

1

2

8

9

1

2

8

9

Y

D 0

D 1

1

2

D 2

D 3

S 0

1

2

8

9

S 1

1

2

1

2

8

9

2

3

4

5

1

VHDL SOURCE CODE:

--Design : MULTIPLEXER--Description : To implement MULTIPLEXER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

Dataflow Modeling:



SELECT INPUT OUTPUT

S1 S0 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3


70/184

use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_dataflow is

Port ( d : in std_logic_vector(3 downto 0);s : in std_logic_vector(1 downto 0);y : out std_logic);

end mux_dataflow;architecture dataflow of mux_dataflow issignal s0bar,s1bar,p,q,r,st:std_logic;begin

p


71/184

z:out std_logic);end component;component and3port(a,b,c:in std_logic;

z:out std_logic);end component;component or4port(a,b,c,d:in std_logic;

z:out std_logic);

end component;signal s0bar,s1bar,p,q,r,st:std_logic;beginn1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d(0),s0bar,s1bar,p);a2:and3 port map (d(1),s0bar,s(1),q);a3:and3 port map (d(2),s(0),s1bar,r);a4:and3 port map (d(3),s(0),s(1),st);o1:or4 port map (p,q,r,st,y);end structural;



Port ( a : in std_logic;b : in std_logic;c : in std_logic;z : out std_logic);

end and3;architecture dataflow of and3 isbegin

z


72/184

entity or4 isPort ( a : in std_logic;

b : in std_logic;c : in std_logic;d : in std_logic;z : out std_logic);

end or4;architecture dataflow of or4 isbegin

z


73/184

n1(s2,s1),n2(s3,s0);anda1(s4,i[0],s2,s3),a2(s5,i[1],s2,s0),a3(s6,i[2],s1,s3),a4(s7,i[3],s1,s0);oro1(y,s4,s5,s6,s7);

endmodule

TEST BENCH(VHDL):



ARCHITECTURE behavior OF test_vhd IS-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux_dataflowPORT(

d : IN std_logic_vector(3 downto 0);s : IN std_logic_vector(1 downto 0);y : OUT std_logic);

END COMPONENT;

--InputsSIGNAL d : std_logic_vector(3 downto 0) := (others=>'0');SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');

--OutputsSIGNAL y : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: mux_dataflow PORT MAP(

d => d,s => s,y => y

);

tb : PROCESSBEGIN

d


74/184

Simulation output:


Synthesis report:

=========================================================================




=========================================================================

TIMING REPORT



Timing Summary:



75/184

---------------Speed Grade: -5


DEMULTIPLEXER:

LOGIC DIAGRAM: `TRUTH TABLE:

Y 0

S 1 S 0

D i n

E n a b l e

2

3

4

5

1

2

3

4

5

1

2

3

4

5

1

1

2

Y 1

2

3

4

5

1

Y 2

1

2

Y 3

VHDL SOURCE CODE:

--Design : DEMULTIPLEXER--Description : To implement DEMULTIPLEXER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_dataflow is

Port ( d : in std_logic;s : in std_logic_vector(1 downto 0);z : out std_logic_vector(3 downto 0));

end demux_dataflow;


INPUT OUTPUT

D S0 S1 Y0 Y1 Y2 Y31 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1


76/184

architecture dataflow of demux_dataflow issignal s0bar,s1bar:std_logic;begins0bar


77/184

z : out std_logic_vector(3 downto 0));end demux_struct;architecture structural of demux_struct iscomponent not1port(a:in std_logic;

z:out std_logic);end component;component and3port(a,b,c:in std_logic;

z:out std_logic);end component;signal s0bar,s1bar:std_logic;beginn1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d,s0bar,s1bar,z(0));a2:and3 port map (d,s0bar,s(1),z(1));a3:and3 port map (d,s(0),s1bar,z(2));a4:and3 port map (d,s(0),s(1),z(3));end structural;



Port ( a : in std_logic;b : in std_logic;c : in std_logic;z : out std_logic);

end and3;architecture dataflow of and3 isbegin

z


78/184

output [3:0] y;wire s2,s3;assign #2 s2=~s0;assign #2 s3=~s1;assign #3 y[0]=i&s2&s3;assign #3 y[1]=i&s2&s1;assign #3 y[2]=i&s0&s3;assign #3 y[3]=i&s0&s1;

endmodule


module demux_behv(s0, s1, i, y);input s0;input s1;input i;output [3:0] y;

reg [3:0] y;reg s2,s3;always@(i or s0 or s1)begins2=~s0;

s3=~s1;y[0]=i & s2 & s3;y[1]=i & s2 & s1;y[2]=i & s0 & s3;y[3]=i & s0 & s1;endendmodule


module demux_struct(s0, s1, i, y);input s0;input s1;

input i;output [3:0] y;wire s2,s3;notn1(s2,s0),n2(s3,s1);anda1(y[0],i,s2,s3),a2(y[1],i,s2,s1),a3(y[2],i,s0,s3),a4(y[3],i,s0,s1);

endmodule

TEST BENCH(VHDL):






79/184

-- Component Declaration for the Unit Under Test (UUT)COMPONENT demux_dataflowPORT(

d : IN std_logic;s : IN std_logic_vector(1 downto 0);z : OUT std_logic_vector(3 downto 0));

END COMPONENT;

--InputsSIGNAL d : std_logic := '0';SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');

--OutputsSIGNAL z : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: demux_dataflow PORT MAP(

d => d,

s => s,z => z

);

tb : PROCESSBEGIN

d


80/184

Synthesis report:

=========================================================================

* Final Report *

=========================================================================

Device utilization summary:

---------------------------


Number of Slices: 2 out of 3584 0%

Number of 4 input LUTs: 4 out of 7168 0% Number of bonded IOBs: 7 out of 97 7%

=========================================================================

TIMING REPORT





RESULT:

Thus the OUTPUTs of Multiplexers and Demultiplexers are verified by synthesizing and simulating theVHDL and VERILOG code.



81/184

EXP NO: 04 DATE: 06-02-11

FLIP FLOPS

AIM:

To develop the source code for flip flops by using VHDL/VERILOG and Obtained the simulation &synthesis , place and route and implement into FPGA.

ALGORITHM:


SR FLIPFLOP:



Q(t) S R Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 X

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 X


82/184

1

2

3

Q

R

S

1

2

3Q

C P

1

2

3

1

2

3

VHDL SOURCE CODE:

--Design : SR-FLIP FLOP--Description : To implement SR-FLIP FLOP--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity srff is

Port ( s : in std_logic;r : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic;qbar : inout std_logic);

end srff;

architecture Behavioral of srff isbeginprocess(s,r,clk,rst,q,qbar)beginif (rst='1') thenq


83/184



module srflipflop(s, r, clk, rst, q, qbar);input s;input r;input clk;

input rst;output q;output qbar;

reg q,qbar;always @ (posedge(clk) or posedge(rst)) beginif(rst==1'b1) beginq= 1'b0;qbar= 1'b1;endelse if(s==1'b0 && r==1'b0)beginq=q; qbar=qbar;end

else if(s==1'b0 && r==1'b1)

beginq= 1'b0; qbar= 1'b1;end

else if(s==1'b1 && r==1'b0)begin

q= 1'b1; qbar= 1'b0;endelsebeginq=1'bx;qbar=1'bx;endend

endmodule

TEST BENCH(VHDL):




-- Component Declaration for the Unit Under Test (UUT)COMPONENT srffPORT(

s : IN std_logic;r : IN std_logic;clk : IN std_logic;rst : IN std_logic;q : INOUT std_logic;qbar : INOUT std_logic);



84/184

END COMPONENT;

--InputsSIGNAL s : std_logic := '0';SIGNAL r : std_logic := '0';SIGNAL clk : std_logic := '0';SIGNAL rst : std_logic := '0';

--BiDirs

SIGNAL q : std_logic;SIGNAL qbar : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: srff PORT MAP(

s => s,r => r,clk => clk,rst => rst,q => q,qbar => qbar

);

tb : PROCESSBEGIN

clk


85/184

Synthesis report:

=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : srff.ngrTop Level Output File Name : srffOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NO

Design Statistics

# IOs : 6

Macro Statistics :# Registers : 2# 1-bit register : 2

Cell Usage :# BELS : 3# LUT2 : 3# FlipFlops/Latches : 2# FDCE : 1# FDPE : 1# Clock Buffers : 1

# BUFGP : 1# IO Buffers : 5# IBUF : 3# OBUF : 2=========================================================================

Device utilization summary:---------------------------




86/184

Number of Slices: 2 out of 3584 0% Number of Slice Flip Flops: 2 out of 7168 0% Number of 4 input LUTs: 3 out of 7168 0% Number of bonded IOBs: 6 out of 97 6% Number of GCLKs: 1 out of 8 12%

=========================================================================TIMING REPORT


Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 2 |-----------------------------------+------------------------+-------+


Minimum period: No path foundMinimum input arrival time before clock: 3.529nsMaximum output required time after clock: 6.216nsMaximum combinational path delay: No path found

Timing Detail:--------------All values displayed in nanoseconds (ns)

=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Total number of paths / destination ports: 8 / 4

-------------------------------------------------------------------------Offset: 3.529ns (Levels of Logic = 2)

Source: r (PAD)Destination: qbar (FF)Destination Clock: clk rising

Data Path: r to qbarGate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 3 0.715 1.066 r_IBUF (r_IBUF)LUT2:I0->O 2 0.479 0.745 _n00051 (_n0005)FDPE:CE 0.524 qbar----------------------------------------Total 3.529ns (1.718ns logic, 1.811ns route)

(48.7% logic, 51.3% route)

=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 2 / 2-------------------------------------------------------------------------



87/184

Offset: 6.216ns (Levels of Logic = 1)Source: qbar (FF)Destination: qbar (PAD)Source Clock: clk rising

Data Path: qbar to qbarGate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------

FDPE:C->Q 1 0.626 0.681 qbar (qbar_OBUF)OBUF:I->O 4.909 qbar_OBUF (qbar)----------------------------------------Total 6.216ns (5.535ns logic, 0.681ns route)

(89.0% logic, 11.0% route)

=========================================================================CPU : 5.77 / 7.67 s | Elapsed : 6.00 / 7.00 s

Place and root report:

Constraints file: srff.pcf.

Loading device for application Rf_Device from file '3s400.nph' in environmentC:/Xilinx.

"srff" is an NCD, version 3.1, device xc3s400, package tq144, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

Device speed data version: "ADVANCED 1.35 2005-01-22".

Device Utilization Summary:

Number of BUFGMUXs 1 out of 8 12%Number of External IOBs 6 out of 97 6%

Number of LOCed IOBs 0 out of 6 0%

Number of Slices 2 out of 3584 1%Number of SLICEMs 0 out of 1792 0%

Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)

Starting Placer

Phase 1.1Phase 1.1 (Checksum:98969a) REAL time: 1 secs

Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs

Phase 3.2Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs



88/184

Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 1 secs

Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs

Phase 6.8Phase 6.8 (Checksum:98f9a3) REAL time: 1 secs

Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs

Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs

Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs

Writing design to file srff.ncd

Total REAL time to Placer completion: 1 secsTotal CPU time to Placer completion: 1 secs

Starting Router





Total REAL time to Router completion: 2 secsTotal CPU time to Router completion: 1 secs

Generating "PAR" statistics.

**************************Generating Clock Report**************************

+---------------------+--------------+------+------+------------+-------------+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+| clk_BUFGP | BUFGMUX0| No | 2 | 0.000 | 0.936 |+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 -The Delay report will not be generated when running non-timing driven PARwith effort level Standard or Medium. If a delay report is required please doone of the following: 1) use effort level High, 2) use the followingenvironment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timingconstraints for the design.

Generating Pad Report.



89/184

All signals are completely routed.

Total REAL time to PAR completion: 2 secsTotal CPU time to PAR completion: 1 secs

Peak Memory Usage: 74 MB

Placement: Completed - No errors found.Routing: Completed - No errors found.

Number of error messages: 0Number of warning messages: 0Number of info messages: 1

Writing design to file srff.ncd

PAR done!

JK FLIPFLOP:


C P

12

8

9

1

2

3

1

2

3

Q

1

2

8

9 Q

K

J

VHDL SOURCE CODE:

--Design : JK-FLIP FLOP--Description : To implement JK-FLIP FLOP--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity jkff is

Port ( j : in std_logic;k : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic;qbar : inout std_logic);

end jkff;architecture Behavioral of jkff isbeginprocess(j,k,clk,rst,q,qbar)begin


Q(t) J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0


90/184

if (rst='1') thenq


91/184

qbar=~qbar;endendendmodule

TEST BENCH(VHDL):

LIBRARY ieee;USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;



-- Component Declaration for the Unit Under Test (UUT)COMPONENT jkffPORT(

j : IN std_logic;k : IN std_logic;

clk : IN std_logic;rst : IN std_logic;q : INOUT std_logic;qbar : INOUT std_logic);

END COMPONENT;

--InputsSIGNAL j : std_logic := '0';SIGNAL k : std_logic := '0';SIGNAL clk : std_logic := '0';SIGNAL rst : std_logic := '0';

--BiDirsSIGNAL q : std_logic;SIGNAL qbar : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: jkff PORT MAP(

j => j,k => k,clk => clk,rst => rst,q => q,qbar => qbar

);

tb : PROCESSBEGIN

clk


92/184

j


93/184


Number of Slices: 2 out of 3584 0% Number of Slice Flip Flops: 2 out of 7168 0% Number of 4 input LUTs: 3 out of 7168 0% Number of bonded IOBs: 6 out of 97 6% Number of GCLKs: 1 out of 8 12%

=========================================================================TIMING REPORT


Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 2 |

-----------------------------------+------------------------+-------+


Minimum period: 2.085ns (Maximum Frequency: 479.513MHz)Minimum input arrival time before clock: 3.529nsMaximum output required time after clock: 6.280nsMaximum combinational path delay: No path found

D FLIPFLOP:


1

2

3

C P

Q 1 2

3

1

2

31

2

3

1

2

3D

Q

VHDL SOURCE CODE:

--Design : D-FLIP FLOP--Description : To implement D-FLIP FLOP



library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dff is


Q(t) D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1


94/184

Port ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic;qbar : inout std_logic);

end dff;architecture Behavioral of dff isbeginprocess(d,clk,rst,q,qbar)

beginif (rst='1') thenq


95/184



-- Component Declaration for the Unit Under Test (UUT)COMPONENT dffPORT(

d : IN std_logic;clk : IN std_logic;rst : IN std_logic;q : INOUT std_logic;qbar : INOUT std_logic);

END COMPONENT;

--InputsSIGNAL d : std_logic := '0';SIGNAL clk : std_logic := '0';SIGNAL rst : std_logic := '0';


BEGIN

-- Instantiate the Unit Under Test (UUT)uut: dff PORT MAP(

d => d,clk => clk,rst => rst,q => q,qbar => qbar

);

tb : PROCESSBEGIN

clk


96/184


Synthesis report:

=========================================================================* Final Report *=========================================================================Device utilization summary:

---------------------------


Number of Slices: 1 out of 3584 0% Number of Slice Flip Flops: 2 out of 7168 0% Number of bonded IOBs: 5 out of 97 5% Number of GCLKs: 1 out of 8 12%

=========================================================================TIMING REPORT





97/184


Minimum period: No path foundMinimum input arrival time before clock: 2.796nsMaximum output required time after clock: 6.216nsMaximum combinational path delay: No path found

T FLIPFLOP:LOGIC DIAGRAM: TRUTH TABLE:

VHDL SOURCE

CODE:

--Design : T-FLIP FLOP

--Description : To implement T-FLIP FLOP--Author : Jeyakannan.N

--Reg no : 3082611--Version : Xilinx- 7.1i


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff is

Port ( t : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic;

qbar : inout std_logic);end tff;architecture Behavioral of tff isbeginprocess(t,clk,rst,q,qbar)beginif (rst='1') thenq


98/184

module tff(t, clk, rst, q, qbar);input t;input clk;input rst;output q;output qbar;

reg q,qbar;always @ (posedge(clk) or posedge(rst)) beginif(rst==1'b1) begin

q= 1'b0;qbar= 1'b1;endelse if (t==1'b0)beginq=q; qbar=qbar;endelsebeginq=~q; qbar=~qbar;endendendmodule

TEST BENCH(VHDL):




-- Component Declaration for the Unit Under Test (UUT)

COMPONENT tffPORT(t : IN std_logic;clk : IN std_logic;rst : IN std_logic;q : INOUT std_logic;qbar : INOUT std_logic);

END COMPONENT;

--InputsSIGNAL t : std_logic := '0';SIGNAL clk : std_logic := '0';SIGNAL rst : std_logic := '0';


BEGIN

-- Instantiate the Unit Under Test (UUT)uut: tff PORT MAP(

t => t,



99/184

clk => clk,rst => rst,q => q,qbar => qbar

);

tb : PROCESSBEGIN

clk


100/184



Number of Slices: 1 out of 3584 0% Number of Slice Flip Flops: 2 out of 7168 0%

Number of bonded IOBs: 5 out of 97 5% Number of GCLKs: 1 out of 8 12%

=========================================================================TIMING REPORT


Clock Information:------------------

-----------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 2 |-----------------------------------+------------------------+-------+


Minimum period: 2.707ns (Maximum Frequency: 369.372MHz)Minimum input arrival time before clock: 1.984nsMaximum output required time after clock: 6.280ns

Maximum combinational path delay: No path found

RESULT:

Thus the OUTPUTs of Flip Flops are verified by synthesizing and simulating the VHDL and VERILOGcode.

EXP NO: 05 DATE: 12-02-11



101/184

SHIFT REGISTERS

AIM:

To develop the source code for shifters unit by using VHDL/VERILOG and obtain the simulation &synthesis.ALGORITM:


SERIAL-IN SERIAL-OUT SHIFT REGISTER:

LOGIC DIAGRAM :

VHDL SOURCE CODE:

--Design : SISO SHIFT REGISTER--Description : To implement SISO SHIFT REGISTER--Author : Jeyakannan.N--Reg no : 3082611--Version : Xilinx- 7.1i


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity siso is

Port ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : out std_logic);

end siso;architecture Behavioral of siso issignal x:std_logic_vector(7 downto 0);

beginprocess(d,clk,rst)beginif (rst='1') thenq


102/184

x(5)


103/184

SIGNAL q : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut: siso PORT MAP(

d => d,clk => clk,rst => rst,

q => q);

tb : PROCESSBEGINclk


104/184

Number of bonded IOBs: 4 out of 97 4% Number of GCLKs: 1 out of 8 12%

=========================================================================TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.



Minimum period: 3.637ns (Maximum Frequency: 274.963MHz)Minimum input arrival time before clock: 3.144nsMaximum output required time after clock: 6.216nsMaximum combinational path delay: No path found

SERIAL IN PARALLEL OUT SHIFT REGISTER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : SIPO SHIFT REGISTER--Description : To implement SIPO SHIFT REGISTER



library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sipo is



105/184

Port ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic_vector(7 downto 0));

end sipo;architecture Behavioral of sipo isbeginprocess(d,clk,rst)begin

if (rst='1') thenq


106/184

COMPONENT sipoPORT(

d : IN std_logic;clk : IN std_logic;rst : IN std_logic;q : INOUT std_logic_vector(7 downto 0));

END COMPONENT;--Inputs

SIGNAL d : std_logic := '0';SIGNAL clk : std_logic := '0';SIGNAL rst : std_logic := '0';--BiDirsSIGNAL q : std_logic_vector(7 downto 0);BEGIN-- Instantiate the Unit Under Test (UUT)uut: sipo PORT MAP(

d => d,clk => clk,rst => rst,q => q

);

tb : PROCESSBEGINclk


107/184


Synthesis report:



Number of Slices: 5 out of 3584 0% Number of Slice Flip Flops: 8 out of 7168 0% Number of bonded IOBs: 11 out of 97 11% Number of GCLKs: 1 out of 8 12%

=========================================================================

TIMING REPORT




Minimum period: No path foundMinimum input arrival time before clock: 1.572nsMaximum output required time after clock: 6.216nsMaximum combinational path delay: 6.756ns



108/184

PARALLEL-IN PARELLEL-OUT SHIFT REGISTER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : PIPO SHIFT REGISTER--Description : To implement PIPO SHIFT REGISTER--Author : Jeyakannan.N--Reg no : 3082611

--Version : Xilinx- 7.1i

Vlsi Record

Documents

Transcript of Vlsi Record