VLSI - Neuron and Neural Network Design

8/13/2019 VLSI - Neuron and Neural Network Design

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Area X Delay (Neural Network Layout)

Area (micron square) = 110.2 * 103.8 = 11438.76

Delay (ns) = 1.3 ns

Area x Delay (um sq x ns) = 14870.388

Description of the Neuron:

There are 10 inputs to the neuron:

6 single-bit data inputs to the neuron,T, U, V, W, Y, Z a single-bit inhibitory inputI, Loadcontrol signal Reset control signal A clockwith 50% duty cycle.

The basic Neuron Function:

The neuron output contains a firingflip-flop you designed in Lab 2, and the output ofthe flip-flop APrepresents the output of the neuron.

The neuron "fires" when the Boolean expression (VY+WY+VZ+WZ+YZ+VW) + (/I)[T + U]evaluates to a 1.

The Boolean equation

= ( VY + WY + VZ + WZ + YZ + VW ) + ( /I )[ T + U ]

= ( V [ Y + Z + W ] ) + ( W [ Y + Z ] ) + ( YZ ) + ( /I )[ T + U ]

= ( V [ Y + Z + W ] ) + ( W [ Y + Z ] ) + ( YZ ) + ( /I )[ T + U ]

= ( V [ Y + Z + W ] ) . ( W [ Y + Z ] ) . ( YZ ) . ( /I )[ T + U ]

The Firing Logic is built using

3 - Compound Gates (designed in Lab 1)

1 - inverter1 (for Input I)

1 - 2-Input NAND Gate


NEURON:


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The Block Diagram of the Neuron:

The Neuron is built using

3 - Compound Gates (designed in Lab 1)

3 - inverter1 (for /I, /load, /clk)



1 - Flip Flop

Floor Plan of the Neuron:

Inverter 1 and 2 as Super Buffers


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NEURON:

Schematic:


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Schematic Simulation:

Case (a):

Load is setto 1 and kept high. All other inputs except clock are 0. Neuron flip-flop is Resetted.

clk=2ns


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Case (b):

Load is set to 1 and kept high. Then the neuron is tested by sequencing through all

combinations of inputs starting with TUVWYZ= 000000 to 111111. I=0.

Clk=2ns


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Case (c):

Set I = 1 (inhibition) and sequence through the same inputs. The output AP is low at some

times.

Clk=2ns


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Case (d):

Reset the neuron flip flop. Now load is set to 0 (zero).The 6 data inputs to are set to 111111,

and I = 0. The flip flop output remains zero.

Clk=2ns


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LAYOUT:


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Case (c):


times.

Clk=2ns


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Case (d):



Clk=2ns


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Description of the Simulation Experiments:

Simulations of Schematics and Layouts:

Case (a):

Load is setto 1 and kept high. All other inputs except clock are 0. Neuron flip-flop is Resetted.

Clk=2ns

Case (b):

Load is set to 1 and kept high. Then the neuron is tested by sequencing through allcombinations of inputs starting with TUVWYZ= 000000 to 111111. I=0.

Clk=2ns

Case (c):


times.

Clk=2ns

Case (d):



Clk=2ns


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NEURON NETWORK:

SCHEMATIC:


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Schematic Simulation:

To determine the fastest clock:

The fastest clock is determined at the worst case inputs.

Initially the Flip Flop is given Reset. Set the inputs to 0(zero) except T which is set to 1. The I input is changes from 0 to 1 and 1 to zero, which is the worst case condition.

Here the worst case condition is where the signal travels through the maximum number of gates that

has the maximum delay in it, i.e. through the inverter-compound gate and the 4-input NAND gate. The

output is given at the negative edge of the clock and it is 90% before the positive edge of the clock.

The Fastest clock for the schematic is found to be 1.25ns.

Case (a):

Showing the working of the Neuron Network for the fastest clock at 1.25ns, with I changing and

T=1,U,Y,Z,V,W=0. Load=1, Reset initially.


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Case (b):

The Enlarged view showing the Clock (1.25ns), output (AP), Inputs (T, I). The output is produced after the

negative edge of the clock and is 90% before the rising of the next clock.


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LAYOUT:

The Layout of the Neuron consists of original Neuron that fans out to 24 other empty Neurons. The

output is measured from the farthest Neuron Input that includes the worst case delay. The output

of the original Neuron goes to the Super Buffer Inverters (2,3), which is fan out to 24 empty Neuro

The Layout is built such that it forms a Square Shape so that to reduce the wire delay. The Inputs

ITUVWYZ,clk,rst,load and the output AP pins are brought out to the edges Layout. The wasted area

is also included in Area calculation. The Metals 1-4 are used for the entire Neural Network.


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Case (b):

The Enlarged view showing the Clock (1.25ns), output (AP), Inputs (T, I). The output is produced after the

negative edge of the clock and is 90% before the rising of the next clock.


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VLSI - Neuron and Neural Network Design

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