VLSI Lab Output
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Transcript of VLSI Lab Output
SIMULATION OF LOGIC GATES
SIMULATION OF FULL ADDER& FULL SUBTRACTOROUTPUT WAVEFORM FOR FULL ADDER
OUTPUT WAVEFORM FOR FULL SUBTRACTOR
SIMULATION OF 8-BIT ADDER
SIMULATION OF 8-BIT SUBTRACTOR
SIMULATION OF 4 BIT MULTIPLIER
SIMULATION OF ENCODER AND DECODEROUTPUT WAVEFORM FOR 8-3 ENCODER
OUTPUT WAVEFORM FOR 3-8 DECODERS
SIMULATION OF MULTIPLEXER / DE-MULTIPLEXEROUTPUT WAVEFORM FOR 8-1 MULTIPLEXER
OUTPUR WAVEFORM FOR 1-8 DEMULTIPLEXERS
SIMULATION OF D FLIP FLOPOUTPUT WAVEFORM FOR D-FLIPFLOP
SIMULATION OF3-BIT COUNTER AND 3-BIT UP/DOWNCOUNTEROUTPUT WAVEFORM FOR 3-BIT COUNTER
OUTPUT WAVEFORM FOR 3-BIT UP/DOWV COUNTER
SIMULATION OF PRBS GENERATOR
SIMULATION OF ALU
SYNTHESIS AND RTL SCHEMATIC FOR 8-BIT ADDER/SUBTRACTORAND MULTIPLEXER/DEMULTIPLEXERSOUTPUT FOR 8-BIT ADDER/SUBTRACTOR
OUTPUT FOR MULTIPLEXER
SYNTHESIS AND RTL SCHMATIC OF COUNTER/ D-FLIP FLOP
DESIGN AND SIMULATE CMOS INVERTER
DESIGN AND SIMULATE MOS DIFFERENTIAL AMPLIFIER