vlsi lab

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Ex No. 1 BASIC LOGIC GATES Date:

AIM:

To write a VHDL program for basic logic gates using dataflow modeling and simulate using Xilinx. TOOLS REQUIRED: 1.Xilinx ISE 8.li 2.ModelSim Simulator

1. OR :

LOGIC DIAGRAM: TRUTH TABLE:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is Port ( a,b: in STD_LOGIC; y: out STD_LOGIC); end orgate; architecture Behavioral of orgate is begin y<= a or b; end Behavioral;

a b y 0 0 0 0 1 1 1 0 1 1 1 1

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OUTPUT WAVEFORM:

2. AND : LOGIC DIAGRAM: TRUTH TABLE:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate is Port ( a,b: in STD_LOGIC; y: out STD_LOGIC); end andgate; architecture Behavioral of andgate is begin y<= a and b; end Behavioral;

a b y 0 0 0 0 1 0 1 0 0 1 1 1

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OUTPUT WAVEFORM:

3. NOT : TRUTH TABLE: LOGIC DIAGRAM:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity notgate is Port (a: in STD_LOGIC; y: out STD_LOGIC); end notgate; architecture Behavioral of notgate is begin y<= not a; end Behavioral;

a y 0 1 1 0

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OUTPUT WAVEFORM:

4. NOR : TRUTH TABLE:

LOGIC DIAGRAM:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity norgate is Port ( a,b: in STD_LOGIC; y: out STD_LOGIC); end norgate; architecture Behavioral of norgate is begin y<= a nor b; end Behavioral;

a b y 0 0 1 0 1 0 1 0 0 1 1 0

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OUTPUT WAVEFORM:

5. NAND : TRUTH TABLE: LOGIC DIAGRAM:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nandgate is Port ( a,b: in STD_LOGIC; y: out STD_LOGIC); end orgate; architecture Behavioral of nandgate is begin y<= a nand b; end Behavioral;

a b y 0 0 1 0 1 1 1 0 1 1 1 0

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OUTPUT WAVEFORM:

6. XOR : TRUTH TABLE:

LOGIC DIAGRAM:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorgate is Port ( a,b: in STD_LOGIC; y: out STD_LOGIC); end xorgate; architecture Behavioral of xorgate is begin y<= a xor b; end Behavioral; OUTPUT WAVEFORM:

a b y 0 0 0 0 1 1 1 0 1 1 1 0

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7. XNOR : TRUTH TABLE: LOGIC DIAGRAM:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnorgate is Port ( a,b: in STD_LOGIC; y: out STD_LOGIC); end xnorgate; architecture Behavioral of xnorgate is begin y<= a xnor b; end Behavioral;

OUTPUT WAVEFORM:

a b y 0 0 1 0 1 0 1 0 0 1 1 1

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RESULT:

Thus the VHDL program for basic logic gates was written using data flow modeling and simulated using Xilinx.

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Ex No. 2 HALF ADDER

Date:

AIM:

To write a VHDL program to implement half adder using all the modeling and simulate using Xilinx. TOOLS REQUIRED:

1. Xilinx ISE 8.1i 2. Model Sim Simulator

LOGIC DIAGRAM:

TRUTH TABLE:

a b sum carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

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PROGRAM: Structural modeling: Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity halfadder is Port (a: in STD_LOGIC; b: in STD_LOGIC; sum: out STD_LOGIC; carry: out STD_LOGIC); end halfadder; architecture Behavioral of halfadder is component xor1 port (a1, b1: in std_logic; c1: out std_logic); end component; component and1 port (x, y : in std_logic; z: out std_logic); end component; begin X1:xor1 port map (a, b, sum); X2:and1 port map (a, b, carry); end behavioral; Data flow modeling: Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder is port(a,b:in std_logic; sum,carry: out std_logic); end halfadder; architecture behavioral of halfadder is begin sum<=a xor b; carry <= a and b; end behavioral;

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Behavioral modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadd is Port ( x,y : in STD_LOGIC; sum, carry : out STD_LOGIC); end halfadd; architecture Behavioral of halfadd is begin process(x,y) begin if(x='0' and y='0') then sum<='0'; carry<='0'; elsif(x='0' and y='1') then sum<='1'; carry<='0'; elsif(x='1' and y='0') then sum<='1'; carry<='0'; elsif(x='1' and y='1') then sum<='0'; carry<='1'; end if; end process; end Behavioral;

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OUTPUT WAVEFORM:

RESULT: Thus the half adder program was written in all the modeling and simulated using Xilinx software.

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Ex No. 3 FULL ADDER

Date:

AIM:

To write a VHDL program for a full adder using all the three modeling and to simulate using Xilinx. TOOLS REQUIRED:

1. Xilinx ISE 8.1i 2. Model Sim Simulator

LOGIC DIAGRAM:

TRUTH TABLE:

a b C Sum carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

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PROGRAM: Structural modeling: Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder is Port (a : in STD_LOGIC; b: in STD_LOGIC; c: in STD_LOGIC; sum: out STD_LOGIC; carry: out STD_LOGIC); end fulladder; architecture Behavioral of fulladder is component halfadder is port (a1: in std_logic; b1: in std_logic; c1: out std_logic; y1: out std_logic); end component; component or1 is port(a:in std_logic; b:in std_logic; c:out std_logic); end component; signal x,y,z: std_logic; begin ha1:halfadder port map(a,b,x,y); ha2: halfadder port map(x,c,sum,z); or2:or1 port map(y,z,carry); end Behavioral; dataflow modeling: entity fulladder is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end fulladder; architecture Behavioral of fulladder is

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begin sum<=x xor y xor z; carry<=(x and y)or(y and z)or(z and x); end Behavioral; behavioral modeling: entity fulladder is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end fulladder; architecture Behavioral of fulladder is begin process(x,y) begin if(x=’0’ and y=’0’ and z=’0’) then sum<= ‘0’; carry<= ‘0’; elsif(x=’0’ and y=’0’ and z=’1’) then sum<= ‘1’; carry<= ‘0’; elsif(x=’0’ and y=’1’ and z=’0’) then sum<= ‘1’; carry<= ‘0’; elsif(x=’0’ and y=’1’ and z=’1’) then sum<= ‘0’; carry<= ‘1’; elsif(x=’1’ and y=’0’ and z=’1’) then sum<= ‘0’; carry<= ‘1’; elsif(x=’1’ and y=’1’ and z=’0’) then sum<= ‘0’; carry<= ‘1’; elsif(x=’1’ and y=’1’ and z=’1’) then sum<= ‘1’; carry<= ‘1’; end if; end process; end Behavioral;

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OUTPUT WAVEFORM:

RESULT:

The full adder VHDL program using all the modeling was written and executed using Xilinx.

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Ex No. 4 HALF SUBTRACTOR

Date:

AIM: To write a VHDL program of a half subtractor using all the modeling and simulate using Xilinx. TOOLS REQUIRED:

1.Xilinx ISE 8.11 2.ModelSim Simulator

LOGIC DIAGRAM:

TRUTH TABLE:

a b diff borr 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

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PROGRAM: Structural modeling: Library ieee; Use ieee.std_logic_1164.all; Entity halfsub is Port(a,b:in std_logic; Diff,borr:out std_logic); End halfsub; architecture Behavioral of halfsub is Component xor1 is Port(m,n:in std_logic; o: out std_logic); end component; component and1 is port(x,y:in std_logic; w:out std_logic); end component; component not1 is port(f:in std_logic; g:out std_logic); end component; signal x: std_logic; begin x1:xor1 port map(a,b,diff); x2:and1 port map(b,x,borr); x3:not1 port map(a,x); end Behavioral; Dataflow modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfsub is Port ( a,b : in STD_LOGIC; diff,bor : out STD_LOGIC); end halfsub; architecture Behavioral of halfsub is begin diff<=a xor b;

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bor<=(not a)and c; end Behavioral; Behavioral modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfsub is Port ( x,y : in STD_LOGIC; diff,bor : out STD_LOGIC); end halfsub; architecture Behavioral of halfsub is begin process(x,y) begin if(x='0' and y='0') then diff<='0'; bor<='0'; elsif(x='0' and y='1') then bor<='1'; diff<='1'; elsif(x='1' and y='0') then diff<='1'; bor<='0'; elsif(x='1' and y='1') then diff<='0'; bor<='0'; end if; end process; end Behavioral;

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OUTPUT WAVEFORM:

RESULT:

The half subtractor VHDL program using all the three modeling was written and executed using Xilinx.

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EX No. 5 FULL SUBTRACTOR

Date:

AIM: To write a VHDL program of a full subtractor using all the modeling and simulate using xilinx. TOOLS REQUIRED:

1. xilinx ISE 8.li 2. ModelSim Simulator

LOGIC DIAGRAM:

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TRUTH TABLE:

a b C diff borr 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

PROGRAM: Structural modeling: Library ieee; Use ieee.std_logic_1164.all; Entity fullsub17 is Port(a,b,c:in std_logic; Diff,borrow:out std_logic); End fullsub17; Architecture Behavioral of fullsub17 is Component aor1 is Port(m,n,o:in std_logic; z:out std_logic); end component; component and1 is port(a,y:in std_logic; w: out std_logic); end component; component or1 is port(p,q,r:in std_logic; s:out std_logic); end component; component not1 is port(f:in std_logic; g:out std_logic); end component; signal d,e,f,h,i,j:std_logic; begin a1:aor1 port map(a,b,d); a2: aor1 port map(d,c,diff); a3:not1 port map(a,h);

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a4:and1 port map(h,b,i); a5:and1 port map(c,b,e); a6:and1 port map(h,c,f); a7:or1 port map(i,e,j); a8:or1 port map(f,j,borrow); end Behavioral ; Dataflow modeling: entity fullsub is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; diff: out STD_LOGIC; bor : out STD_LOGIC); end fulladder; architecture Behavioral of fullsub is begin diff<=a aor b aor c; bor<=((not a ) and b) or (b and c) or ((not a) and c) end Behavioral; Behavioral modeling: entity fullsub is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; diff : out STD_LOGIC; bor : out STD_LOGIC); end fullsub; architecture Behavioral of fulladder is begin process(a,b) begin if(a=’0’ and b=’0’ and c=’0’) then diff<= ‘0’; bor<= ‘0’; elsif(a=’0’ and b=’0’ and c=’1’) then diff<= ‘1’; bor<= ‘1’; elsif(a=’0’ and b=’1’ and c=’0’) then

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diff<= ‘1’; bor<= ‘1’; elsif(a=’0’ and b=’1’ and c=’1’) then diff<= ‘0’; bor<= ‘1’; elsif(a=’1’ and b=’0’ and c=’1’) then diff<= ‘0’; bor<= ‘0’; elsif(a=’1’ and b=’1’ and c=’0’) then diff<= ‘0’; bor<= ‘0’; elsif(a=’1’ and b=’1’ and c=’1’) then diff<= ‘1’; bor<= ‘1’; end if; end process; end Behavioral; OUTPUT WAVEFORM:

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RESULT:

Thus the full subtractor VHDL program was written in all the modeling and simulated using Xilinx software.

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Ex No. 6 RIPPLE CARRY ADDER

Date:

AIM: To write a VHDL program to implement four bit ripple carry adder and simulate using Xilinx in dataflow modeling. APPARATUS REQUIRED:

1. Xilinx ise 8.1i 2. Model sim simulator

LOGIC DIAGRAM:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ripple is Port ( a,b : in STD_LOGIC_vector(7 downto 0); cin : in STD_LOGIC;

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s : out STD_LOGIC_vector(7 downto 0); cout : out STD_LOGIC); end ripple; architecture Behavioral of ripple is signal x0,x1,x2,x3,x4,x5,x6 :std_logic; component fulladder is Port ( a,b,c : in STD_LOGIC; s,ca : out STD_LOGIC); end component; begin d1:fulladder port map(a(0),b(0),cin,s(0),x0); d2:fulladder port map(a(1),b(1),x0,s(1),x1); d3:fulladder port map(a(2),b(2),x1,s(2),x2); d4:fulladder port map(a(3),b(3),x2,s(3),x3); d5:fulladder port map(a(4),b(4),x3,s(4),x4); d6:fulladder port map(a(5),b(5),x4,s(5),x5); d7:fulladder port map(a(6),b(6),x5,s(6),x6); d8:fulladder port map(a(7),b(7),x6,s(7),cout); end Behavioral; OUTPUT WAVEFORM:

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RESULT:

Thus the eight bit ripple carry adder program was written in dataflow modeling and simulated using Xilinx software.

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Ex No. 7 8:1 MUX

Date:

AIM:

To write a VHDL program to implement 8:1 multiplexer in all the three modeling and to simulate using Xilinx. TOOLS REQUIRED:

1. Xilinx ISE 8.1i 2. ModelSim Simulator

LOGIC DIAGRAM:

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PROGRAM: Dataflow modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity muxgates is Port ( i:in std_logic_vector(7 downto 0); s1,s2,s3 : in STD_LOGIC; o : out STD_LOGIC); end muxgates; architecture Behavioral of muxgates is begin o<=((not s1)and (not s2) and (not s3) and i(0))or ((not s1)and (not s2) and (s3) and i(1))or ((not s1)and (s2) and (not s3) and i(2))or ((not s1)and (s2) and (s3) and i(3))or ((s1)and (not s2) and (not s3) and i(4))or ((s1)and (not s2) and (s3) and i(5))or ((s1)and (s2) and (not s3) and i(6))or ((s1)and (s2) and (s3) and i(7)); end Behavioral; Behavioral modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity B-Mux is Port ( i0,i1,i2,i3,i4,i5,i6,i7 : in STD_LOGIC; s : in STD_LOGIC_VECTOR(2 DOWNTO 0); y : out STD_LOGIC);

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end B-Mux; architecture Behavioral of B-Mux is begin process(i0,i1,i2,i3,i4,i5,i6,i7,s) begin case s is when "000"=>y<=i0; when "001"=>y<=i1; when "010"=>y<=i2; when "011"=>y<=i3; when "100"=>y<=i4; when "101"=>y<=i5; when "110"=>y<=i6; when "111"=>y<=i7; when others=> NULL; end case; end process; end Behavioral; Structural modeling: entity muxstruct42 is Port ( s0 : in STD_LOGIC; s1 : in STD_LOGIC; i0 : in STD_LOGIC; i1 : in STD_LOGIC; i2 : in STD_LOGIC; i3 : in STD_LOGIC; p0 : out STD_LOGIC); end muxstruct42; architecture Behavioral of muxstruct42 is component and342 is port(a,b,c:in std_logic; d:out std_logic); end component; component or442 is port(u,v,w,x:in std_logic; y:out std_logic); end component; component not42 is port(e:in std_logic;

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f:out std_logic); end component; signal w0,w1,w2,w3,r,s:std_logic; begin mux1:not42 port map(s1,r); mux2:not42 port map(s0,s); mux3:and342 port map(i0,r,s,w0); mux4:and342 port map(i1,r,s0,w1); mux5:and342 port map(i2,s1,s,w2); mux6:and342 port map(i3,s1,s0,w3); mux7:or442 port map(w0,w1,w2,w3,p0); end Behavioral; OUTPUT WAVEFORM:

RESULT:

Thus the 8:1 multiplexer VHDL program was written in all the modeling and simulated using Xilinx software.

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Ex No. 8 1:8 DEMUX Date:

AIM :

To write a 1:8 demultiplexer program in all the modeling and simulate it using xilinx software. TOOLS REQUIRED :


LOGIC DIAGRAM :

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PROGRAM : Behavioral modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmuxbeh is Port ( i : in STD_LOGIC; s1,s2,s3 : in STD_LOGIC; m : out STD_LOGIC_vector(7 downto 0)); end dmuxbeh; architecture Behavioral of dmuxbeh is signal e:integer; signal s:std_logic_vector(2 downto 0); begin s<=(s1&s2&s3); e<=0 when s="000" else 1 when s="001" else 2 when s="010" else 3 when s="011" else 4 when s="100" else 5 when s="101" else 6 when s="110" else 7; process(e) begin for n in 0 to 7 loop if(n=e) then m(e)<=i; else m(n)<='0'; end if; end loop; end process; end Behavioral;

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Data flow modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux is Port ( i : in STD_LOGIC; s1,s2,s3 : in STD_LOGIC; h : out STD_LOGIC_vector(7 downto 0)); end dmux; architecture Behavioral of dmux is signal a,b,c:std_logic; begin a<=not s1; b<=not s2; c<=not s3; h(0)<=(i and a and b and c); h(1)<=(i and a and b and s3); h(2)<=(i and a and s2 and c); h(3)<=(i and a and s2 and s3); h(4)<=(i and s1 and b and c); h(5)<=(i and s1 and b and s3); h(6)<=(i and s1 and s2 and c); h(7)<=(i and s1 and s2 and s3); end Behavioral; Structural Modeling: entity demux is Port ( s : in STD_LOGIC_VECTOR (2 downto 0); i : in STD_LOGIC; y : out STD_LOGIC_VECTOR (7 downto 0)); end demux; architecture Behavioral of demux is signal t: std_logic_vector (2 downto 0); component andga is Port ( a,b,c,d : in STD_LOGIC; x : out STD_LOGIC); end component; component notga is

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Port ( a : in STD_LOGIC; b : out STD_LOGIC); end component; begin x1:notga port map(s(2),t(2)); x2:notga port map(s(1),t(1)); x3:notga port map(s(0),t(0)); x4:andga port map (i,t(0),t(1),t(2),y(0)); x5:andga port map (i,t(0),t(1),s(2),y(1)); x6:andga port map (i,t(0),s(1),t(2),y(2)); x7:andga port map (i,t(0),s(1),s(2),y(3)); x8:andga port map (i,s(0),t(1),t(2),y(4)); x9:andga port map (i,s(0),t(1),s(2),y(5)); x10:andga port map (i,s(0),s(1),t(2),y(6)); x11:andga port map (i,s(0),s(1),s(2),y(7)); end Behavioral; OUTPUT WAVEFORM:

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RESULT : Thus a 1:8 demultiplexer VHDL program in all the modeling is written and simulated using xilinx software.

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Ex No. 9 8 : 3 ENCODER

Date:

AIM :

To write a VHDL program for 8:3 encoder in all the modeling and simulate it using xilinx software. TOOLS REQUIRED :


PROGRAM : Behavioral modeling: LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; USE ieee.std_logic_unsigned.all ; ENTITY encoder IS PORT ( x : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; y : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 )); END encoder ; ARCHITECTURE Behavioral OF encoder IS BEGIN y <= “000” WHEN x=”0000 0001” ELSE

“001” WHEN x=”0000 0010” ELSE “010” WHEN x=”0000 0100” ELSE “011” WHEN x=”0000 1000” ELSE “100” WHEN x=”0001 0000” ELSE “101” WHEN x=”0010 0000” ELSE “110” WHEN x=”0100 0000” ELSE “111” WHEN x=”1000 0000” ELSE “ZZZ” ; end Behavioral ;

Dataflow modeling: entity encoder1 is Port ( i : in STD_LOGIC_VECTOR (7 downto 0);

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o : out STD_LOGIC_VECTOR (2 downto 0)); end encoder1; architecture Behavioral of encoder1 is begin o(2)<=i(4) or i(5) or i(6) or i(7); o(1)<= i(2) or i(3) or i(6) or i(7); o(0)<= i(1) or i(3) or i(5) or i(7); end Behavioral; Structural modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encc is Port ( i : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end encc; architecture Behavioral of encc is component or1 is Port ( a,b,c,d : in STD_LOGIC; e : out STD_LOGIC); end component; begin x1:or1 port map(i(1),i(3),i(5),i(7),y(0)); x2:or1 port map(i(2),i(3),i(6),i(7),y(1)); x3:or1 port map(i(4),i(5),i(6),i(7),y(2)); end Behavioral;

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OUTPUT WAVEFORM:

RESULT : Thus a VHDL program for 8:3 encoder was written in all the modeling and simulated using xilinx software.

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Ex No. 10 3:8 DECODER Date:

AIM: To write a VHDL coding for a 3:8 decoder using all the three modeling and to simulate using xilinx. TOOLS REQUIRED:

1.Xilinx ISE 8.li 2.ModelSim Simulator

LOGIC DIAGRAM:

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PROGRAM: Structural modeling: Library ieee; Use ieee.std_logic_1164.all; Entity decoder is Port(p:in std_logic_vector(2 downto 0); q:in std_logic; r:out std_logic_vector(7 downto 0)); end decoder; architecture decoder of decoder is component not1 is port (a:in std_logic; b:out std_logic); end component; component and1 is port(c,d,e,f:in std_logic; g:out std_logic); end component; signal w:std_logic_vector(2 downto 0); begin z1:not1 port map(p(0),w(0)); z2:not1 port map(p(1),w(1)); z3:not1 port map(p(2),w(2)); z4:and1 port map(q,w(2),w(1),w(0),r(0)); z5:and1 port map(q,w(2),w(1),p(0),r(1)); z6:and1 port map(q,w(2),p(1),w(0),r(2)); z7:and1 port map(q,w(2),p(0),p(1),r(3)); z8:and1 port map(q,w(0),w(1),p(2),r(4)); z9:and1 port map(q,p(0),w(1),p(2),r(5)); z10:and1 port map(q,w(0),p(1),p(2),r(6)); z11:and1 port map(q,p(0),p(1),p(2),r(7)); end decoder; Behavioral modeling : library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; entity decoder IS port ( x : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; y : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )); end decoder ;

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architecture decoder of decoder is begin with x select y <= ”00000001” WHEN “000”,

”00000010” WHEN “001”, ”00000100” WHEN “010”, ”00001000” WHEN “011”, ”00010000” WHEN “100”, ”00100000” WHEN “101”, ”01000000” WHEN “110”, ”10000000” WHEN “111”, “ZZZZ ZZZZ” WHEN OTHERS ;

end decoder ; Data flow modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder12 is Port ( i : in STD_LOGIC_VECTOR (2 downto 0); o : out STD_LOGIC_VECTOR (7 downto 0); n : inout STD_LOGIC_VECTOR (2 downto 0)); end decoder12; architecture Behavioral of decoder12 is begin n(2)<=not i(2); n(1)<=not i(1); n(0)<=not i(0); o(0)<=n(2) and n(1) and n(0); o(1)<=n(2) and n(1) and i(0); o(2)<=n(2) and i(1) and n(0); o(3)<=n(2) and i(1) and i(0); o(4)<=i(2) and n(1) and n(0); o(5)<=i(2) and n(1) and i(0); o(6)<=i(2) and i(1) and n(0); o(7)<=i(2) and i(1) and i(0); end Behavioral;

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OUTPUT WAVEFORM:

RESULT: The 3:8 decoder program was written in all the modeling and simulated using xilinx.

45

Ex No. 11 MULTIPLIER (8X8)

Date:

AIM : To write a VHDL program for multiplier using dataflow modeling and simulate it using xilinx software. TOOLS REQUIRED :


PROGRAM : LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; USE ieee.std_logic_unsigned.all ; ENTITY multiplier IS PORT ( a, b : IN UNSIGNED ( 7 DOWNTO 0 ); mul : OUT UNSIGNED ( 15 DOWNTO 0 )); END multiplier ; ARCHITECTURE multiplier OF multiplier IS BEGIN mul <= a * b ; END multiplier ;

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OUTPUT WAVEFORM:

RESULT :

Thus a VHDL program for multiplier was written in dataflow modeling and simulated using xilinx software.

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Ex No. 12 FLIP FLOPS

Date:

AIM :

To write a VHDL program for D,RS,JK and T flip flops using behavioral modeling and simulate it using xilinx software. TOOLS REQUIRED :


LOGIC DIAGRAM:

PROGRAM: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dff is port(d :IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; qbar:OUT STD_LOGIC; q :BUFFER STD_LOGIC); end dff; architecture Behavioral of dff is begin process(d,clk,rst) begin

48

if(rst=’1’) then q<=0; elsif(clk ‘event and clk=’1’) then q<=d; end if; end process; qbar<=not q; end behavioral; OUTPUT WAVEFORM:

SR FLIP FLOP LOGIC DIAGRAM:

PROGRAM: Library ieee; Use ieee.std_logic_1164.all;

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Entity srff is Port(sr:in std_logic_vector(1 downto 0); Clk:in std_logic; Q,qbar:out std_logic); End srff; Architecture srff of srff is Begin Process(sr,clk) Variable temp : std_logic:=’0’; Begin If (clk’event and clk=’1’)then Case sr is When “00” =>temp:=temp; When “01”=>temp:=’0’; When “10”=>temp:=’1’; When “11”=>temp:=’X’; When others=>NULL; End case; End if; q<=temp; qbar<=not temp; end process; end srff; OUTPUT WAVEFORM:

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JK FLIP FLOP LOGIC DIAGRAM:

PROGRAM: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity jkff is port(jk : IN STD_LOGIC_VECTOR(1 DOWNTO 0); rst: IN STD_LOGIC; clk: IN STD_LOGIC; q :OUT STD_LOGIC); end jkff; architecture behavioral of jkff is begin process(jk,rst,clk) variable y:STD_LOGIC; begin if(rst=’1’) then y:=’0’; elsif(clk ‘event and clk=’1’) then case jk is when “00” => y:=y; when “01” => y:=’0’; when “10” => y:=’1’; when “11” => y:= NOT y; when others => NULL; end case; end if; q<=y; end process; end behavioral;

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OUTPUT WAVEFORM:

T FLIP FLOP LOGIC DIAGRAM:

PROGRAM: Library ieee; Use ieee.std_logic_1164.all; Entity tff is Port(t,clk:in std_logic; q:buffer std_logic:=’0’; qbar:out std_logic); end tff; architecture tff of tff is begin

52

process(t,clk) begin if(clk’event and clk=’1’)then if(t=’0’)then q<=q; else q<=not q; end if; end if; end process; qbar<=not q; end tff; OUTPUT WAVEFORM:

RESULT:

Thus a VHDL program for D, RS, JK and T flip flop was written using behavioral modeling and simulated using Xilinx software.

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Ex No. 13 COUNTERS Date:

AIM:

To write a program for counters using behavioral modeling and simulate it using Xilinx software. TOOLS REQUIRED:


LOGIC DIAGRAM:

PROGRAM: Upcounter: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity count is port(clk: IN STD_LOGIC; rst: IN STD_LOGIC; count:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); end count; architecture behavioral of count is begin process(clk,rst)

54

variable temp:STD_LOGIC_VECTOR(2 DOWNTO 0); begin if(rst=’1’) then temp=”000”; elsif(clk ‘event and clk=’1’) then temp:= temp+1; end if; count<=temp; end processs; end behavioral; OUTPUT WAVEFORM:

Down counter: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count is port(rst,clk:in std_logic; q:buffer std_logic_vector(3 downto 0)); end count; architecture count1 of count is begin process(clk,rst,q)

55

begin if(clk'event and clk='1') then if(rst='0') then q<=q-1; elsif(rst='1')then q<="1111"; end if; end if; end process; end count1; updown counter: Library ieee; Use ieee.std_logic_1164.all; Entity ctr is Port(clk,rst,sel:in std_logic; q:out std_logic_vector(2 downto 0)); End ctr; Architecture behavioral of ctr is Begin Process (clk,rst,sel) Variable count:std_logic_vector(2 downto 0):=”000”; Begin If(sel=’0’)then If(rst=’1’)then Count:=count+1; End if; q<=count; End if; If(sel=’1’)then If(rst=’1’) Count:=count-1; End if; q<=count; End if; End process; End behavioral;

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OUTPUT WAVEFORM:

RESULT: Thus the program for counter is written using Behavioral modeling and simulated using Xilinx software.

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Ex No. 14 SHIFT REGISTERS

Date:

AIM: To write a VHDL program for shift register using behavioral modeling and simulate using Xilinx software. TOOLS REQUIRED:


SISO

LOGIC DIAGRAM:

Din a b c Dout PROGRAM: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity sh-reg is port(clk: IN STD_LOGIC ; din: IN STD_LOGIC; dout:OUT STD_LOGIC ); end sh-reg; architecture behavioral of sh-reg is SIGNAL a,b,c:BIT; begin process(clk) begin

D FF

D FF

D FF

D FF

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if(clk ‘event and clk=’1’) then a<=din; b<=a; c<=b; dout<=c; end if; end process; end behavioral; OUTPUT WAVEFORM:

SIPO LOGIC DIAGRAM:

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PROGRAM: Library ieee; Use ieee.std_logic_1164.all; Entity sipo is Port(din,clk,rst:in std_logic; a,b,c:buffer std_logic; dout:out std_logic); end sipo; archictecture Behavioral of sipo is begin process(clk,rst) begin if(rst=’1’)then a<=’0’; b<=’0’; c<=’0’; dout<=’0’; elsif(clk’event and clk=’1’)then dout<=c; c<=b; b<=a; a<=din; endif; end process; end Behavioral; OUTPUT WAVEFORM:

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PIPO LOGIC DIAGRAM:

PROGRAM: Library ieee; Use ieee.std_logic_1164.all; Entity pipo is Port(a:in std_logic_vector(3 downto 0); Clk,rst:in std_logic; b:out std_logic_vector(3 downto 0)); End pipo; Architecture Behavioral of pipo is Component dff Port(d,c,r:in std_logic; q: out std_logic); end component; begin z1:dff port map(a(0),clk,rst,b(0)); z2:dff port map(a(1),clk,rst,b(1)); z3:dff port map(a(2),clk,rst,b(2)); z4:dff port map(a(3),clk,rst,b(3)); end Behavioral;

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OUTPUT WAVEFORM:

RESULT:

Thus the VHDL program for shift registers was written in behavioral modeling and simulated using Xilinx software.

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Ex No. 15 FREQUENCY DIVIDER Date:

AIM: To write a VHDL program for frequency divider using behavioral modeling and simulate using Xilinx. TOOLS REQUIRED:

1.Xilinx ISE 8.li 2.ModelSim Simulator

LOGIC DIAGRAM:

PROGRAM: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity fd is port(clk: IN STD_LOGIC; rst: IN STD_LOGIC; out :BUFFER STD_LOGIC); end fd; architecture Behavioral of fd is begin process(clk,rst) variable count: INTEGER RANGE 0 to 7; begin if(rst=’1’) then out<=0;

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elsif(clk ‘event and clk=’1’) then count:= count +1; end if; if(count=3) then out<=NOT out; count:=0; end if; end process; end behavioral; OUTPUT WAVEFORM:

RESULT:

Thus the VHDL program for frequency divider was written in behavioral modeling and simulated using Xilinx software.

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Ex No. 16 CMOS INVERTER

Date:

AIM: To implement and study the transient & DC analysis of CMOS inverter using Tspice simulator TOOLS REQUIRED:

1. Tanner EDA 2. Tspice Simulator

CIRCUIT DIAGRAM: Transient Analysis:

DC Analysis:

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PROGRAM: For Transient Analysis: * Main circuit: Module0 M1 Output Input Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 Output Input Vdd Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u .include "C:\Documents and Settings\Administrator\Desktop\Tanner\TSpice70\models\ml2_125.md" v1 vdd gnd 5 v2 Input gnd bit ({0101}) .tran 10n 40n .print tran Output Input * End of main circuit: Module0 For DC Analysis: * Main circuit: Module0 M1 N2 N6 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 N2 N6 Vdd Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u R3 N2 Gnd 50k TC=0.0, 0.0 v4 N6 Gnd 5.0 .include "C:\Documents and Settings\Administrator\Desktop\Tanner\TSpice70\models\ml2_125.md" v1 vdd gnd 5 .dc v4 0 5 .01 .print v4 v(N6)v(N2) * End of main circuit: Module0

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OUTPUT WAVEFORM: Transient Analysis:

DC Analysis:

RESULT:

Thus the CMOS inverter circuit for the transient & the DC analysis were implemented and studied using Tspice simulator.

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Ex No. 17 CMOS NAND

Date:

AIM: To implement and study the transient & DC analysis of CMOS NAND gate using Tspice simulator. TOOLS REQUIRED:


CIRCUIT DIAGRAM: CMOS NAND Transient Analysis:

DC Analysis:

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PROGRAM: For Transient Analysis: * Main circuit: Module0 M1 N1 A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 Output B N1 N1 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 Output A Vdd Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u M4 Output B Vdd Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u .include "C:\Documents and Settings\Administrator\Desktop\Tanner\TSpice70\models\ml2_125.md" v1 vdd gnd 5 v2 A gnd bit ({0011}) v3 B gnd bit ({0101}) .tran 10n 40n .print tran A B Output * End of main circuit: Module0 For DC Analysis: * Main circuit: Module0 M1 N6 N3 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 N4 N3 N6 N6 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 N4 N3 Vdd Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u M4 N4 N3 Vdd Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u R5 N4 Gnd 50k TC=0.0, 0.0 v6 N3 Gnd 5.0 .include "C:\Documents and Settings\Administrator\Desktop\Tanner\TSpice70\models\ml2_125.md" v1 vdd gnd 5 .dc v6 0 5 .01 .print dc v6 v(N3) v(N4) * End of main circuit: Module0

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DC Analysis:

RESULT:

Thus the transient & the DC analysis for CMOS NAND circuit is implemented and studied using Tspice simulator.

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Ex No. 18 CMOS NOR

Date:

AIM: To implement and study the transient & DC analysis of CMOS NOR gate using Tspice simulator. TOOLS REQUIRED:

Tanner EDA Tspice Simulator

CMOS NOR: Transient Analysis:

DC Analysis:

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PROGRAM: For Transient Analysis: * Main circuit: Module0 M1 Gnd N9 op Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 op A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 Vdd B N3 Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u M4 op A N3 Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u .include "H:\Tanner\models\ml2_125.md" v1 vdd gnd 5 v2 A gnd bit {(0011)} v3 B gnd bit ({0101}) .tran 10ns 40ns .print tran A B op * End of main circuit: Module0 For DC Analysis: * Main circuit: Module0 M1 N7 N3 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 Gnd N13 N7 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 N7 N3 N1 Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u M4 Vdd N3 N1 Vdd PMOS L=2u W=66u AD=66p PD=24u AS=66p PS=24u R5 N7 Gnd 50k TC=0.0, 0.0 v6 N3 Gnd 5.0 .include "H:\Tanner\models\ml2_125.md" v1 vdd gnd 5 .dc v6 0 5 0.01 .print dc v(N3) v(N7) * End of main circuit: Module0

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DC Analysis:

RESULT:

Thus the transient & the DC analysis for CMOS NOR circuit is implemented and studied using Tspice simulator.

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Ex No. 19 NMOS OR

Date:

AIM: To implement and study the transient & DC analysis of NMOS OR gate using Tspice simulator. TOOLS REQUIRED:


Transient analysis:

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PROGRAM: * SPICE netlist written by S-Edit Win32 7.00 * Written on Apr 1, 2011 at 16:16:30 * Waveform probing commands .probe .options probefilename="nmos orgate.dat" + probesdbfile="C:\Tanner\S-Edit\nmos orgate.sdb" + probetopmodule="Module0" * Main circuit: Module0 .include "C:\Tanner\models\ml2_125.md" M1 op a a Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 op b b Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u v1 a gnd bit({0010}) v2 b gnd bit({0101}) .tran 10n 40n .print tran a b op * End of main circuit: Module0 OUTPUT WAVEFORM:

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RESULT:

Thus the transient & the DC analysis for NMOS OR circuit is implemented and studied using Tspice simulator.

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Ex No. 20 NMOS XNOR

Date:

AIM: To implement and study the transient & DC analysis of NMOS XNOR gate using Tspice simulator. TOOLS REQUIRED:


Transient analysis:

PROGRAM: * SPICE netlist written by S-Edit Win32 7.00 * Written on Apr 1, 2011 at 16:31:19 * Waveform probing commands .probe .options probefilename="sedit.dat" + probesdbfile="q.sdb" + probetopmodule="Module0"

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* Main circuit: Module0 M1 op a b Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 op abar bbar Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u v1 a gnd bit ({0101}) v2 abar gnd bit ({1010}) v3 b gnd bit ({0110}) .include "C:\Tanner\models\ml2_125.md" v4 bbar gnd bit ({1001}) .tran 10n 40n .print tran a b op * End of main circuit: Module0 OUTPUT WAVEFORM:

78

RESULT:

Thus the transient & the DC analysis for NMOS OR circuit is implemented and studied using Tspice simulator.

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Ex No. 21 D LATCH Date:

AIM:

To implement and study the transient analysis of Dlatch using Tspice simulator. TOOLS REQUIRED:


CIRCUIT DIAGRAM:

PROGRAM: * Main circuit: Module0 M1 op N9 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 N9 clk q N11 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 q op Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M4 N9 clk ip1 N8 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M5 op N9 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M6 q clkbar N9 N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

80

M7 q op Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M8 N9 clkbar ip1 N5 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u .include "C:\Tanner\models\ml2_125.md" v1 vdd gnd 5 v2 clk gnd BIT ({1010}) v3 clkbar gnd BIT ({0101}) v4 ip1 gnd BIT ({1010}rt=0.01n ft=0.01n) .tran 10n 40n .print ip1 q op *End of main circuit: Module0 OUTPUT WAVEFORM:

RESULT:

Thus the Dlatch circuit was implemented and studied using Tspice simulator.

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EX NO:22 DOWNLOADING 4 BIT ADDER TO KIT

DATE: AIM To download the simulated 4 bit adder program into spartan2 kit and to check using DIP switches and LED’s. PROCEDURE

• Start Xilinx project navigator using desktop shortcut. • In the project navigator, go to file - > new project - > select device (family

spartan2 device XCS200, package PQ208).

• Click on the symbol of FPGA device and then right click on the new source - > VHDL module - > give name of the project - > define ports - > finish.

• Generate VHDL code for the given program. • Check syntax and remove errors. • Simulate the design using modelsim. • Synthesis the design. • Double click on the synthesis process window after synthesis is completed

successfully. • Write the user constrain file where in the FPGA pins are locked as per

spartan2 hardware. • Save bus delimiter window will open. Set the option to VHDL default.

Click ok. Close the window. • Run Xilinx implement tool by double clicking unit. • Double click to generate programming file, this will generate a bit stream;

now connect the data cable to kit. • Double click on configure device to download the bit stream and impact

window open select boundary scan downloading occurs a window called “assign” new configuration file opens. In that click your counter Xilinx design program property window opens. Program succeeded.

• Apply the input through kit switches and output will be displayed on LED’s.

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

82

entity adder is Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0); d : in STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0); cy : out STD_LOGIC); end adder; architecture Behavioral of adder is signal c:std_logic_vector(4 downto 0); begin c(0)<=d; L1:for i in 0 to 3 generate s(i)<=a(i)xor b(i) xor c(i); c(i+1)<=((a(i) and b(i)) or (b(i) and c(i)) or (c(i) and a(i))); end generate L1; cy<=c(4); end Behavioral;

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PIN ASSIGNMENTS: PORT NAME

PORT NUMBER

Input: A0 A1 A2 A3 B0 B1 B2 B3 Cin Output: Sum0 Sum1 Sum2 Sum3 Cout

P3 P4 P5 P6 P9 P10 P20 P21 P22 P46 P47 P48 P49 P57

RESULT:

Thus the program 4 bit adder was simulated using Spartan2 kit and the output was verified

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EX NO:23 DOWNLOADING D-FLIP FLOPTO KIT

DATE: AIM To download the simulated D-flip flop program into spartan2 kit and to check using DIP switches and LED’s.

PROCEDURE











PROGRAM: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dff is port(d :IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC;

85

qbar:OUT STD_LOGIC; q :BUFFER STD_LOGIC); end dff; architecture Behavioral of dff is begin process(d,clk,rst) begin if(rst=’1’) then q<=0; elsif(clk ‘event and clk=’1’) then q<=d; end if; end process; qbar<=not q; end behavioral;


PORT NUMBER

Input: D Clk reset Output: Q Qb

P3 P80 P154 P46 P47

86

RESULT:

Thus the program D-flip flop was simulated using Spartan2 kit and the output was verified.

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EX NO:24 IMPLEMENTATION OF REAL CLOCK

DATE: AIM To download the simulated real time clock program into spartan2 kit and to check using DIP switches and LED’s. PROCEDURE











PROGRAM library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity realtime is

88

Port ( sgout : out STD_LOGIC_VECTOR (07 downto 0); dis : out STD_LOGIC_VECTOR (05 downto 0); load : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC); end realtime; architecture Behavioral of realtime is SIGNAL sec1_rg, sec2_rg, min1_rg, min2_rg, hr1_rg, hr2_rg: std_logic_vector(3 downto 0); SIGNAL pulsegen: std_logic_vector(21 downto 0); SIGNAL cnk2: std_logic_vector(2 downto 0); SIGNAL mout: std_logic_vector (3 downto 0); SIGNAL sgout_rg:std_logic_vector(7 downto 0); SIGNAL dis_sig: std_logic_vector(5 downto 0); SIGNAL sec1, sec2, min1, min2, hr1, hr2: std_logic_vector (3 downto 0); SIGNAL tc1, tc2, tc3, tc4, tc5, tc6, enable: std_logic; begin --*************************** Pulse Generator ****************** fsm1: PROCESS (clk , reset ) begin if (reset = '1') THEN pulsegen <= (others => '0'); else if ((clk'event) and (clk = '1' )) THEN if (pulsegen = "1111010000100100000000") THEN pulsegen <= (others => '0'); else pulsegen <= pulsegen + 1; end if; end if; end if; end process fsm1; --Enable signal to generate 1-sec pulse for sec1 counter enable <= '1' when (pulsegen = "1111010000100100000000")else '0' ; --enable signal for sec1 counter --*************************** Second_cntr1 ****************** fsm2: PROCESS (clk , reset )

89

begin if (reset = '1') THEN sec1_rg <= (others => '0'); else if (clk'event) and (clk = '1' ) THEN if (load = '1') THEN sec1_rg <= "0100"; else if (enable = '1') THEN if (sec1_rg = "1001") THEN sec1_rg <= "0000"; else sec1_rg <= sec1_rg + 1; end if; end if; end if; end if; end if; end process fsm2; sec1 <= sec1_rg; --------------------tc1 signal to start sec2 counter--------------------------- tc1 <= '1' when (sec1_rg = "1001") AND (enable = '1')else '0'; --*************************** Second_cntr2 ****************** fsm3: PROCESS (clk , reset ) begin if (reset = '1') THEN sec2_rg <= (others => '0'); else if (clk'event) and (clk = '1' ) THEN if (load = '1') THEN sec2_rg <= "0100"; else if (tc1 = '1') THEN if (sec2_rg = "0101") THEN sec2_rg <= "0000"; else sec2_rg <= sec2_rg + 1; end if; end if;

90

end if; end if; end if; end process fsm3; sec2 <= sec2_rg; ---------------------------tc2 signal to start min1 counter------------------- tc2 <= '1' when (sec2_rg = "0101") AND (tc1 = '1') else '0'; ----************************ Minute_cntr1 ************************* fsm4: PROCESS (clk , reset ) begin if (reset = '1') THEN min1_rg <= (others => '0'); else if (clk'event) and (clk = '1' ) THEN if (load = '1') THEN min1_rg <= "0100"; else if (tc2 = '1') THEN if (min1_rg = "1001") THEN min1_rg <= "0000"; else min1_rg <= min1_rg + 1; end if; end if; end if; end if; end if; end process fsm4; min1 <= min1_rg; --------------------------tc3 signal to start min2 counter-------------------- tc3 <= '1' when (min1_rg = "1001") AND (tc2 = '1')else '0'; ----************************ Min_cntr2 ************************* fsm11: PROCESS (clk , reset ) begin if (reset = '1') THEN min2_rg <= (others => '0'); else if (clk'event) and (clk = '1' ) THEN

91

if (load = '1') THEN min2_rg <= "0100"; else if (tc3 = '1') THEN if (min2_rg = "0101") THEN min2_rg <= "0000"; else min2_rg <= min2_rg + 1; end if; end if; end if; end if; end if; end process fsm11; min2 <= min2_rg; -----------------------tc4 signal to start hr1 counter-------------------------- tc4 <= '1' when (min2_rg = "0101") AND (tc3 = '1')else '0'; ----************************ Hour_cntr1 ************************* fsm5: PROCESS (clk , reset ) begin if (reset = '1') THEN hr1_rg <= (others => '0'); else if (clk'event) and (clk = '1' ) THEN if (load = '1') THEN hr1_rg <= "0001"; else if (tc6 = '1') THEN hr1_rg <= "0000"; else if (tc4 = '1') THEN if (hr1_rg = "1001") THEN hr1_rg <= "0000"; else hr1_rg <= hr1_rg + 1; end if; end if; end if; end if; end if;

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end if; end process fsm5; hr1 <= hr1_rg; -----------------------tc5 signal to start hr2 counter-------------------------- tc5 <= '1' when (hr1_rg = "1001") AND (tc4 = '1')else '0'; --------------------------tc6 signal to reset at 23:59:59-------------------------- tc6 <= '1' when (hr2_rg = "0010") AND (hr1_rg = "0011") AND (tc4 = '1')else '0'; ----************************ Hour_cntr2 ************************* fsm6: PROCESS (clk , reset ) begin if (reset = '1') THEN hr2_rg <= (others => '0'); else if (clk'event) and (clk = '1' ) THEN if (load = '1') THEN hr2_rg <= "0000"; else if (tc6 = '1') THEN hr2_rg <= "0000"; else if (tc5 = '1') THEN if (hr2_rg = "0010") THEN hr2_rg <= "0000"; else hr2_rg <= hr2_rg + 1; end if; end if; end if; end if; end if; end if; end process fsm6; hr2 <= hr2_rg; fsm7: PROCESS (pulsegen(9) , reset ) begin

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if (reset = '1') THEN cnk2 <= (others => '0'); else if (pulsegen(9)'event) and (pulsegen(9) = '1' ) THEN if (cnk2 = "101") THEN cnk2 <= "000"; else cnk2 <= cnk2 + 1; end if; end if; end if; end process fsm7; fsm8: PROCESS (cnk2,sec1,sec2,min1,min2,hr1,hr2 ) begin case cnk2 is when "000" => mout <= sec1; when "001" => mout <= sec2; when "010" => mout <= min1; when "011" => mout <= min2; when "100" => mout <= hr1; when "101" => mout <= hr2; when others => NULL; end case; end PROCESS fsm8; fsm9: PROCESS (mout ) begin case mout is when "0000" => sgout_rg <= "11000000"; when "0001" => sgout_rg <= "11111001"; when "0010" => sgout_rg <= "10100100"; when "0011" => sgout_rg <= "10110000"; when "0100" => sgout_rg <= "10011001"; when "0101" => sgout_rg <= "10010010"; when "0110" => sgout_rg <= "10000010"; when "0111" => sgout_rg <= "11111000"; when "1000" => sgout_rg <= "10000000"; when "1001" => sgout_rg <= "10011000"; when others => NULL; end case;

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end PROCESS fsm9; fsm10: PROCESS (cnk2 ) begin case cnk2 is when "000" => dis_sig <= "111110"; when "001" => dis_sig <= "111101"; when "010" => dis_sig <= "111011"; when "011" => dis_sig <= "110111"; when "100" => dis_sig <= "101111"; when "101" => dis_sig <= "011111"; when others => NULL; end case; end PROCESS fsm10; sgout <= NOT sgout_rg; dis <= NOT dis_sig; end Behavioral;

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PORT NUMBER

Input: Clk Rst 7 segment a b c d e f g Display 0 1 2 3 4 5 Load

P80 P154 P125 P127 P129 P132 P133 P134 P136 P112 P113 P114 P120 P121 P122 P3

RESULT: Thus the program real time clock was simulated using Spartan2 kit and the output was verified.

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