VLSI for Signal Processing
Transcript of VLSI for Signal Processing
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KEEE 463
VLSI
Signal Processing
Laboratory
KECE 463
VLSI Design and Experiment
Lecture 1
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Course Format
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Teaching Assistant
Ju-seong Lee ( [email protected])Office : Engineering Building Annex ( ) 501Phone : (02)3290-3669
Lecturer : Prof. Jongsun Park
Email : [email protected] : Innovation Building ( ) 716 BPhone : (02) 3290-4827
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Course Format
English Class !
Lecture
Time: Wednesday 2:00 ~ 6:00 PM
Place: Convergence Building 109
LAB: Engineering Building II 313
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Text Book : Verilog HDL: A Guide to Digital Design
and Synthesis, 2nd Edition 2003 By Samir PalnitkarPublisher: Prentice Hall PTR, ISBN: 0-13-044911-3
Grading :Have to do the HW and projects.
Homework : 35 % - must attend the class and LAB.
Exam : 20 %Project 1 : 20 % Project 2 : 25 %
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Course Format
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Course Objectives For the students to get to know
Current Digital VLSI Design Flow For the students to get familiar with
Industry Grade Design Tools For the students to have the concepts of
Delay, Area, Power of Digital Design
Prerequisite Course : Digital System
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Course Format Lecture goes First
Experiment will follow
LAB : Embedded system design LAB
Engineering Building 313CAD tools are available. (15 copies)
Homework and Projects are veryimportant !
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What is the course about ?
Why ?
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Electronic World
Courtesy of ISSCC 2013 Plenary
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Electronic World
What are the REAL basics ?
Transistors,ICs (Integrated Circuits)
Those are what thisElectronic Circuit
course is about.
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HISTORY : Transistor Size ScalingFrom Electronics to Micro-electronics
to Nano-electronics ... to ?
Electronics systemsused vacuum tubes
Electronics systemsused
Transistors 1940s
Microelectronics systems1960s
10-6 10-9
Nano
First Transistor, Bell Labs 1948
BJT CMOS
vacuum tube
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The Integrated Circuit (IC)An IC consists of interconnected electronic components in a single piece
(chip) of semiconductor material.
The first planar IC
(actual size: 0.06 in. diameter)
In 1959, Robert Noyce (FairchildSemiconductor) demonstrated an IC madein silicon using SiO2 as the insulator and Alfor the metallic interconnects.
In 1958, Jack S. Kilby (TexasInstruments) showed that it was possible tofabricate a simple IC in germanium.
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Central Processing Units (CPU)
Intel 4004 (1971)
First Single Chip Processorwith 2250 Transistors
Intel 8080(1975, 4500 tr)
5 Mhz
Intel 8086(1978, 29,000 tr)
10 Mhz
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From a Few, to Billions The degree of integration has increased at an exponential pace over
the past 40 years. IC performs very complex tasks.
The number of devices on a chip doublesevery ~18 months, for the same price.
Moores Law still holds today.
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1971
1973
1975
1977
1979
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
Intel CPU DRAM
4044
8080
8086
80486
PentiumPentiumII
80286
80386
Pentium III & IV
1K4K
16K
64K
256K
1M
4M
16M
64M
256M
1 Gb
300mm Si wafer
Intel Pentium4 Processor
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From a Few, to Billions
45nm processor
(Nehalem)Courtesy of Intel
45nm 6-Core Xeon CPU
8-Core Enterprise Xeon CPU
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Semiconductor Impacts
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Application Processor
Courtesy of Samsung
PC era Smart Device
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Application Processor Trend
Courtesy of ISSCC 2013 Plenary
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ASIC SoC
Single Chip
Digital & Analog Components
From ASIC, to SoC
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Transistor Size Scaling
From Electronics to Micro-electronics
to Nano-electronics ... to ?
Electronics systemsused vacuum tubes
Electronics systemsused
Transistors 1940s
Microelectronics systems1960s
10-6 10-9
Nano
First Transistor, Bell Labs 1948
BJT CMOS
vacuum tube
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Process Technologies
< from ISSCC 2012 plenary >
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Process Technologies
< from ISSCC 2012 plenary >
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Tri-gate Advantages
[ on-current ]
[ off-current ]
< from ISSCC 2012 plenary >
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How can we design
those chips ?
Why HDL ?
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VLSI Design Methodology
Full Custom
Design Method
SystemSpecification
Schematic
Optimization
Layout
C or Matlab
Analog
High performance
Digital Datapath
Memory
Register f iles
in1 in2
o
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VLSI Design Methodology
Semi Custom
Design Method
SystemSpecification
HDLDescription
C or Matlab
Verilog
Most of Digital circuitsSynthesis
Place & Routing
Design
Compiler
P & R
tool
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Semi-Custom Design !
Memory Wrapper
FFT Memory
FFT
DIRS
CABLE
VIT
PAL
CFE DTL
MDT
PE
SBDCE
SPD
SPD
DTL
SIF
TPS
Uanalog
DAC
TEST
MD
CFE
MDT ROM
SFT
SBD
DIRS
DIRS
VITRD ROMVIT CE
DTLDTL
Digital TVBasebandProcessor
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KEEE 485:VLSI Design & Experiment
Learn about Semi-Custom Design Methodology
SystemSpecification
HDLDescription Synthesis
Place &Routing
For each K loopif ( Ni is the smallest)
Decrease Ni byend if
Restore NiEnd For
No TimingNo Clock
verilog
always @ (posedge clk )begin
b
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What is
Gooood Design?
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Design Issue
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Chip Area = > Money $$
300mm Si wafer
Fabrication cost / chip
Smaller System
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Lead Microprocessors frequency doubles every 2 years
P6
Pentium proc486
38628680868085
8080
80084004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Frequency(Mhz)
Doubles every
2 years
Courtesy, Intel
Trend - Frequency in Microprocessor
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Design Issue
Power Consumption
Year
Powerdensity
(W/cm2)
Source : Intel
Battery Life
System Reliability
(System down ?)
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Design Issue
To reduce Power Consumption
Low Power VLSI Design is required
Thermal gradient Simulation
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VLSI Design Why ? : SummaryTransistor size, Integrated Circuit
Transistor size scale down Micro > NanoIntegration Density increases Billions of Transistors
Design Methodology ?
Full Custom, Semi-Custom Most of Chip area
Semi Custom Design Flow (need to learn before graduations)
VLSI Design IssuesArea , Power ConsumptionSoC trends
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Prerequisites ? Digital Systems (KEEE 207)
Q
D
in1
in2
o
D Q
clk
gates
Digital systems
Not a prerequisites but helpfulElectronic Circuits I BJT CMOS
delay
area
power
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Things to remember for
Verilog Design
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Basic Gates
in1
in2
o
Prerequisites
D Q
clk
NAND
NORINVMUX
XORDFFFADDHADD
ANDOR
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KEEE 485:VLSI Design & Experiment
Learn about Semi-Custom Design Methodology
SystemSpecification
HDLDescription Synthesis
Place &Routing
For each K loopif ( Ni is the smallest)
Decrease Ni byend if
Restore NiEnd For
No TimingNo Clock
verilog
always @ (posedge clk )begin
b
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RULE # 1When you design Verilog,
ALWAYS think about what is the HARDWARE is going to be ?
always @( )beginif (s == 1) out = a ;else out = b;
end
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Example 2
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always @( )begin
if (s == 1) out = a ;else out = 0;
end
ALWAYS Think about HARDWARE !
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Example 3
always @(posedge clk)begin
b
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Example 4
always @(posedge clk)begin
if (s == 1) out
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RULE # 2
When you design Verilog,
ALWAYS draw Timing Diagram
always @(posedge clk )begin
count
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Example 5
always @(posedge clk )begin
count
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Verilog Coding Tips : Summary
1. ALWAYS Think about the
HARDWARE !
2. Draw the Timing Diagram
When you design Verilog,