Vlsi Fabrication Gopu

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BASIC CMOSTECHNOLOGY

K.L.N .COLLEGE OF ENGINEERING

T.GOPU,ME(VLSI)/AP-2/DEPT.OF.EEE.


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CMOS VLSI Design0: Introduction Slide 2

Four main CMOS technologies:

1.N-WELL PROCESS.

2.P-WELL PROCESS. 3.TWIN TUB PROCESS. 4.SILICON ON INSULATOR.


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Major process steps of n-well process:

n-well maskused to create n-well or n-tub via ion-implantation or deposition/diffusion.


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active maskdefines areas where transistors arefabricated.


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Cont.

p-well maskused to produce channel-stop (p+diffusion), field oxide grown


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CONT..

poly maskused to etch poly patterns.


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n-plus mask (select mask) used to indicate thosethin-oxide areas and poly that are to implanted n+.

CONT..


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CMOS VLSI Design

CONT..

p-plus maskused to indicate those thin-oxide areasand poly that are to implanted p+.

0: Introduction Slide 8


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CMOS VLSI Design

CONT..

Surface is covered with SiO2and contact cutsmade.



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CMOS VLSI Design

CONT..

Metallization applied and etched using metal mask. The wafer is then passivated and opening to bond

pads are etched.



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CMOS Fabrication

CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or

etched Easiest to understand by viewing both top and

cross-section of wafer in a simplified manufacturingprocess


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Inverter Cross-section

Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

Y

GND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


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Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor

connection called Shottky Diode Use heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tap well tap

n+ p+


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Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor


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Detailed Mask Views

Six masks n-well Polysilicon

n+ diffusion p+ diffusion Contact Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well


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Fabrication Steps

Start with blank wafer Build inverter from the bottom up First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

p substrate


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Oxidation

Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2


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Photoresist

Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

p substrate

SiO2

Photoresist


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Lithography

Expose photoresist through n-well mask Strip off exposed photoresist

p substrate

SiO2

Photoresist


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Etch

Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist


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Strip Photoresist

Strip off remaining photoresist Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

p substrate

SiO2


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n-well

n-well is formed with diffusion or ion implantation Diffusion

Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

n well

SiO2


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Strip Oxide

Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

p substrate

n well


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Polysilicon

Deposit very thin layer of gate oxide < 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH

4)

Forms many small crystals called polysilicon Heavily doped to be good conductor

Thin gate oxide

Polysilicon

p substraten well


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Polysilicon Patterning

Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxide

Polysilicon

n well


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Self-Aligned Process

Use oxide and masking to expose where n+ dopantsshould be diffused or implanted

N-diffusion forms nMOS source, drain, and n-wellcontact

p substraten well


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N-diffusion

Pattern oxide and form n+ regions Self-aligned processwhere gate blocks diffusion Polysilicon is better than metal for self-aligned gates

because it doesnt melt during later processing

p substraten well

n+ Diffusion


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N-diffusion cont.

Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n wellp substrate

n+n+ n+


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N-diffusion cont.

Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+


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P-Diffusion

Similar set of steps form p+ diffusion regions forpMOS source and drain and substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+


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Contacts

Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact


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Metalization

Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

p substrate

MetalThick field oxide

n well

n+n+ n+p+p+p+

Metal


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CMOS VLSI Design

P-well process

Similar to n-well process except a p-wellis implanted rather than an n-well.

Produces n- and p-transistors that are

more balanced.

Transistors that reside in the nativesubstrate tend to have better

characteristics.

In general, p-devices are lower gain than

n-devices. Therefore, p-well process naturally

moderate the differences.



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CMOS VLSI Design

P-well process



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CMOS VLSI Design

Twin-tub process:



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CMOS VLSI Design

Twin-tub process

Allows independent optimization of gain, thresholdvoltage, etc. of n-type and p-type devices.

Both types of substrate contacts are REQUIRED inthis process.



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CMOS VLSI Design

It is also possible to create both a p-well and an n-well for the n-MOSFET's and p-MOSFETrespectively in the twin well or twin tub technology.

Such a choice means that the process is

independent of the dopant type of the startingsubstrate (provided it is only lightly doped).



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CMOS VLSI Design

Silicon-on-Insulator (SOI) has been under activeconsideration for the last many years.

SOI refers to placing a thin layer of silicon on top ofan insulator such as silicon oxide or glass.

The transistors would then be built on top of this thinlayer of SOI.

The basic idea is that the SOI layer will reduce thecapacitance of the switch, so it will operate faster.


CMOS Processing Technology


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CMOS VLSI Design

Silicon-On-Insulator (SOI) process:

Silicon-On-Insulator (SOI) process: Instead of silicon substrate, use an insulating

substrate. Silicon can be grown on:

Sapphire or SiO2which in turn has been grown on silicon.



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CMOS VLSI Design

CONT



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CMOS VLSI Design

Advantages: Closer packing of p- and n-transistors, due to

absence of wells. Absence of latch-up problems (to be discussed). Only "sidewall" areas of source and drain diffusions

contribute to parasitic junction capacitance, fasterdevices.

Leakage currents to substrate and adjacent devices

almost eliminated. Enhanced radiation tolerance.



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CMOS VLSI Design

DISADVANTAGES:

Disadvantages: No substrate diodes, inputs more difficult to protect. Device gains are lower, I/O structures must be

larger. Density of contemporary digital processes is actually

determined by number and density of metalinterconnection layers.

Sapphire and silicon on SiO2substrates areconsiderably more expensive.


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