VLSI Datapath Choices: Cell-Based Versus...
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Masterworks98 4/25/98 1 VLSI Datapath Choices: Cell-Based Versus Full-Custom Andrew Liang Ping Chang Concurrent VLSI Architecture Group Artificial Intelligence Laboratory Massachusetts Institute of Technology and Computer Systems Laboratory Stanford University
Transcript of VLSI Datapath Choices: Cell-Based Versus...
Masterworks98 4/25/98 1
VLSI Datapath Choices:Cell-Based Versus Full-Custom
Andrew Liang Ping ChangConcurrent VLSI Architecture Group
Artificial Intelligence LaboratoryMassachusetts Institute of Technology
andComputer Systems Laboratory
Stanford University
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Design Options
Standard-Cell
INCREASINGQualityCustomizationEffort
FPGA Standard-Cell Full-Custom
Lucent OR2C15A MIT Alewife A-1000 CMMU DEC ALPHA 21164
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Example: 0.25µm Technology
FPGA Standard-Cell Full-Custom
Xilinx XC4000CV25M T’s100MHz
< 500K Gates
IBM SA-1213.6M T’s (est)400MHz (est)
< 3400K Gates
Alpha KP2126415.2M T’s700MHz
Not Applicable
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Full-Custom Quality with Standard Cell Effort
l Limits of Cell-Based Datapathl Crafted-Cell Methodl Application Examples:
Microprocessor Register Fetch Stage64-bit Adder
Full-Custom vs Crafted-Cell vs Standard Cell
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Datapaths
l Structurally Regularl Composed of Bit-slicesl Apply operation to n-bitsl Examples: Register Files, Adders, Multipliers
.
..64b
RFADDERRF
Logical Physical
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MIT MAP Chip Design
l 64b Multi-ALU Processorl 6 IU’s, 1 FPU, 32KB Cachel 5M T’s - 2.7M Memory
2.3M Logicl Mix of Full-Custom and
Cell-based componentsl Complexity Similar to
HP PA8000 & Sun Ultra I
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Limits: Grids
Standard-Cell Full-Custom
POTENTIAL PENALTY: 16% - 21%
l Lose 1 X-track & 1 Y-trackX
Y
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Limits: N:P Transistor Ratio
Standard-Cell Full-Custom
l Datapaths Employ Smaller T’sl Datapaths are N-Dominated
AOI22 MUX2
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N:P Disparity
POTENTIAL PENALTY: 27%-54%
Library
Standard Cell
#Cells Ave CellArea (Χ )
% N-Trans
68
66Datapath
Ave T’s/Cell
8.5
9.0
2
95
149
N:P Ratio
39.4
48.9
1:1.54
1:1.04
Other Full Custom 50 13.0 266 43.9 1:1.33
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Gate Density (ρg) &Transistor Density(ρt)
l ρg - cell % dedicated to “gate”
l ρt - number of T’s per routing grid point
AOI22
Area = 60 grid points#T’s = 8
ρt = 0.1 T’s/grid
INV_16
Area = 108 grid points#T’s = 2
ρg = 20%
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Limits: Area Utilization
l Utilization AloneINSUFFICIENT
l Device InterconnectIMPORTANT
0%
5%
10%
15%
20%
25%
30%
AND
2 A
ND3
PLT
CH_C
ELL
AND
4 X
OR2
XNO
R2 C
KA_1
INV
_2 N
LTCH
_SCA
N P
DFF_
SCAN
NCK
A_1
NAN
D2 C
KA_2
INV
_4 N
AND3
NAN
D4 C
KA_4
AO
I21
BUF
_8 A
OI2
222
CKA
_8 A
OI2
2 I
NV_8
NCK
A_8
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
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Layout Efficiency: ηlayout
ηlayout = α β+ρt-max ρg-max
ρ t-cell ρg-cell
α
β
= 0.7
= 1.0
0.000.050.10
0.150.200.250.30
0.350.40
0% 10% 20% 30%
SRAM BIT_CELL
NCKA_8
(ρg-cell)%Fill
T’s/grid
(ρt-cell)
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Crafted-Cell Method
l Small Set of Module Specific Cells (<10)l Share INV’s, BUF’s, MUX’sl Reuse Cells Whenever Possiblel Custom Placementl Automated Routing
A Simplification of the Full-Custom Approach orAn Enhancement to Standard Cell Methods
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IRRDP Crafted-Cells
AREA GROWTH: 11% - 25%
l Aligned to Routing Gridl Explicit Pins
Pipeline LatchRegister BitRegister R/W
Full-Custom Crafted-Cell Full-Custom Crafted-Cell Full-Custom Crafted-Cell
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BIT-SLICE/FULL IRRDP
1x/1x 1.64x/1.64x 5.25x/14.5x
Standard-CellFull-Custom Crafted-Cell80 Different Cells 7 Different Cells 17 Different Cells
l 7 Specific vs 80 Custom Cellsl 7 Complex vs 17 Simple Cellsl Automated Placement
LOSES Structurel Bitslice > 97% Fill
Full < 33% Fill
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Area Growth Breakdown: +64%
l Growth in Width» +37% Within Cells» +2% Irregular Structures» +11% Additional Routing Tracks» +3% Well/Substrate Contacts
l Growth in Height» 1.07x (15 tracks/bit vs. 14 tracks/bit)
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Additional Experimental Results
Design
IRRDP
ADDSUB
Critical Path
Area
Critical Path
Area
Full-Custom Crafted-Cell Standard Cell
1450%
223%
440%(270%)
120% (167%)
100% 164%
111%
117%
174%
100%
100%
100%
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Conclusions
l Traditional Standard Cells Make Poor DatapathsToo Big, Too Few, Wrong Ratio!
l Crafted-Cells Overcome Traditional LimitsNear Full-Custom Quality w/ Standard Cell Effort!
l Crafted-Cells Successfully AppliedIRRDP, ADDSUB, & MAP chip!
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Acknowledgements - Full-Custom Baselines
l IRRDP layout - MCNCl ADDSUB design - Parag Gupta ‘96l ADDSUB layout - Cadence Spectrum Design
