VLSI Architectures and Rapid Prototyping Testbeds for Wireless … · 2005-06-16 · Rice...
Transcript of VLSI Architectures and Rapid Prototyping Testbeds for Wireless … · 2005-06-16 · Rice...
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1Rice University, 8 June 2005
Visiting Professor, CWC, University of Ouluand
Center for Multimedia Communication, www.cmc.rice.eduDepartment of Electrical and Computer Engineering
Rice University, Houston TX
Joseph R. Cavallaro
VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems
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2Rice University, 8 June 2005
OutlineOutline
Rice University CMC and University of Oulu CWCWireless Systems EvolutionBaseband Processor ChallengesApplication Specific Architectures⇒ Imagine Media Processor⇒ Transport Triggered Architectures
Testbed Systems⇒ LabVIEW FPGA, Xilinx System Generator⇒ Rice CMC Testbed⇒ Oulu CWC Elektrobit 4G Testbed
Summary
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3Rice University, 8 June 2005
Rice CMC and University of Oulu CWC Interaction
Rice CMC and University of Oulu CWC Interaction
Rice CMC and Oulu CWC Common Vision on Wireless Systems⇒ Algorithms, Architectures, Testbeds⇒ Communications, VLSI, Networks
Faculty and Student Exchange and Courses⇒ Wireless Systems Architecture
• Parallelism and FPGA Prototyping
Research Interaction⇒ WCDMA and WLAN Systems⇒ Beyond 3G Systems with TI and Nokia
Nokia Foundation Fellowship – Spring 2005
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4Rice University, 8 June 2005
Wireless Communication Architectures
Wireless Communication Architectures
Cellular Generation Evolution from 2G to 4G⇒ 4G (MC-CDMA/OFDM) Voice & 100 Mbps Data…
Wireless LAN Evolution⇒ 11 Mbps, 54 Mbps (802.11a,b,g), 100 Mbps….
VLSI Signal Processing Architectures are the Key⇒ Algorithms to Architectures⇒ DSP, ASIP, or ASIC⇒ Theory and Experimentation
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5Rice University, 8 June 2005
Channelestimation
Equalization
DetectionDecoding
Antenna
Informationbits
(to higherlayers)
RFunit A/D
Digital
Analog
+1
Communication System –Physical Layer Receiver
Communication System –Physical Layer Receiver
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6Rice University, 8 June 2005
MIMO Research ChallengesMIMO Research Challenges
Communication Algorithms – Coding StrategiesHigh Complexity Real-time Signal Processing –⇒ VLSI, FPGA, Application Specific Processors⇒ Reconfigurable Accelerators for Multiple StandardsNetwork Scheduling – Transit Access Points⇒ Multiple RF InterfacesExperimentation and Verification with Real-Time RF Hardware in CMC Lab⇒ Behnaam Aazhang, Ashutosh Sabharwal, Patrick Frantz,
Edward Knightly, Richard BaraniukContributions by: Sridhar Rajagopal, PredragRadosavljevic, Marjan Karkooti, and Patrick Murphy
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7Rice University, 8 June 2005
Challenges of Customization and Flexibility
Challenges of Customization and Flexibility
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8Rice University, 8 June 2005
Reconfigurable BasebandArchitectures
Reconfigurable BasebandArchitectures
Base Band
DSPFPGAASICsASIPs
HomeWLAN
Office HSWLAN
Mobile
Host
RF interface
RF interface
RF interface
CellularW-CDMA
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9Rice University, 8 June 2005
Very Large Scale Integration Signal Processing Architectures
Very Large Scale Integration Signal Processing Architectures
Multi-disciplinary ProcessMapping of Algorithms to ArchitecturesIdentify Datapath Blocks (Add / Mult)Identify Efficient Parallel ScheduleDesign & Simulate, Fabricate, TestFPGA for Prototype Baseband
3G Wireless Detector CircuitsDesigned at Rice
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10Rice University, 8 June 2005
Processors in Future Wireless Systems
Processors in Future Wireless Systems
ASIPs (Application Specific Instruction set Processors):Excellent Tradeoff between Efficiency of ASICs and Flexibility of DSPsImplementation of Special Function Units (SFUs) for CustomizationFlexible and Retargetable Compilation – Machine Description File
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11Rice University, 8 June 2005
System Design MethodologySystem Design Methodology
Algorithm Mapping to Parallel Architectures ⇒ Real-time data and sampling rates and the corresponding
area and time complexities
Configurable Mapping and Design Exploration⇒ Heterogeneous DSP and programmable application-
specific instruction (ASIP) processor architectures
Verification and Testbed Integration ⇒ Prototype implementation on programmable devices and
integration with RF units.
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12Rice University, 8 June 2005
ASIP Processor Design Exploration Strategies Example
ASIP Processor Design Exploration Strategies Example
Data-Parallel DSPs
+++***
+++***
+++***
Algorithmmapping:
Design of algorithms for
efficient mapping and performance
Architecturescaling:
Having designed the algorithms,
find a low power processor
Workloadadaptation:
Having designed the processor,
improve power at run-time
Sridhar Rajagopal (Imagine) and Predrag Radosavljevic (TTA)
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13Rice University, 8 June 2005
ASIP System Research ToolsASIP System Research Tools
Characterized by Machine Description File and Retargetable CompilerVLIW – type Data Parallel Systems
Imagine Streaming Media Processor – MIT/Stanford
Transport Triggered Architecture – Delft/Tampere
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14Rice University, 8 June 2005
Stream Processors : Multi-cluster DSPs (Micro’04)
Stream Processors : Multi-cluster DSPs (Micro’04)
+++***
InternalMemory
ILPMMX
Memory: Stream Register File (SRF)
VLIW DSP(1 cluster)
+++***
+++***
+++***
+++***
…ILPMMX
DP
Adapt clusters to DPIdentical clusters, same operations.Power-down unused FUs, clusters
mic
ro
cont
rolle
r
mic
ro
cont
rolle
r
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15Rice University, 8 June 2005
Example: 3G Algorithm Kernels Running at (amax,mmax, cCDP)
Example: 3G Algorithm Kernels Running at (amax,mmax, cCDP)
<1256Packing
Decoding
<164Re-packing
1764Initialization
25464Add-Compare-Select (ACS)
2364Decoding output
8332Interference cancellation
7132Matched filterDetection
132Correlation
Estimation
4332Matrix mul
132Iteration
< 1512Transpose
538 MHzMin. real-time frequency (a,m,c) =(5,3,512)
2232Matrix mul C
2232Matrix mul L
MHzCDPKernel Algorithm
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16Rice University, 8 June 2005
Cluster Size Relationship with Parallelism - c = 64, at 541 MHzCluster Size Relationship with
Parallelism - c = 64, at 541 MHz
100 101 102 10310-3
10-2
10-1
100
Clusters
Nor
mal
ized
Pow
er
Power ∝ f2
Power ∝ f2.5
Power ∝ f3
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17Rice University, 8 June 2005
ALU Utilization (+,*) ExplorationALU Utilization (+,*) Exploration
c = 64, α = 0.01, β = 1, p = 3
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18Rice University, 8 June 2005
TTA Processors: HSDPA Channel Equalization (VTC’04)
TTA Processors: HSDPA Channel Equalization (VTC’04)
Downlink transmission in MIMO wireless systemLinear channel equalization on the receiver sidePhysical layer of the mobile handset for 3GPP wireless standard – HSDPA applicationProgrammable and customizable processor implementation
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19Rice University, 8 June 2005
Channel EqualizationCG Algorithm and Adaptation
Channel EqualizationCG Algorithm and Adaptation
Block equalizationLatency of N samples:⇒ 4096 in slow fading⇒ 256 in fast fading
Second order statistics⇒ Channel estimation⇒ Covariance matrix
Modified algorithm⇒ Fast fading channels⇒ Weighted averaging
• second order statistics Channel equalization at the mobile handsetChannel equalization at the mobile handset
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20Rice University, 8 June 2005
TTA Processor for EqualizationTTA Processor for Equalization
Customized Processor for CG Filter Update in 2x2 Case⇒ Application-specific SFUs for equalization
Area of approximately 76K GatesFlexible Design Exploration⇒ Equalization in broad range of environments⇒ Dynamic power dissipation:
• 26 mW – 42 mW⇒ Minimum clock frequency to achieve real time:
• 37 MHz – 104 MHz
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21Rice University, 8 June 2005
Generated TTA Processor Architecture
Generated TTA Processor Architecture
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22Rice University, 8 June 2005
Example: LDPC Decoding -(ITCC’04)
Example: LDPC Decoding -(ITCC’04)
High Performance Decoding for Next Generation SystemsEmerging Algorithm – Early Stages of Design and Hardware ImplementationUnique View on Tradeoffs of BER Performance and Hardware ComplexityParallel Architecture Prototype in VHDL and LabVIEW FPGA to Target Flexible FPGAs
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23Rice University, 8 June 2005
Semi-Parallel LDPC Decoder Architecture
Semi-Parallel LDPC Decoder Architecture
CFU1
BFU96
BFU1
CFU48
BFU2
CFU2
Controller
... ...
Channel
MemInitnn=1..6MEMmn
m=1..3n=1..6
MemCodemn
OutputB1
B8
B7
B6
B5
B4
B3
B2
C1
C4
C3
C2
Check Nodes
Bit Nodes
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24Rice University, 8 June 2005
Decoding Parameters for Architecture Analysis
Decoding Parameters for Architecture Analysis
Decoding algorithm: Modified Min-SumBlock length: 768,1536Code rate: 1/2Structured Parity check matrix⇒ Row degree: 6⇒ Column degree: 3
Maximum # of iterations: 20Message bit-length: 5 bits
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25Rice University, 8 June 2005
LDPC FPGA Design StatisticsLDPC FPGA Design Statistics
A (3,6) semi-parallel LDPC decoder has been implemented in VHDL and Using LabVIEW FPGA For a VirtexII-3000 FPGA
25%RAMB16s
19%External IOBs
97%Slices
768 bitsBlock Length
LabVIEW FPGADecoder Structure
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26Rice University, 8 June 2005
LabVIEW ImplementationLabVIEW Implementation
Full Communication LinkLabVIEW Host⇒ LDPC Encoder⇒ AWGN ⇒ LDPC DecoderCo-Simulation⇒ FPGA Decoder
Current Work: New Layered Row and Column Schedules
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27Rice University, 8 June 2005
Testbeds: Rice University CMC Laboratory
Testbeds: Rice University CMC Laboratory
Collaboration with TI, Nokia, National Instruments, Spirent Communications, Xilinx, and US National Science Foundation.
Key Instruments are Channel Emulators to inject realistic channel conditions – Recorded or SimulatedFPGA Prototype Hardware for VLSI Signal Processing for Baseband
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28Rice University, 8 June 2005
CMC Wireless TestbedComponents
CMC Wireless TestbedComponents
Integration of Digital Baseband, RF, and Channel EmulationNI LabVIEW for Control Software in First Version2.4 GHz Radio Upconverters, Downconverters and Programmable RF Switch GearProgrammable and ReconfigurableOngoing Development of Custom FPGA System for MIMO Research
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29Rice University, 8 June 2005
CMC Testbed HardwareCMC Testbed Hardware
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30Rice University, 8 June 2005
Rice Transit Access Points –MIMO OFDM Testbed
Rice Transit Access Points –MIMO OFDM Testbed
Rice Networking Group Relay Network Architecture2 x 2 MIMO OFDM-based channel measurement system at 2.4 GHzBaseband processing and digital up and down conversion on FPGAs – Flexible waveformsNallatech FPGA Kits with National Instruments radios for amplification and analog up and down conversionCustom FPGA and RF system based on Virtex-II Pro and Maxim 2.4 GHz radios under Development
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31Rice University, 8 June 2005
University of Oulu 4G LabUniversity of Oulu 4G Lab
Elektrobit EB4G Testbed SystemPhysical 2.4 GHz RF link for MIMO Research between Elektrobit Research and CWC⇒ 1 Km Non-line of Sight
FPGA based System with Open Architecture⇒ Core and Algorithm Research Hardware Partition
Integrates with PropSim and PropSound2 x 2 System under Development⇒ Rapid Prototyping and Experimental Verification⇒ MIMO Detectors – Extensions to LMMSE and Sphere-like
Decoding
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32Rice University, 8 June 2005
Related Testbed EffortsRelated Testbed Efforts
Elektrobit EB4G Research Use⇒ University of Oulu⇒ VTT⇒ Osaka University
UCLA / Ohio State UniversityUniversity of Texas, Austin
Common Goals on MIMO and Beyond 3G Algorithm Research Characterization with FPGA and DSP Baseband and 2.4 GHz Radios
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33Rice University, 8 June 2005
SummarySummary
Wireless Architectures - Rice Research:⇒ VLSI Signal Processing Architectures
• Channel Estimation and Equalization• Multi-user Detection• Decoding
⇒ Programmable and Configurable ASIPs• Imagine, TTA
⇒ Development of CMC Wireless Testbed
Rice – CWC Research Interaction⇒ CWC Postgraduate Course ⇒ Beyond 3G Research and Elektrobit EB4G Testbed