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VLSI and hardware engineering interviewquestionsBy admin | Decem ber 7 , 2 003

1 . Explain why & how a MOSFET works

2. Draw Vds-Ids curv e for a MOSFET. Now, show how this curv e changes (a) with

increasing Vgs (b) with increasing transistor width (c) considering Channel Length

Modulation

3. Explain the v arious MOSFET Capacitances & their significance

4. Draw a CMOS Inv erter. Explain its transfer characteristics

5. Explain sizing of the inv erter

6. How do y ou size NMOS and PMOS transistors to increase the threshold v oltage?

7 . What is Noise Margin? Explain the procedure to determine Noise Margin

8. Giv e the expression for CMOS switching power dissipation

9. What is Body Effect?

1 0. Describe the v arious effects of scaling

1 1 . Giv e the expression for calculating Delay in CMOS circuit

1 2. What happens to delay if y ou increase load capacitance?

1 3. What happens to delay if we include a resistance at the output of a CMOS circuit?

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1 4. What are the limitations in increasing the power supply to reduce delay ?

1 5. How does Resistance of the metal lines v ary with increasing thickness and increasing

length?

1 6. You hav e three adjacent parallel metal lines. Two out of phase signals pass through the

outer two metal lines. Draw the wav eforms in the center metal line due to

interference. Now, draw the signals if the signals in outer metal lines are in phase with

each other

1 7 . What happens if we increase the number of contacts or v ia from one metal lay er to the

next?

1 8. Draw a transistor lev el two input NAND gate. Explain its sizing (a) considering Vth (b)

for equal rise and fall times

1 9. Let A & B be two inputs of the NAND gate. Say signal A arriv es at the NAND gate later

than signal B. To optimize delay , of the two series NMOS inputs A & B, which one would

y ou place near the output?

20. Draw the stick diagram of a NOR gate. Optimize it

21 . For CMOS logic, giv e the v arious techniques y ou know to minimize power consumption

22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data

from a Bus

23. Why do we gradually increase the size of inv erters in buffer design? Why not giv e the

output of a circuit to one large inv erter?

24. In the design of a large inv erter, why do we prefer to connect small transistors in

parallel (thus increasing effectiv e width) rather than lay out one transistor with large

width?

25. Giv en a lay out, draw its transistor lev el circuit. (I was giv en a 3 input AND gate and a

2 input Multiplexer. You can expect any simple 2 or 3 input gates)

26. Giv e the logic expression for an AOI gate. Draw its transistor lev el equiv alent. Draw its

stick diagram

27 . Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD,

giv e the output for a square pulse input going from 0 to VDD

29. Draw a 6-T SRAM Cell and explain the Read and Write operations

30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size

this circuit? (Consider Channel Length Modulation)

31 . What happens if we use an Inv erter instead of the Differential Sense Amplifier?

32. Draw the SRAM Write Circuitry

33. Approximately , what were the sizes of y our transistors in the SRAM cell? How did y ou

arriv e at those sizes?

34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s

performance?

35. What’s the critical path in a SRAM?

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36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of

Clock signal?

37 . Giv e a big picture of the entire SRAM Lay out showing y our placements of SRAM Cells,

Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

38. In a SRAM lay out, which metal lay ers would y ou prefer for Word Lines and Bit Lines?

Why ?

39. How can y ou model a SRAM at RTL Lev el?

40. What’s the difference between Testing & Verification?

41 . For an AND-OR implementation of a two input Mux, how do y ou test for Stuck-At-0 and

Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant

logic)

42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inv erter. How do y ou

av oid Latch Up?

Th is en tr y w a s posted in Hardw are. Bookm a r k th e perm alink . Post a comment or lea v e a

tr a ckba ck: Trackback URL.

48 COMMENT S ON V LSI A ND HA RDWA RE ENGINEERING

INT ERV IEW QUEST IONS

VLSIwww.utltraining.com

Get the UTL edge, be the Industry preffered one. 100%placements

Ruchi GuptaPosted 1/24/2004 at 8:45 pm | Pe rmalink

Do y ou also post the answers to these (Hardware)questions?

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adminPosted 1/24/2004 at 8:48 pm | Pe rmalink

Ruchi, I only post what I hav e, and this set of questions came without answers.

If y ou and other readers know the answers, y ou can post the comments here,

and I will add them to the original documents.

Karthik RamachandranPosted 1/27/2004 at 1:36 am | Pe rmalink

All answers can be found in ” Principles of CMOS VLSI design by Neil and

Kamran

mushtaquePosted 3/17/2004 at 12:37 am | Pe rmalink

i hav e forgotten my administrator password in Win 2000n serv er ,and file

sy stem is NTFS how can i break that and work normally plz say it fast

PrafullaPosted 4/7/2004 at 8:22 am | Pe rmalink

Use Digital Integrated Circuits A Design Prespectiv e BY Jan M. Rabaey for

answer to all Questions……Njoy y y y

Subodh TaigorPosted 4/11/2004 at 11:23 pm | Pe rmalink

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Here are the books:

1 . Design of CMOS analog integrated Circuits: For Mosfet operation, secondry

effects, short-channel effects, mos-capacitances, Lay out issues.

2. Digital Integrated Circuits A Design Prespectiv e BY Jan M. Rabaey :

For:Read chapters:Inv ertor, CMOS combinational logic, Interconnects,

CMOS sequential logic, Memory (last chapter)

**for moise margins fundas read “kang”

BalaPosted 4/18/2004 at 12:05 pm | Pe rmalink

For Question 6, I think the PMOS transistors should be sized more than NMOS

transistors

TinaPosted 4/20/2004 at 11:30 am | Pe rmalink

Hi,

has any one appeared in the Wipro’s exam held in Jan 2004 and Nov 2003 for

the M.Tech/MS/ME for VLSI candidates. Can someone help in in this regards.

Thanks.

JunaidPosted 4/21/2004 at 1:45 pm | Pe rmalink

Here is the stick diagram for NAND,NOR and NOT gates.Got it by searching on

google.

VCC VCC

| | | |

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| | | |

P -x——–x———x————————

| | |

| |____/|\________ C

| | |

N -x—————–x————————-

| | |

| | |

VSS B A

2 INPUT NAND

VCC

| | |

| | |

P –x—————-x—–

| | |

| ____/|\_|____ C

| | |

N –x——-x——–x—–

| | | |

| | | |

VSS A B VSS

2 INPUT NOR

VCC

| |

| |

P –x—–x–

| |

| |__ B

| |

N –x—–x–

| |

| |

VSS A

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INVERTER

JunaidPosted 4/21/2004 at 1:46 pm | Pe rmalink

Sorry i showed up right in comment box …but not after posting.

JunaidPosted 4/21/2004 at 1:51 pm | Pe rmalink

Follow this link for stick diagram

JunaidPosted 4/21/2004 at 3:52 pm | Pe rmalink

http://www.geocities.com/cmoslay outdesign/amask/amask1 1 .html

RekhaPosted 5/11/2004 at 9:23 pm | Pe rmalink

hi guy s does any one hav e the answers ready ? i know its in the book

but wud appreciate if any one can prov ide some answers. thanks!

AnynonymousPosted 12/15/2004 at 5:14 am | Pe rmalink

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Q1 4: Dy namic Power dissipation increases.

Q1 5: Resistance is directly propotional to length and inv ersly propotional to

area.So higher metals has lesser resistance.Increasing L increases the

resistance.

Q1 7 :Increase in contact resistance.

Q27 :NMOS passes clean zero and a bad one while PMOS passes clean 1 and bad

zero(Hint:Vt loss)

Q42:Paratic Tx act as ty ristors.Chances of triggering this thy ristor.

Put sufficient well contacts.

Kundan SrivastavaPosted 12/16/2004 at 1:08 am | Pe rmalink

u can find all the needfull in :

1 )Principles of CMOS VLSI Design : Neil Weste

2)Microelectronics circuits : Adel A. Sedra,K.smith

3)Digital Integrated Circuit : Kang

G.MadhusudhanPosted 5/10/2005 at 4:24 am | Pe rmalink

Hi, any guy s can help me in getting interv iew questions on digital sequential

logic, F/Fs, timing constraints, formal v erification.

NitinPosted 5/10/2005 at 11:03 am | Pe rmalink

Thanx, this page has certainly prov ided a background to withstand interv iew

for our project assignment on Vlsi. But additional details are required (other

than kang & neil weste’s book)for that can any one find from

-Cmos Analog Circuit Design

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by Phillip E. Allen and Douglas R. Holberg

-RF Cmos Integrated Circuits

by Thomas H. Lee

fist book is ideal for newcomers in analog domain (ev ery thing is properly

arranged ADDitional topics ADC & DAC)& second for those who wants to work

in RF mode.

the lungPosted 6/5/2005 at 5:39 pm | Pe rmalink

how do y ou increase the noise margins?

The only thing that i can think of is increase the width of the nmos (k_R ratio),

but then that also increases y our V_IH

nagaprasadPosted 6/26/2005 at 10:35 pm | Pe rmalink

hi…analog designers

these answers can be found in simpler way in the book

“AnalogICdesign” by baker

all the best to all of u

RoshanPosted 7/7/2005 at 1:21 am | Pe rmalink

Can u explain me about latch up proble in cmos gates

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narasimhaPosted 7/13/2005 at 8:46 am | Pe rmalink

answer for 1 9 th question:

connect b signal to the transistor(mos) which is nearer to the supply ,bec it will

reduces the charge sharing problem between the source of one Txr and drain of

another Txr.the reason for the charge sharing is that the capacitance formed

between the two lay ers

if any queries please free to mail me

narasimha_828@y ahoo.co.in

Subodh TaigorPosted 7/26/2005 at 10:44 pm | Pe rmalink

Vt of MOS decreases with temperature, But current decreases. How come?

ranjitPosted 12/20/2005 at 12:37 pm | Pe rmalink

Answer for Question 6:

Threshold v oltages are increased by making the v oltage of the NMOS bulk

silicon negativ e with respect to the source terminal of the array , and the PMOS

bulk more positiv e v is–v is the drain of the array .

Krishnamraju KurraPosted 12/27/2005 at 12:22 pm | Pe rmalink

Comment 1 4 say s that answer to question 1 7 is “Increase in contact

resistance”.

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I think the resistance decreases. Look at the ‘contacts’ between the metal lines

as ‘resistances in parallel’ with one another. If one conatact giv es a resistance of

R between the meatl lines, then four contacts would giv e a resistance of R/4.

Krishnamraju KurraPosted 12/27/2005 at 12:30 pm | Pe rmalink

I would recommend “CMOS: Circuit Design, Lay out, and Simulation” by “Dr.

Jake Baker”. Check http://www.cmosedu.com/ and the authors website for

streaming v ideo lectures on CMOS circuits.

Krishnamraju KurraPosted 12/27/2005 at 12:42 pm | Pe rmalink

Answer to question on comment # 22.

Both resistance and threshold v olatge are effected by temperature.

As temperature goes up threshold goes down and resistance goes up.

Effect of increase in resistance in more than the effect of decrease in threshold

abov e a certain temprature, thats why we see a decrease in current.

Think in terms of mobility of the majority carriers to understand why

resistance goes up.

PrashantPosted 1/26/2006 at 12:20 am | Pe rmalink

Ans to Q1 4

Considering the Punchthru and DIBL (because of which gate looses the control

ov er the transistor operation) the increase in Vdd has to be restricted. As well

the HOT electron effect also takes place.

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You can refer the book ‘Digital Integrated Circuits, A Design Perspectiv e’ by

‘Jan M. Rabaey ’

Prashant

(IITM)

YgchenPosted 2/6/2006 at 6:52 pm | Pe rmalink

Answer to question on comment # 22.

Around room temperature, the threshold of a MOSFET reduces with

temperature, but the carrier mobility increase with temperature.

These two effects influence the drain current simutaneously , but the mobility

change dominates, so the ov erall effects shows the current decrease.

YgchenPosted 2/7/2006 at 1:18 am | Pe rmalink

Sorry for the ty po error, the mobility decreases with temperature around room

temperature.

NIKHIL AHUJAPosted 4/8/2006 at 2:59 pm | Pe rmalink

anser to ques 21 :

we can reduce power dissipation of mos ckts by reducing the supply v oltage and

reducing the frequency .

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NIKHIL AHUJAPosted 5/7/2006 at 1:26 pm | Pe rmalink

hi..to all

ans to 24…i think its a better to connect them in parallel instead of one large

width transistor because it reduces the area…

PrashantPosted 5/7/2006 at 2:01 pm | Pe rmalink

in reply to comment 31 i would like to say that.. instead of say ing it reduces the

area.. its better if we say it reduces the stray capacitances..

the circuit performace is the first criteria for the designer.. not area

AtulPosted 5/23/2006 at 5:04 am | Pe rmalink

Ans to Q21 . The way s to minimize power consumption of CMOS is by 1 )

Optimizing Vt, 2) process Scaling and 3) Fabrication Adv ancements

SurajPosted 12/25/2006 at 7:46 pm | Pe rmalink

Corrected the ty pos:

First - This set of questions and the feedback from ev ery one is wonderful.

Additional Answer for question 24: Longer the width y ou encounter IR-drop

since the poly /gate is high resistance. There is signal degradation along the

long width. True, for capacitiv e reasons and from lay out perspectiv e (area) are

the two reasons to av oid long widths. Too short widths are not good either since

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it can be susceptible to delta w-v ariations.

mansiPosted 1/17/2007 at 2:11 pm | Pe rmalink

Ans#9:

The Body Effect describes the effect of Source to Bulk v olateg on the Threshold

v oltage of the mosfet.

If there is ev en a little potential difference between the source and the bulk, this

will increase the threshold v olatge v alue.

Vtn = Vto + γ(√Vsb + 2Æ)- √2Ãâ€

where Vto = zero bias v olatge , Vsb =source to bulk v olatge, γ = body effect

parameter , Æ= surface potential .

umaPosted 3/8/2007 at 1:18 am | Pe rmalink

After drawing the CMOS lay out where actually it’s giv en as input for next

process.What is the difference bten. pre and post lay out

Ashwath & RaghavendraPosted 4/1/2007 at 3:57 pm | Pe rmalink

Refer Pg no. 1 7 3–1 7 6 in “CMOS digital Intergrated Circuits ” ……Kang

chiranjeevi

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Posted 4/12/2007 at 9:10 am | Pe rmalink

MOSFET is ty pe of transistor.first of all,let us discuss about the FET then

MOSFET.FET means field effect transistor.hence it can be noy ed that transistor

is effected by the applied field

Mohammad Usaid AbbasiPosted 6/17/2007 at 7:32 am | Pe rmalink

1 9. Let A & B be two inputs of the NAND gate. Say signal A arriv es at the

NAND gate later than signal B. To optimize delay , of the two series NMOS

inputs A & B, which one would y ou place near the output?

Ans. The input which is coming late is tied close to output.Take a look at the

pull-down circuitry :

__out

_|

A -|_

_|- C

B -|_

|

Gnd

-> Lets say that A is coming at 3ns and it takes 1 ns to discharge a node, and B is

coming at 4ns and it takes 1 ns to discharge the node.A will not starts

discharging the node out until and unless node C is discharged which happens

only after 5 ns (4+1 ).So total time to discharge out is 6ns.But if A is coming at

4ns and B is coming at 3ns,then total time to discharge C is 4ns (3+1 ) and to

discharge out is 5ns.

——usaidabbasi@gmail.com

Mohammad Usaid Abbasi

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Posted 6/17/2007 at 7:33 am | Pe rmalink

1 9. Let A & B be two inputs of the NAND gate. Say signal A arriv es at the

NAND gate later than signal B. To optimize delay , of the two series NMOS

inputs A & B, which one would y ou place near the output?

Ans. The input which is coming late is tied close to output.Take a look at the

pull-down circuitry :

__out

_|

A -|_

_|- C

B -|_

|

Gnd

-> Lets say that A is coming at 3ns and it takes 1 ns to discharge a node, and B is

coming at 4ns and it takes 1 ns to discharge the node.A will not starts

discharging the node out until and unless node C is discharged which happens

only after 5 ns (4+1 ).So total time to discharge out is 6ns.But if A is coming at

4ns and B is coming at 3ns,then total time to discharge C is 4ns (3+1 ) and to

discharge out is 5ns.

â€â€Ã¢â‚¬â€usaidabbasi@gmail.com

Mohammad Usaid AbbasiPosted 6/17/2007 at 7:36 am | Pe rmalink

23.Why do we gradually increase the size of inv erters in buffer design? Why

not giv e the output of a circuit to one large inv erter?

Ans.. If we directly giv e the output of the circuit to one large inv erter then the

output of the circuit might not be able to driv e the

inv erter completely resulting in large delay s…

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Mohammad Usaid AbbasiPosted 6/17/2007 at 7:40 am | Pe rmalink

1 5. How does Resistance of the metal lines v ary with increasing thickness and

increasing length?

R = pl/A (p is resistiv ity here)

if y ou increase the length charge carriers hav e to go longer (motion get

retarded due to brownian mov ement,increase in resistance).If y ou increase

thickness carriers face less congestion so mov es freely (decrease in resistance)

— usaidabbasi@gmail.com

RajaPosted 7/29/2007 at 3:43 pm | Pe rmalink

Transmission gate works if and only if the both nmos and pmos triggers.. if any

of the mos switches does not switch.. then the output goes into impedence state

(which may be high or low)

RajaPosted 7/29/2007 at 3:47 pm | Pe rmalink

Q34 The PMOS Pull up transistors act when we need to write in the SRAM. as

one of the node turns high the other turns low (coz both the inv erters are cross

soupled with two pass transistors) in order for the node to turn high it needs the

transistor pull up. so pmos transistor is used to pull up.

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RajaPosted 7/29/2007 at 3:55 pm | Pe rmalink

Q31 . Differential Sense amplifier(SA) is used in order to differentiate the two

inputs(BL & /BL) and amplify the signal of the bitlines, example.. If we see a

small v oltage rise (around 0.6v ) in the bitlines which in turn the output of the

6T memory cell.. then the differential amplifier amplifies the signal to 1 .2V

(that is the v oltage produced to S.A)so if we use the inv erter instead of the

Amplifier, as we know that inv erter can be used for amplification of the signal..

but the problem here can be the output is inv erted and the the comparison of

both bit and bit bar is not possible..

RajaPosted 7/29/2007 at 4:12 pm | Pe rmalink

Q1 2 Delay increases if we increase the Load Cap. by eqn.

Td(delay ) = An *(CL / Bn)

here Td is directly proportional to CL so as CL increases Td increases

where

An = Process const. for a specific Vdd.

Bn = Beta of NMOS.

andyPosted 1/13/2008 at 2:50 pm | Pe rmalink

well for question 6 detailed answer:

for an NMOS:

as v t decreses Vds increases

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therefore Ids icreases or qualitativ ely the effectiv e channel length of NMOS

decreses.

thus to increase v t for nmos increase channel length and v ice v ersa for PMOS

-Bolo Yo…….if u read neil and weste thoruoghly it willl put u in good stead…….

Mohammad Usaid AbbasiPosted 4/25/2008 at 12:45 pm | Pe rmalink

1 2. What happens to delay if y ou increase load capacitance?

Delay increases…

I=Cdv /dt

or dt=Cdv /I

or dt proportonal to C

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