Design, Applications and Discussions on VLSIMuhammad Fahd Waseem

Faculty of Electronics EngineeringGhulam Ishaq Khan Institute of Engineering Sciences and Technology

Topi, Swabi, PakistanEmail: muhammadfahd@ieee.org

Abstract—This is originally a course assignment done for theCS465 course at the GIK Institute, Pakistan, and was completedon the 17th of November, 2010. This is NOT a research paper,though every attempt has been made to keep the informationin this document as accurate as possible. This paper is releasedunder the Creative Commons Share-Alike license only.

This paper answers some simple questions that rise in de-velopment and design of ASICs, and VLSI, on the logic andphysical level. It does so by solving some small problems inan optimized manner. A discourse on the tools used, and thetechniques employed in such endeavours is also provided.

Index Terms—ASIC, VLSI, MicroWind, Switch Level, PhysicalLevel, EDA, routing

I. INTRODUCTION

Four questions are answered in this VLSI and ASIC DesignCourse Assignment.

1) To draw and simulate the optimized physical level layoutof the logic expression

(A+B) · (B + C)

using "µwind" (MicroWind) as the graphical layoutsoftware tool.

2) To draw and simulate the optimized physical level layoutof a single-bit full-adder for inputs A, B and Cin andoutputs S and Cout.

3) A discussion of commercially available CAD toolswhich are used in real time chip designing for logicverification, net-list generation (synthesis tools), logiclevel simulators and physical level simulators.

4) A discussion on interconnect routing techniques andmethods in physical layouts.

The sections that follow answer the questions in detail, inthe same order. Some basic level of knowledge in VLSI &ASICs is required to be able to understand them completely[1].

II. QUESTION 1A. Answer Explanation

The given expression is:

F = (A+B) · (B + C)

This can easily be implemented efficiently using the OAI(Or-And-Invert) method for implementing CMOS circuits. SeeFig. 1.

Fig. 2. shows the optimized physical layout design. Notethat the physical layout diagram has been converted intosketchmark patterns for printing clarity.

Figure 1. OAI implemented CMOS Schematic for Question 1

It may be seen from the layout that care has been takento keep the overall size of the layout at a minimum, whilealso maintaining the mimimum number of contacts (vias) andlength of the electrical routes as short as possible. The layoutis compliant with the standard design rules, and was subjectto DRC checks before finalization.

Table I shows the expected results from the evaluation ofthe given expression. Fig. 3. shows the MicroWind simulationresults.

B. Conclusion to Question 1

The physical layout is as optimized as possible, and thesimulation results match the expected results of the given logicexpression.

Figure 3. Simulation Verification for Question 1

Figure 2. CMOS Physical Layout Schematic for Question 1

Table IEXPECTED SIMULATION RESULTS FOR QUESTION 1

A B C Output

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0

III. QUESTION 2

A. Transmission Gate Based Full Adder

A single-bit full-adder can be implemented using the equa-tions:

S = A⊕B ⊕ Cin

Cout = (A ·B) + (Cin · (A⊕B))

Note that the + operator in the expression for Cin can bereplaced by ⊕ without altering the logic of the circuit, asshown in Table II, our design will become far simpler becausewe now have to construct only two types of gates: XOR &AND. Cout = (A·B)⊕(Cin·(A⊕B)). These can be replicatedin cells. See Fig. 4.

However, using this approach increases the number ofgates involved. As the assignment question explicitly asks for

Table IIEXPECTED RESULTS AND EQUATION OUTPUT FOR QUESTION 2

Cin B A S = A ⊕ B ⊕ CinCout =

(A·B)⊕(Cin·(A⊕B))

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Figure 4. Gate Implementation of Single-Bit Full-Adder with XOR & AND

optimized layouts, the least size solution demands that the useof the OR gate be maintained.

For the XOR gates, a particularly compact configurationutilizing transmission gates (TG) may be used. Fig. 5. showssuch a XOR gate. A full adder implemented using this is theTG XOR gated adder. A TG XOR gated adder can be imple-mented in a minimum of 26 transistors. This is less transistorsthan the standard OR & AND full adder implementation.

Finally, there is another TG based full adder that uses just 24transistors, as shown in Fig. 6, however the routing complexityis high.

B. Mirror Adders

There is another method for designing a CMOS single-bitfull-adder: the mirror adder. This is a nmos-pmos symmetricstructure, and the number of transistors used in this configu-

Figure 5. TG XOR Gate

Figure 6. TG Based Full Adder with 24 Transistors

Figure 7. Basic / Unmanipulated Mirror Adder

ration is actually more than that used in the TG XOR gatedadder, while still less than the standard OR & AND full adder.

However, the basic mirror adder, as shown in Fig. 7. usesthe expressions below[2]:

Co = AB + CiA+ CiB,Cout = Co

S = ABCi + CoA+ CoB + CoCi, Cin = Ci

These equations can further be manipulated for true-mirroring i.e. such that the upper and lower half are trulysymmetric. The following sets of equations are the same inlogic, yet lend themselves to true nmos-pmos symmetry:

Co = AB + Ci · (A+B)

Co = (A+B) · (Ci +AB)

&

S = (A+B + Ci).Co +ABCi

S = (ABCi + Co) · (A+B + Ci)

Note in particular the re-usage of the Co in both the Sequations. In each set, one equation forms the nmos circuit,while the other equation forms the pmos circuit. Also note thatthe equations are essentially the same with all the operatorsreversed. Fig. 8. shows the implementation.

Figure 8. True Mirror Adder

C. Physical Layout Selection and Simulation

Due to the ease of implementation, and size efficiencyof the true-symmetry mirror adder, that is the one chosenfor the physical layout. The physical layout so developed inMicroWind is shown in Fig. 9. The simulation of this layout,also done in MicroWind, is shown in Fig. 10.

D. Conclusion to Question 2

After considering multiple designs and techniques, it wasdeemed that the true-symmetry mirror adder was the best onefor our requirements. It was highly optimized, and simulationwas working perfectly.

IV. QUESTION 3

A. Introduction

The tools being referenced are known as ECAD (ElectronicComputer Aided Design). They are also often known as EDA(Electronic Design Automation) tools.

These days, the EDA tools available are usually highlymodular, and often perform more than one particular task.They also come in a wide range of prices: completely free,free just for academic use, low cost, or high cost. Naturally,the high cost tools are generally better in terms of functionalcapability and performance, particularly for large circuits.

Due to this variance, it is no longer possible to distinctlycategorize most software tools as logic verification tools,net-list generation (synthesis tools), logic level simulators,physical level simulators or anything such.

Logic verification means the confirmation of the correctworking for given circuit design. Synthesis tools generate anet-list for inter-component connections that can be exportedto implementation tools. Logic level simulators simulate thedigital logic of a circuit; physical level simulators, likewise,simulate the actual physical layouts.

Commercially, a few companies dominate the industry.These companies follow industrial standards, and have estab-lished their own softwares as standards as well. It should benoted that the software these companies produce is geared

towards volume or high-budgeted manufacturers, and is gener-ally priced accordingly. Another point to note is that the Linuxplatform is prevalent in the high performance semiconductorindustry as an OS, so most of the products provided by thesecompanies usually do not run on the Microsoft Windows© OS.The following are the major EDA software companies:

• Synopsys• Cadence• Mentor Graphics• Magma Design Automation• Zuken Inc. (This company, however, provides no software

tools for IC level EDA.)• EEsof, Agilent Technologies EDA ArmOf these, Synopsys and Cadence have the largest market

caps.

B. Synopsys[3]The Discovery Verification Platform is an integrated port-

folio of functional, formal, low-power and hardware-assistedverification tools. Discovery provides high performance, highaccuracy and efficient interactions among best-in-class tech-nologies including mixed-HDL simulation, mixed-signal simu-lation, assertions, coverage, testbench automation, verificationIP, formal analysis, unified debug, equivalence checking andrapid prototyping.

Synopsys also provides a large portfolio of tools for syn-thesis.

C. Cadence[4]The Virtuoso Platform is a set of tools for designing full-

custom integrated circuits; it includes schematic entry, behav-ioral modeling (Verilog-AMS), circuit simulation, full customlayout, physical verification, extraction and back-annotation. Itis used mainly for analog, mixed-signal, RF, and standard-celldesigns, but also memory and FPGA designs.

The Encounter Platform is a set of tools for creation of dig-ital integrated circuits. This includes floorplanning, synthesis,test, and place and route. Typically, a digital design starts fromVerilog netlists.

The Incisive Platform is a set of tools for simulation andfunctional verification of RTL including Verilog, VHDL andSystemC based models. This includes formal verification,formal equivalence checking, hardware acceleration, and em-ulation.

D. Mentor Graphics[5]Most pertinent for our purposes is the Questa ADMS

(Analog-Digital Mixed Signal Simulator). It gives design-ers a comprehensive environment for verifying complexanalog/mixed-signal (AMS) System-on-Chip (SoC) designs.ADMS combines four high performance simulation engines inone efficient tool: Eldo for general purpose analog simulations,Questa for digital simulations and ADiT for fast transistor-level simulations.

That in itself is a subpart of the Mentor Graphics IC-Flowor ICStudio platform. This platform encompasses the completeIC development flow, from design to production mask layouts.

Figure 9. True Mirror Adder Physical Layout in CMOS

Figure 10. Single-Bit Full-Adder Simulation for Question 2 Mirror Adder

E. Magma Design Automation[6]

The Talus Suite provides digital chip implementation tools,while the Titan Suite provides analog/mixed-signal designtools for ICs.

F. EEsof, Agilent Technologies EDA Arm[7]

Integrated Circuit Characterization and Analysis Program(IC-CAP) is a tool for DC and RF semiconductor device mod-eling. IC-CAP extracts accurate compact models used in highspeed/digital, analog and power RF applications. IC-CAP isused for modeling silicon CMOS, bipolar, compound galliumarsenide (GaAs), gallium nitride (GaN) and many other devicetechnologies. IC-CAP is the advanced, customizable modelingsoftware and includes measurement, simulation, optimizationand statistical analysis tools.

V. QUESTION 4

A. Interconnect Routing Consideration

Metal or wire interconnects between semiconductor featuresare an essential part of VLSI design. Optimized interconnec-tions will cause better signal fidelity, low signal latency, lowercosts and greater packing density. These come in the shape ofminimum number of vias, shortest possible routes, decreasedcapacitances, least number of layers and best placement offeatures.

B. Interconnect Routing Techniques and Methods

Perhaps the best example of optimized interconnects comesfrom Cadence’s Encounter Platform[4]. It includes optionsto ‘Place and Route’ semiconductor features as optimally aspossible when provided a Verilog netlist. It takes into accountgiven design rules when doing so, as well as user specifiedweights to the typical routing tradeoffs: numbers of vias,layers, route lengths etc. This is an example of letting an EDAtool do ‘PAR’. Else, these must be done manually.

Other methods for interconnect routing optimization comefrom the fabrication process itself. Better materials and diver-sion from the typical 90˚ ‘Manhattan’ layout promise far betterinterconnect routing possibilities and far denser packaging atthe price of increased cost.

Typically, there need to be specially optimized routes be-tween blocks for[8] for the given purposes. They are alsogenerally handled in this order.

1) Power supplies: High current and connectivity; needto be connected to almost all transistors. These aretypically placed in ‘straps’ rows of high large width lineswith smaller columnar paths to the transistor blocks.The straps originate at the power source. One layeris generally completely reserved for power in largerdesigns.

2) Clocks: Pervasive, and dynamic. These may be suppliedlike the power lines, or alternatively they may be ‘tree-d’, i.e. buffered at strategic points, with thinning pathwidths from there on.

3) Buses: Groups of signals. Generally critical.

4) Special Signals: Non standard width, differential pairs,shielded, etc.

5) General Routing: The remainder of the signals.For the items 3-5, meshes are generally used in large circuits.These are two dedicated layers of straight paths, perpendicularto each other. These meshes can have the ‘links’ broken at theright places to create connections.

One final twist to this scheme comes as better fabricationprocesses reduce cell sizes significantly. Some designers nowuse semiconductor layer components to provide main signalpaths, or even use full gate sized semiconductor logic featuresfor signal crossing using XOR gates[9].

C. Conclusion

Interconnect routing is a vast area of work, and cannot assuch be answered in such short space as this. However, thevital points were provided.

ACKNOWLEDGMENT

The author would like to thank his teachers, instructorsand TAs without whom this work would neither have beenrequired, nor completed.

REFERENCES

[1] J. P. Uyemura, Introduction to VLSI Circuits and Systems. GeorgiaInstiute of Technology, USA: Chinese Press, 2001.

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[3] (2010, Nov) Synopsys.com. Synopsys, Inc. [Online]. Available:http://www.synopsys.com/

[4] (2010, Nov) Cadence design systems. Cadence Design Systems, Inc.[Online]. Available: http://www.cadence.com/us/pages/default.aspx

[5] (2010, Nov) The eda technology leader - mentor graphics. MentorGraphics®. [Online]. Available: http://www.mentor.com/

[6] (2010, Nov) Magma: Integrating digital & analog ic design & verification.Magma Design Automation. [Online]. Available: http://www.magma-da.com/

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[8] D. Clein, CMOS IC layout: concepts, methodologies,and tools. Newnes, 2000, no. 1. [Online]. Available:http://books.google.com/books?id=fzuX6tyIeBkC

[9] (2010, Nov) Xor gate - wikipedia, the free ency-clopedia. WikiMedia Foundation, Inc. [Online]. Available:http://en.wikipedia.org/wiki/XOR_gate