Validating next generation CPUs

Praveen Vishakantaiah

President, Intel India

Feb 22, 2008

DV Club Bangalore

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“Validation is increasingly in the critical path of product success and requires continuous innovation to meet

customer satisfaction, schedule and margin requirements”

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Agenda

• Current Challenges

• Addressing the challenges

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CPU bug trends

Exponential growth of design complexity

• Deeply pipelined complex micro-architecture

• Logic bugs increase 3 - 4x per generationPre-silicon logic bugs per generation

( Source: Tom Schubert, Intel, DAC 2003 )

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Pentium Pentium Pro Pentium 4 Next ?

Up to 70% of design time and resources are spent during functional validation

Up to 70% of design time and resources are spent during functional validation

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The Pre-Si Verification gap

EE Times 03/18/2004 Verification Capabilities is fast becoming the limiting

factor for VLSI design improvements Verification Capabilities is fast becoming the limiting

factor for VLSI design improvements

EE Times 2004

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Current Challenges – Technical

• Increasing CPU design complexity– Multi core– Chipset integration– Power Management– New technology like security

• Increasingly bulky validation environment– Increase in development and maintenance cost– Environment bugs >= Logic design bugs

• Increasing number of product variants– Validation is not as incremental as design

• Increasing micro-architectural coverage space increases probability of escapes

• Decreasing simulation/emulation speed limits pre-silicon cycles

• Legacy features and compatibility validation

High volumes magnify the cost of a validation escape – can not let it happen!

High volumes magnify the cost of a validation escape – can not let it happen!

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Current Challenges – Non-Technical

• Shorter TTM (Time to Market)

• Physical limits and cost of data centers

• CPU validation expertise– More pronounced in India due to frequent job changes

• Cross site development– Design and validation may not be co-located

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Post-silicon validation

• SOC and Multi core leverage incremental design effort– Design interactions are spatial in nature– Effective design reuse is possible

• Post Si Validation efforts currently not scaling incrementally

- Logic interactions across widely separated areas introduces unexpected bugs

- No effective coverage feedback mechanism

- When is Validation enough ?- Synthesis of approx coverage measure - Effective Mathematical Models

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Addressing the challenges• Use experienced architects, micro-architects and front end designers

– Very likely to have lot more validation “burn” marks and will proactively code less bugs– Will be able to help validators debug issues faster– Raise the watermark for bugs and reduce iterations

• Validators drive requirements into architecture and micro-architecture– Influence technology decisions to keep validation tractable– Minimize feature creep during execution– Reduce back end design impact on front end design

• Instrument design models to enable validation– Assertions, instrumentation signals, comments– Aim for sweet spot with Effectiveness vs. Efficiency trade offs

• Validation Environment– Minimize custom tool development

• Reuse design, validation and debug tools across programs

• Scale emulation, formal verification and mixed signal validation

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Validation coverage profile and Efficacy Pro

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Time Si Spin1 Si Spin2

•Efficiency: Catch bugs fast

•Effectiveness: Catch all customer visible bugs

Early detection and bug accelerationEarly detection and bug accelerationhas significant business benefitshas significant business benefits

Early detection and bug accelerationEarly detection and bug accelerationhas significant business benefitshas significant business benefits

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Q&A