12th MRAM Global Innovation Forum

Virtual Forum, part of Intermag2021Live part: 27 April 2021, 2:00 am Europe CEST / 8:00 am Asia CST / 7:00 pm (26 April) USA CDT

Sessions Topics Invited Speakers Welcome & Introduction (Bernard Dieny)

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Mat

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Proc

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Ultrathin free layers for lowering the switching current in STT-MRAM

Tiffany Santos (Western Digital)

On-demand

Co-optimization of thin film deposition, etching, and encapsulation processes for high performance STT-MRAM

Sahil Patel (Applied

Materials)

MRA

M P

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On-demand

Development of high-performance MRAM and technology trade-offs

Eric Edwards (IBM)

On-demand

Current status and future prospect of STT-MRAM for a mainstream memory

Jeong-Heon Park

(Samsung)

On-demand

Line of Defense Strategies for Embedded STT-MRAM High Volume Manufacturing

Johannes Muller

(GLOBALFOUNDRIES)

On-demand

STT-MRAM in 16 nm FinFET for Solder-Reflow Applications

Yuan-Jen Lee (TSMC)

Desi

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echn

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On-demand

Advanced MRAM based memory systems for near future computing applications

Shinobu Fujita (KIOXIA)

On-demand

A 2MB, 16nm, sub 5ns Reads, MRAM-based Memory IP Core

Jack Guedj (Numem)

Beyo

nd S

TT-M

RAM

On-demand

SOT-MRAM and emergent applications

Shunsuke Fukami (Tohoku

University)

On-demand

On-Chip 3D caches for advanced heterogenous SoCs – A cross layer look at discerning MRAM design and technology requirements

Manu Perumkunnil

(Imec) Live Question & Answer Session with Invited Speakers, moderated by Kevin Garello

Panel Discussion Live

What do we need to bring MRAM to the next level? Moderator: Luc Thomas (Applied Materials) Panelists: Simone Bertolazzi (Yole), Gouri Sankar Kar (Imec), Daniel Worledge (IBM), Seung Kang (Qualcomm), Ko-Min Chang (NXP Semiconductor)

17:30 Closing remarks

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Tiffany Santos Senior Manager, Western Digital

Tiffany Santos is a Senior Manager at Western Digital in San Jose, California, working in the Research division on materials for non-volatile memory technology. She first joined the company in 2011, when it was previously known as Hitachi Global Storage Technologies, to work on research of media for heat-assisted magnetic recording. She received her SB and PhD in Materials Science and Engineering from the Massachusetts Institute of Technology, where she did her thesis research on magnetic tunnel junctions and thin film magnetism. After receiving a PhD, she became a Distinguished Postdoctoral Fellow, and later an Assistant Scientist, in the Center for Nanoscale Materials at Argonne National Laboratory. In 2009, she was awarded a L’Oreal USA Fellowship for Women in Science. Ultrathin free layers for lowering the

switching current in STT-MRAM Tiffany S. Santos, Neil Smith, Goran Mihajlović, Jui-Lung Li, Matthew Carey, Jordan A. Katine, and Bruce D. Terris, Western Digital Research Center, Western Digital Corporation, San Jose, CA 95119 A primary challenge in the creation of a high-density spin-transfer torque magnetic random access memory (STT-MRAM) technology is lowering the switching current needed to switch the magnetization of the free layer (FL) when writing a bit in the MRAM cell, while maintaining high thermal stability for data retention. As the critical switching current density Jc0 is proportional to the damping parameter α, saturation magnetization MS and thickness tF of the FL, one route toward lowering Jc0 is to lower tF. We present our approach to reduce tF while maximizing MS and minimizing α, thereby improving FL film quality and ultimately leading to lower Jc0. Conventional FLs typically have thickness > 2 nm. We have modified the FL design such that we can reduce tF down to 1.2nm while minimizing the magnetic dead layer, so that high MS > 1700 emu/cm3, high exchange constant Aex ~ 2.0 µerg/cm, and low α ~ 0.003 was obtained. We fabricated STT-MRAM devices having a ladder of FL thicknesses. Our device measurements show that Jc0 is lowest for the thinnest FLs, while the thermal stability factor ∆ remains high, so that overall, the thinnest FLs have the highest spin-transfer torque efficiency. Ref: T.S. Santos et al, J. Appl. Phys. 128, 113904 (2020)

Sahil Patel

Senior Process Engineer, Applied Materials Sahil Patel is a process technologist with a background in film deposition and etching for spintronic devices. Prior to joining Applied Materials where he works in the Advanced Product and Technology Development Group, he worked on PVD and etch for STT-MRAM devices at TDK-Headway technologies. Sahil is interested in linking process conditions to final device performance in order to design new processes and tools that can enable the next generation of semiconductor devices. Co-optimization of thin film deposition, etching, and encapsulation processes for

high performance STT-MRAM For compatibility with advanced node transistors, as well as to reduce overall chip power consumption to compete with conventional SRAM memory designs, STT-MRAM bits must be fabricated at reduced CD <50nm in order to reduce switching current, Ic. While for technologies at CD >50nm, much of the focus on MRAM development has centered around MRAM stack deposition using etch processes that result in high bit yields, current development must focus on the interplay of the MTJ film stack, etching, and encapsulation and their combined effect on the sidewall, which represents a large portion of the final device. In this talk, I will highlight experiments from our team at Applied Materials on mini-array short loop test vehicles which illustrate the need for 3-way co-optimization of film, etch and encapsulation to enable the next generation of MRAM technologies. I will focus on unit processes, and how improvements in unit processes can significantly improve the final device performance, but, more importantly, I will illustrate how these unit processes interact and can be combined to improve the final device performance and meet targets for specific MRAM applications.

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Eric Edwards

Advisory Engineer, IBM Eric Edwards is a member of the Advanced Logic & Memory Technology Research, Semiconductor, and AI Hardware Group of IBM Research at the Thomas J. Watson Research Center. He received his PhD from the University of Muenster in 2012 with a thesis on the optical study of magnetization dynamics in thin films, followed by postdoctoral work at the University of Regensburg and Martin Luther University Halle-Wittenberg. From 2015 to 2018, he was a National Research Council postdoctoral researcher at the National Institute of Standards and Technology in Boulder, Colorado working on high performance magnetic materials. He joined IBM Research in 2018, where he works on the development of MRAM technology for hybrid-cloud applications.

Development of high-performance MRAM and technology trade-offs

Twenty-five years after the invention of spin-transfer torque MRAM, the technology has reached wide adoption in the industry. MRAM has proven to be a versatile technology able to cover a large range of applications, from non-volatile embedded memory to DRAM-like standalone products. In its next incarnation, MRAM will be targeted to higher performance applications such as last-level cache for CPUs. In this talk, we will review the new challenges faced by the industry for such applications and discuss what technological trade-offs are available. We will present a holistic view of our advanced MRAM technology from MTJ device physics to system-level considerations. We will see how the recent demonstrations of reliable high-speed switching and integration of sub-40nm MTJs on 14nm FinFET indicate great potential for future high-performance MRAM technologies.

Jeong-Heon Park Principal Engineer, Samsung Jeong-Heon Park is a Principal Engineer at Samsung Electronics and currently works on Research and Development of STT-MRAM and emerging memories. He is responsible for developing MTJ stack and module process for Samsung’s next generation MRAM and emerging devices with higher speed and higher density. He started his career at Samsung in 1999 where he had developed integration processes for DRAM and Flash memories. He received a Ph. D in Materials Science and Engineering at Carnegie Mellon University in 2010 where he had studied perpendicular magnetoresistive devices for STT-MRAM and Spin Torque Oscillator. He has authored or co-authored more than 50 research papers and holds more than 30 U.S. and international patents.

Current status and future prospect of STT-MRAM for a mainstream memory

With the recent evolution of data-intensive computing systems, STT-MRAM has emerged as one of the most promising candidates of non-volatile memory solution with its high performance and logic process compatibility. In the conventional memory hierarchy, there exists a huge performance gap between high-speed cache and high-density storage. As processor core-count rises and key applications require higher volume of data processing, the performance gap causes significant increase in latency and power consumption. This has called broad interest in embedded non-volatile memory (eNVM) for its potential use as persistent on-chip memory to fill in the gap, resulting in the improvement of the entire system performances. With the fundamental benefits of harvesting “spin” instead of “electrical charge”, STT-MRAM is regarded as a unique eNVM having high read/write speed, practically unlimited endurance and robust data security. Although STT-MRAM lies no longer on the pursuit of universal memory, its superior adaptability makes it to be a very attractive building block for diverse IoT and computing applications. The performance adaptability originates from tailoring magnetic tunnel junction (MTJ), key storage element of STT-MRAM. Non-volatility modulation is a possible way to customize MRAM performances by changing the magnitude of magnetic anisotropy energy in MTJs. In this case, reducing or enhancing magnetic anisotropy energy tunes the thermal stability of magnetic bits, which shifts the practical range of operating temperature and retention time with the corresponding scaling of write energy. While this type of short-range tunability expands the applicability of MRAM, fundamental breakthrough is needed to overcome the chasm of this technology and to pull it into the main stream of future memory sub-system. Here we discuss progress and challenge for enabling such technological innovations.

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nnesMu Johannes Müller Group Manager NVM, GLOBALFOUNDRIES Dr. Johannes Müller is a member of the eNVM development team at GLOBALFOUNDRIES Dresden and currently acts as the responsible MTJ-Module Integrator for the 22FDX™ STT-MRAM technology. Prior to joining GLOBALFOUNDRIES he was heading the group for Non-Volatile Memories at Fraunhofer IPMS (formerly known as CNT) overseeing direct industry collaborations and European projects focused on FERAM, FeFET, STT-MRAM, RRAM, and FLASH. His research & development interests are primarily focused on the device physics, material development and integration of embedded memory solutions, with a special interest lying in the exploration of emerging ferroelectric and ferromagnetic device concepts. Line of Defense Strategies for Embedded

STT-MRAM High Volume Manufacturing

After several decades of trying to intercept FLASH based NVM solutions the frequently used term emerging memories began to slowly transition from a bold vision to an everlasting stigma. Especially in the primarily cost per bit driven mass data storage segment the introduction of 3D-NAND FLASH further solidified the dominance of charge-based memories and provided a roadmap to continuously raise the entry-barrier to the stand-alone market. On the contrary, the window of opportunity for emerging memories to conquer the embedded NVM market kept opening wider from technology node to technology node. This shift towards emerging BEOL-placed memories, such as spin-transfer-torque magnetic random access memory (STT-MRAM), is mainly due to the constantly increasing incompatibility of FLASH-based bit cells to advanced CMOS platforms. Main drawbacks are the intrinsically exhausted planar scalability of FLASH, its need for high voltage devices, as well as the challenging FEOL integration of Poly-SiON based memory transistors into High-K-Metal-Gate technologies. As a consequence, and with the break even in terms of mask adder and bit cell size being reached for the 2X nm nodes, solder reflow capable pSTT-MRAM (1T-1MTJ) technologies are now entering the market as an economical eFLASH replacement [1]. Considering the unique tunability of the endurance-retention trade-off in magnetic devices and the emergence of alternative write concepts, such as voltage controlled magnetic anisotropy (VCMA) [2] and spin-orbit –torque (SOT) [3], a roadmap extending beyond this initial entry point all the way to high speed,

high endurance lower level cache replacement may as well be envisioned. However, even though the technological challenges for this first generation of embedded STT-MRAM have been overcome, the passing of the baton as a full eFLASH replacement has not yet completed. Especially the vast amount of field data collected for classical eFLASH solutions and decades of manufacturing experience are still decisive factors that are slowing down the paradigm shift towards more advanced memory solutions. Here STT-MRAM needs to prove its ability to sustain the qualified reliability and yield in the course of volume ramp, as well as its potential for continuous yield enhancement and wafer cost reduction. To gain this trust, inline methodologies to tightly control the magnetic and electrical properties of the MTJ-based bit cell become an essential prerequisite. This is especially true for the foundry approach, where final assembly and functional test of the NVM-containing product are often directly conducted by the customer or a third party, which leaves only inline data and electrical test sites to safeguard the quality of the outgoing material. Consequently, a solid, multi-walled line of defense (LoD) is of utmost importance to first and foremost protect the customer and guarantee a reliable wafer disposition. Naturally, not only the detection of an excursion at the earliest manufacturing step possible, but also the entire prevention of multiple non-conforming wafers, needs to be part of the LoD strategy. This is highly rewarding since due to the late insertion point of BEOL-placed embedded memories the wafer has already acquired the largest part of its value when entering the MTJ processing steps. In this presentation we will address the aforementioned challenges based on a 1T-1MTJ perpendicular STT-MRAM technology embedded into an advanced, low power CMOS platform (22nm Fully-Depleted Silicon-On-Insulator, 22FDX® technology). The unprecedented complexity of this new memory technology needs to be counteracted by an equally unprecedented reservoir of versatile and profound characterization methodologies that are capable of predicting the yield and reliability critical properties of the final memory cell. To enhance the turn-around time of tool monitoring and to enable on-product film level and patterned MTJ metrology, the transition of classical lab-based methodologies, such as perpendicular magneto-optical Kerr effect (pMOKE), current-in-plane tunneling (CIPT) and ferromagnetic resonance (FMR), to full inline capability is essential. Correlation of these magneto-electric and magneto-optical parameters to the End of Line wafer electrical test and reliability monitoring are key for establishing a strong LoD. This work was funded in the framework of the Important Project of Common European Interest (IPCEI) by the Federal Ministry for Economics and Energy and by the State of Saxony [1] V.B. Naik et al., IEDM (2019) [2] T. Nozaki et al. Micromachines (2019) [3] K. Garello et al. VLSI (2019)

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Yuan-Jen Lee Technical Manager, TSMC Yuan-Jen Lee is a Technical Manager of MRAM Program in Embedded Technology Division at TSMC. He has 16 years of professional experiences in the research and development MRAM. Prior to joining TSMC, he was a Senior Manager in the STT-MRAM team at TDK-Headway Technologies. He received Ph.D. degree in Physics from National Taiwan University in 2003. He has published 30+ MRAM relative papers and holds 20+ issued U.S. patents.

STT-MRAM in 16 nm FinFET for Solder-Reflow Applications

Embedded STT-MRAM (eMRAM) can be used in a wide range of applications, such as microcontrollers (MCU), artificial intelligence (AI), and Internet of Things (IoT), to name a few. This versatility is enabled by its non-volatility, good endurance, reliable write, read performance, radiation hardness and CMOS process compatibility. TSMC has successfully demonstrated 22 nm (N22) eMRAM for solder-reflow capability with high yield, reliability, and magnetic immunity. N22 eMRAM is currently in the mass production stage. Here we present eMRAM scaling at the next technology node, N16 FinFET. Stable, high yield has been demonstrated. Even with the smaller cell size compared to N22, this cell retains reflow capability and a data retention of 10 years at > 200oC. Compared to the N22 eMRAM, we demonstrate faster read access time and lower write power consumption at a wide temperature range— -40oC to 125oC. Endurance bit-error-rate (BERs) are low and no significant aging effect was observed after 1 M cycles.

Shinobu Fujita Senior Fellow, KIOXIA

Shinobu Fujita received his PhD from the University of Tokyo and joined Toshiba in 1989. He has been working for new nonvolatile memory (NVM) circuit, system and application development for over 15 years. His major applications are ReRAM-based NV-logics, ReRAM-based-FPGA, NVM-based secure random number generators, NV-SRAM based cache memories, “normally-off processors” with STT-MRAM, persistent memory systems with STT-MRAM. These are used from cloud computing to IoT edge computing and mobile devices. Currently, he is a Senior Fellow of KIOXIA corporation (formally Toshiba Memory Corporation) and working on various NVM application projects including next generation flash memories.

Advanced MRAM based memory systems for near future computing

applications Various kinds of advanced MRAM technologies and memory systems have been intensively developed. This paper describes prospective views of near future computing applications from mobile/IoT edge computing to cloud computing using MRAM. There applications use three beneficial points of MRAM: fast persistent data storage, performance improvement and energy saving of memory hierarchy. These are shown using some examples of computing applications in details.

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Jack Guedj

Co-Founder/CEO, Numem Jack was President and CEO of Tensilica since 2008 where, he transformed Tensilica into a rapidly growing company ascending to the #1 position in merchant DSP and ultimately leading to the Cadence acquisition in 2013 where he served as Corporate VP, Tensilica Products. Prior to Tensilica Jack led the spin-out of Magnum from Cirrus Logic serving as founder, president and CEO. Jack led Magnum’s growth from ground zero to leadership in Multimedia SOCs for the Professional Video Broadcast, Consumer PVR TV/Camcorder/DVD Recorder and Set Top Box markets and the acquisition of the Consumer Products Group of LSI Corporation (C Cube). Prior to Cirrus, Jack was President of Tvia, Inc., leading that company’s successful IPO in August 2000. Jack holds an MBA from the UCLA Graduate School of Management. Jack attained a MSEE from Pierre & Marie Curie Engineering School of Paris, and a doctoral degree from the University of Pierre & Marie Curie.

A 2MB, 16nm, sub 5ns Reads, MRAM-based Memory IP Core

High-Performance STT MRAM can bring many benefits to SOC designers for replacement of eFlash but also certain SRAMs and OTPs. With higher speed Reads, it can be ideally suited to meet the requirements of demanding DNN AI coefficient memory applications. The device has been extensively tested using NuTest Algorithmic tester both at Wafer level and packaged parts including Radiation testing for Space/Defense applications and accelerated endurance/Read disturb.

Shunsuke Fukami

Professor, Tohoku University

Shunsuke Fukami, Ph.D. is a Professor of the Research Institute of Electrical Communication in Tohoku University. His areas of expertise include spintronics physics/materials/devices and their application to integrated circuits and computing technologies. He received his Master’s degree in Nagoya University in 2005, and joined NEC Corporation. He received his Doctor degree from Nagoya University in 2012. In 2011, he moved to Tohoku University. He received a number of awards for his research, including the JSAP Young Scientist Presentation Award, the Young Scientists' Prize of Science and Technology by the MEXT, Asian Union of Magnetics Societies, Young Researchers Award, the Outstanding Research Award of the Magnetics Society of Japan, and the JSAP Outstanding Paper Award.

SOT-MRAM and emergent applications

Magnetoresistive random access memories (MRAMs) are promising to drastically reduce the power consumption of various integrated circuits while keeping or enhancing their performance, due to their nonvolatility and capabilities of fast and reliable operation. While the spin-transfer torque (STT)-induced magnetization switching has been extensively studied for about two decades and is used in the currently commercialized STT-MRAM, spin-orbit torque (SOT)-induced magnetization switching [1-3] has a potential to offer alternative pathway for even higher speed operation. In this presentation, I will show a material and device engineering [3,4] for the demonstration of SOT-MRAM with 55-nm CMOS circuits fabricated through an industry-compatible 300-mm wafer process [5,6]. Using three-terminal magnetic tunnel junction with in-plane magnetic easy axis and Ta/W channel, field-free switching is achieved down to the pulse width of 0.35 ns. I will also discuss emerging applications of STT and SOT technologies. An antiferromagnet/ferromagnet heterostructure controlled by SOT shows analog-like behavior [7], showing promise for artificial synapse in neural networks [8]. Also, stochastic nature of magnetic tunnel junction is useful for probabilistic computing, that has a similar functionality to quantum annealing machine [9]. The work has been carried out in collaboration with H. Ohno, T. Endoh, T. Hanyu, S. Sato, Y. Horio and their team members in Tohoku University as well as S. Datta, K. Camsari and their team members in Purdue University. The work is supported in part by the ImPACT Program of CSTI, JST-CREST JPMJCR19K3, and JSPS KAKENHI 19H05622.

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Manu Perumkunnil Program Manager, Imec Manu Perumkunnil Komalan completed his Integrated Masters in Nanotechnology from Amity University, India in 2011. He received his Ph.D. in Electrical Engineering from Katholieke Univ. Leuven, Belgium and in Computer Science from Universidad Complutense de Madrid in 2017. He then joined imec as a memory system architecture researcher. His research activity primarily involves exploration, analysis, and optimization of NVMs across the different layers of abstraction. He is also interested in system level design, bridging the gap between hardware and software. Currently, he is the Manager of the Memory INSITE program at Imec.

On-Chip 3D caches for advanced heterogenous SoCs – A cross layer look at discerning MRAM design and technology

requirements

For the most advanced CMOS nodes, because of diminished power, performance and cost returns, dimensional scaling must be now complemented by Design and System Technology Co-optimization (DTCO and STCO) strategies, so that SoC bottlenecks can be mitigated. Performance scaling for SoCs has plateaued over the last decade because dimensional technology scaling has not been able to mitigate the ‘Memory Wall’ problem. This problem will only exacerbate with Machine Learning, Artificial Intelligence, Vision, and other data dominated application domains coming to the forefront and also SRAM Power Performance and Area (PPA) gains saturating at advanced nodes.

To this end, it has become increasingly clear that 3-D integration and partitioning schemes can offer potential routes to continue scaling and tackle the Memory Wall via DTCO and STCO innovations. This can be via enabling higher integration density, heterogeneous (and novel) technology integration and extending the number of functions per 3-D chip. The 3-D integration scene has attracted a lot of interest over the past decade with demonstrations as well as commercial products like chiplets (AMD Rome, Milan in EPYC products) and 3D stacking (Intel Lakefield) more recently.

In this talk, I will give an overview for the need of 3D on-chip cache like memories in highly heterogenous advanced SoCs for the future based on commercial references of today like the Apple 13, Kirin 990 etc via a top-down approach. Following this, based on cross layer exploration results and validation by means of a functional stacked 3D STT-MRAM array, design and technology specifications for MRAM memories (namely STT and SOT) needed to make these feasible options for 3D on-chip cache like memories are derived.

PANEL DISCUSSION:

What Do We Need to Take MRAM to the Next Level?

Moderator: Luc Thomas Senior Director, Applied Materials Luc Thomas is a Senior Director at Applied Materials, where he manages MRAM programs. Prior to joining Applied Materials in March 2019, he was a Principal Technologist in the STT-MRAM R&D group at TDK-Headway Technologies, and a Research Staff Member at the IBM Almaden Research Center. He has authored and co-authored more than 100 publications and patents on magnetic and spintronics materials and devices. He received his Ph.D. in Physics in 1997 from the University Joseph Fourier in Grenoble, France, and was elected fellow of the American Physical Society in 2012. Panelists: Simone Bertolozzi Technology & Market Analyst, Yole Simone is a Technology & Market Analyst at Yole Développement (Yole), working with the Semiconductor, Memory and Computing division. He is a member of Yole’s Memory team and contributes daily to the analysis of memory markets and technologies, their related materials, and fabrication processes. Previously, Simone conducted experimental research in the fields of nanoscience and nanotechnology, focusing on emerging semiconducting materials and their device applications. He has authored or co-authored more than

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15 papers in high-impact scientific journals and was awarded the Marie Curie Intra-European Fellowship. Simone obtained a PhD in Physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland), where he developed flash memory cells based on heterostructures of 2D materials and high-κ dielectrics. Simone also earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude. _____________________________________________ Gouri Sankar Kar Program Director, Imec

Gouri Sankar Kar received the PhD degree in semiconductor device physics from the Indian Institute of Technology, Khragput, India in 2002. From 2002 to 2005, he was a visiting scientist at Max Planck Institute for Solid State Research, Stuttgart, Germany, where he worked with Nobel Laureate (1985, Quantum Hall Effect) Prof. Klaus von Klitzing on quantum dot FET. In 2006, he joined Infineon/Qimonda in Dresden, Germany as lead integration engineer. There he worked on the vertical transistor for DRAM application. In 2009, he joined imec, Leuven, Belgium, where he is currently program director. In this role, he defines the research strategy and vision for SCM, DRAM, FeRAM and MRAM programs both for stand-alone and embedded applications. He has authored, co-authored more than 200 peer-reviewed publications, many articles and holds patents in the memory domain. _____________________________________________ Daniel Worledge Distinguished Research Staff Member and Senior Manager, IBM Dr. Worledge received a BA with a double major in Physics and Applied Mathematics from UC Berkeley in 1995. He then received a PhD in Applied Physics from Stanford University in 2000, with a thesis on spin-polarized tunneling in oxide ferromagnets. After joining the Physical Sciences Department at the IBM T. J. Watson Research Center, he invented and developed Current-in-Plane Tunneling (CIPT), enabling fast measurements of magnetic tunnel junctions. In 2003, Dr. Worledge became the manager of the MRAM Materials

and Devices group, and in 2013 he became Senior Manager of MRAM. He discovered perpendicular magnetic anisotropy in CoFeB/MgO and led the team to demonstrate the first practical perpendicular magnetic tunnel junctions for Spin Torque MRAM. _____________________________________________

Seung Kang Director of Engineering, Qualcomm Seung Kang is a recognized semiconductor technologist who has holistically driven system-centric innovations of device, circuit design, and chip architecture. He built and led an advanced memory team at Qualcomm who pioneered embedded STT-MRAM and delivered the industry-first product prototype for mobile SOC. He currently leads a team for developing sub-5nm CMOS logic architecture, circuit, and co-optimization methodology. He received Ph.D. from U.C. Berkeley and both B.S. and M.S. from Seoul National University, Korea. Dr. Kang has published >100 papers and given >70 keynote and invited speeches. He served as Distinguished Lecturer for the IEEE Electron Device Society from 2014 to 2018 and as Visiting Professor at the Center for Innovative Integrated Electronic Systems of Tohoku University. He holds >240 granted US patents. Ko-Min Chang Senior Director, NXP Semiconductor Ko-Min Chang is a Senior Director at NXP. He joined Motorola 35 years ago after receiving the Ph.D from The Ohio State University. He initiated the development of many generations of proprietary embedded flash processes which served as the foundation of a long history of popular Motorola/Freescale MCU product families. Many of the flash cells and array concepts developed by the team were published and were subsequently adopted by other industry players for embedded applications serving automotive, industrial, and consumer segments. His focus in recent years has shifted to discovering and evaluating technologies that hold promising features to satisfy the explosive demand on user experiences. Ko-Min holds 35 US patents and served on IEDM and VLSI technical committees.

12th MRAM Global Innovation Forum

INTERMAG 2021, 27 April 2021

1st Forum: San Jose, California 2nd Forum: Tokyo, Japan 3rd Forum: Paris, France 4th Forum: Seoul, South Korea 5th Forum: Tokyo, Japan 6th Forum: Santa Clara, California 7th Forum: Zurich, Switzerland 8th Forum: Seoul, South Korea 9th Forum: San Francisco, California 10th Forum: San Francisco, California 11th Forum: San Francisco, California

Chair: Bernard Dieny (SPINTEC, Univ. Grenoble Alpes /CEA/CNRS, France)

Program Co-Chairs:

Luc Thomas (Applied Materials, USA)

Kevin Garello (SPINTEC, France)

Acknowledgements: This Forum is the 12th of a series initiated by Samsung Semiconductor in 2013. We are grateful to this year’s Forum Sponsors, our two partners: