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Transcript of Virginia Commonwealth University School of Engineering DEPARTMENT OF ELECTRICAL AND COMPUTER...
Virginia Commonwealth UniversitySchool of Engineering
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Embedded Systems-EGRE 631
TECHNO*Toward an Interactive Environment for Embedded Systems Design
Fadi Obaidat
Dr. Jerry Tucker
[April 2009]
Embedded Systems:•Embedded System: is a special purpose/custom design computer used to control certain device.
•Need to be able to work with very limited resources (memory, power)
•and often has to work in a real-time environment.
•Employ a combination of hardware and software to perform a specific function.
•It is typically part of a larger system that may not necessarily be a ‘computer’ and works in a reactive and time-constrained environment.
Using Of Embedded Systems:Cars IndustryFlight Control SystemsMars Exploration RoverMedical equipments and many other
applications …
FPGAs Based Embedded Systems:
High performance.Design Flexibility.Low cost.Reconfigurability.
Objectives: Establishing an interactive environment
which enables us to insert or replace HW/SW modules/applications written in VHDL/C.
Building Real Time Hardware Simulation to allow the user to see the results in real time.
About TECHNO* System: Xilinx Spartan 3E FPGA 500K:
HDL: custom design, coprocessor… Soft-core MicroBlaze Processor
C: either simple applications or under uClinux HDL interfaces for the monitor and keyboard…. To achieve and test the objectives of the project, and to show
the capabilities of the system, Two HW/SW applications were implemented and chosen because of the need to the HW speed and time-accuracy, and the SW flexibility.
Frequency Counter Cycle Accurate Counter
Components and Resources: Input Units: 8-Swithches, 4-Buttons, and or
Keyboard. Output Units: 8-LEDs, 4 digits 7-Segment-
Display, Monitor or Data Show. Logic and Processing Resources: 500K
Spartan 3E FPGA, and Softcore MicroBlaze processor (part of 500k).
Digilent Nexys2 Board:
http://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdf
Spartan 3E:
Spartan 3E 500K FPGADigilent Board
http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
Main HDL Modules: Monitor Interface ROM (.coe file) RAM (Look Up Table) Character Converter Clock Divider Frequency Counter Cycle Accurate Counter …... Not in use Keyboard Interface, buttons and
7-Sigment-Display…
Block Diagram of TECHNO*K
eybo
ard
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
RAM LUT(20*6):Inputs: row_address[5..0], column_address[5..0],
input_data[3..0], & clock_25Mhz.
Outputs: output_data[3..0].
Function: takes the results of any algorithm and time stores them in specific registers attached to
specific location on the screen, in the same time it outs its contents to the ROM through character converter module.
clock_25Mhz
row_address[5..0]column_address[5..0]input_data[3..0]
output_data[3..0] 0001
Value to be shown on screen at this moment
Data to be shown on screen
Current location address on screen
RAM (20*6)
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Character Converter:Inputs: RAM_out[3..0] & clock_25Mhz.Outputs: Character address[5..0].
Function: Get the address of the number or character that will be shown on screen and pass
it to the ROM to be displayed on the screen.
100111
Output of RAM Data goes to the ROM, addres of that char.
RAM_out[3..0]
clock_25MhzChar. add[5..0]
Character Converter
0111=7
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
ROM(64*8*8):Inputs: char_address[5..0], font_row[2..0] & font_col[2..0].
Outputs: rom_mux_output.
Function: used to generate dots on a video display . Each character is represented by an 8 by 8
pixels
binary. Font data and its addressees are stored in
a .coe memory initialization file.
char_address[5..0]font_row[2..0]font_col[2..0]
rom_mux_output
ROM
000001000-111000-111
‘1’ at each pixel we want to make dot on
Address of ‘A’ = 1
ROM contents:Address Char. Data
000001000 00011000
000001001 00111100
000001010 01100110
000001011 01111110
000001100 01100110
000001101 01100110
000001110 01100110
000001111 00000000
This is an example
That show how the Binary
of the character A stored
in the .coe file (ROM)
Char address: 000001
Font row: 000-111
Font col.: 000-111
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Monitor:Inputs: red_out, green_out blue_out, horiz_sync,
ver_sync.
Outputs: dots drown on screen.
Function: takes the outputs of the monitor interface and draw them pixel by pixel on
screen.
Monitor Pins
PIN# SIGNAL PIN# SIGNAL
1 RED 0.7v 9 NC
2 GREEN 0.7v 10 SYNC RTN
3 BLUE 0.7v 11 ID0
4 ID2 12 ID1 or DDC DATA
5 GND 13 HSYNC
6 RED SHIELD 14 VSYNC
7 GREEN SHIELD 15 ID3 or DDC CLOCK
8 BLUE SHIELD
Monitor Pins
Monitor Interface (60 frame/sec):Inputs: 3-red, 3-green, 2-blue, & clock_25Mhz.
Outputs: 3-red_out, 3-green_out, 2-blue_out, horiz_sync, ver_sync, pixel_row[9..0]&
pixel_column[9..0].
Function: generates horizontal and vertical signals to synchronize the drown eight bit colors on
each
pixel.
clock_25Mhz
redgreenblue
3-red_out3-green_out
2-blue_out
pixel_row[9..0]pixel_column[9..0]
ver_sync_outhoriz_sync_out
Monitor Interface
Monitor
1
00
go to the RAM and ROM to make sync between pixels and Char
Tell monitor to refresh anew row of 640pixels
v
h
http://www.altera.com/literature/univ/upds.pdf
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Clock Divider:Inputs: clock_50Mhz.
Outputs: clock_25MHz.
Function: used to generate appropriate, a 25MHz, clock signal to be used by monitor interface.
clock_50Mhz clock_25MHz
Clock Divider
25 MHz50Mhz
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
TECHNO* Applications:Frequency Counter:
Measure the frequency of an external signal.
Cycle Accurate Counter: Measure the number of cycles needed to
execute certain C function or program.
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Frequency Counter:Inputs: IC12 pin#5 external clk and 50MHz clk.
Outputs: 1-8 decimal digits represent the frequency in Hz.
Function: Counting the number of positive edges of the guest signal and store the result in 8
registers to be displayed on the screen.
frq_clk
Frequency Counter
Guest CLK
Frq_value [32..0]
Reg0Reg1Reg2Reg3Reg4Reg5Reg6Reg7
clock_50Mhz50Mhz
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Accurate Cycle Counter:Inputs: Start_Done’ [C program] and 50MHz clk.
Outputs: decimal digits represent number of cycles/prog.
Function: Counting the number of clocks between the start flag and the end flag => Logic
Analyzer . //C_Function
Done_Start++;//=01;
Function()
{ ……….
……….
………
}
Done_Start++;//=10;Start_Done’
Frequency Counter
#clks [32..0]
clock_50Mhz50Mhz
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
MicroBlaze:
http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf
Soft Core - reduced instruction set computer (RISC)32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Keyboard*:
Inputs: mechanical input by user hand.
Outputs: serial data & keyboard clock
Function: send a serial data to the keyboard interface , each 8-bit serial data represent a scan
code to the pressed button.
Keyboard PS/2pins
PS/2 KEYBOARD
PIN# SIGNAL PIN# SIGNAL
1 DATA 4 +5
2 NC 5 CLOCK
3 GND 6 NC
If you pressed button ‘A’ the keyboard send 00011100
Time 0Time 7…
Keyboard Interface*:Inputs: keyboard_clk, keyboard_data, clock_50Mhz,
reset & read.
Outputs: scan_code[7..0] & scan_ready.
Function: converts the serial data from the key board to parallel format to produce the scan
code output.
Keyboard Interface
keyboard_clkkeyboard_dataclock_50Mhzresetread
scan_code[7..0]
scan_ready
Serial data of ‘A’ =00011100
Ex:Scan code of ‘A’ =1C
Ex:
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Key
boar
d
Monitor
Key
boar
d C
ard Mo ni to r C
a rd
ROM
Frequency CounterClock Divider
Conv. Number
RAM
50 MHz
In this area:You can add or replaceany VHDL module or C function.
Cycle Acc. Counter
IC12 pin#5
Interface
Char. Converter
Converting Number*:Inputs: scan_code[7..0] & clock_50Mhz.
Outputs: total_binary_no.[7..0].
Function: level I:convert the scan code of the number to its real value .
level II: calculate the total number entered by keyboard .
Converting Number
scan_code[7..0]
clock_50Mhztotal_binary_no.[7..0]
Data from keyboard intr. After conv. it to its real values
254 = 00000010 00000101 00000100
11111110
Data to VHDL Module
2=0E=00001110
Scan code of 2
(2*100)+(5*10)+(4)
Device Utilization Summary:
Selected Device : 3s500efg320-4
Number of Slices: 1464 out of 4656 31% Number of Slice Flip Flops: 1767 out of 9312 18% Number of 4 input LUTs: 2431 out of 9312 26%
-Number used as logic: 2085 -Number used as Shift registers: 90 -Number used as RAMs: 256
Number of IOs: 29Number of bonded IOBs: 29 out of 232 12% Number of BRAMs: 7 out of 20 35% Number of MULT18X18SIOs: 3 out of 20 15% Number of GCLKs: 4 out of 24 16% Number of DCMs: 1 out of 4 25%
Conclusion: In this project we built an interactive environment for
embedded systems design. This environment allows the end user to insert C application and/or HDL custom design and get real time simulation through the monitor.
It allows to test the performance of a certain SW or/and HW application. In addition to that, it allows evaluating the efficiency of using coprocessor technique.
References http://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdf http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf http://www.altera.com/literature/univ/upds.pdf
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