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Proceedings of the Multi-Disciplinary Senior Design Conference

Project Number: P13571

D3 RUGGEDIZED CAMERA SYSTEM

Andy AnthonyElectrical Engineering

Peter HoodComputer Engineering

Stephen BrownElectrical Engineering

Adriana Becker-GomezFaculty Guide

Jose PortugalMechanical Engineering

Stephen GossComputer Engineering

Cameron StaunchMechanical Engineering

ABSTRACT

There are many existing camera designs with attributes that include high-definition video/imaging, a rugged structure, a small package, or precise still image capturing, but very few have the complexity to offer competitive value in all of these areas. The objective of this project was to design a tethered, miniaturized camera system that is ruggedized and weather resistant, while maintaining precise high-definition imaging (14 megapixels). The system is housed in an anodized aluminum body that can withstand a temperature range of -40°C to 105°C and adhere to IP64 environmental protection standards. Four circuit boards were required to meet the minimum size constraints, while still providing the electronics necessary to meet the specifications. Programs were written in a hardware description language (Verilog HDL) that implemented the selected data transmission protocol (CoaXPress).

INTRODUCTION

As technology advances, the presence of camera systems is becoming more frequent in everyday life. The demand for higher resolution images, faster frame rates, and a smaller form factor continues to grow. Processing speed has advanced in parallel, so the opportunities for real-time image processing techniques that include facial recognition, collision avoidance, and stereo vision have become a reality. In addition, there are many applications in which cameras need to be capable of consistent operation in extreme hot, cold, or moisture-laden environments. The intent of this design is to incorporate many of these aspects for potential use in machine vision, automotive, or military applications.

DESIGN PROCESSThe various system requirements were inherently divided into three different design processes: the mechanical design, the electrical/circuit board design, and the software design. Each discipline had its own unique requirements, yet each aspect of the design affected the project as a whole. The team had to work closely together across disciplines in order to meet the system requirements.

Mechanical Design Process Automotive conditions and IP64 standards were key factors taken into consideration in order to meet the system requirements. IP64 is an “Ingress Protection” rating defined by the IEC standard 60529. The first digit indicates a protection level against solids such as dust, and the second digit indicates a protection level against liquids. The

Copyright © 2013 Rochester Institute of Technology


design was also required to have a small cross-section of 30.48X30.48 mm (1.2”X1.2”) and be able to accept 3 different lens formats.

Enclosure DesignThe automotive conditions require that the enclosure be able to withstand temperatures ranging from -40°C - 105°C and fuel splatter. The components within the enclosure, on the other hand, have a maximum temperature tolerance of 80°C, above which it will no longer be operable. Under the anticipation that future components will be capable of reaching 125°C before failing, the product was designed using 125°C as the critical failing temperature. Due to these conditions, Aluminum 6061-T6 was chosen as the enclosure material in order to dissipate the heat generated by the inner components. The aluminum housing was anodized as a secondary process to reduce corrosion and abrasion due to harsh environments.

Figure 1 - Exploded view of assemblies.

The enclosure consists of four parts, creating three unique assemblies. The assemblies accommodate C-mount lenses, M3F focus modules, and M12 lenses. The general assembly of the product is as follows:

1) Place adhesive thermal pads on Housing, Cold Finger, and PCBs. 2) Add Gaskets. 3) Assemble PCB stack with Sensor Mount. 4) Adjust M12 lens and shim Sensor PCB with 0.0254mm (0.001”) shims into focus to counteract sensor

soldering tolerance. 5) Slide Assembly into rear housing and fasten BNC connector. 6) Slide Housing Front (M12/M3-F or C-Mount Housing Front). 7) Screw 4 socket-head screws into housing.8) Add Lens Cover or C-Mount Lens.

Due to the cross-sectional restriction and the limited space available, alignment pins and flat head screws on the sensor mount were used to ensure the optical center of the sensor aligned with the focal point of the lens. The circuit board stack up is fastened at both ends by the HD-BNC connector and the Sensor Board, so the tolerance stacking had to be evaluated. Using the assumption that production measurements of tolerances will produce a normal distribution and the maximum acceptable tolerance is at three standard deviations away, the total stack up tolerance is ±0.04mm. This influenced the housing length and in the worst case scenarios, the board to board connector would be pulled apart 0.06mm or compresses 0.02mm. The contact wipe distance of the board to board connectors are ~0.07mm so this is acceptable.

Sealing IntegrationTo ensure the IP64 water resistance and fuel resistance, Buna-N was chosen as the gasket’s elastomeric material for its high oil and temperature resistance, which is above 125°C. Each gasket, with a shore-hardness of 70A, was compressed about 15% ensuring a max sealing pressure of 3.35MPa (485psi). This sealing pressure ensured a safety factor of 340 when the enclosure is submerged under 1.00m of water (9.81KPa, assuming the inner-system pressure is constant at 1.0atm). Four gaskets were implemented in the assembly, between the Lens/Filter and Lens Holder, the Lens Holder and Housing Front, the Housing Front and Housing Rear, and the CoaXPress HD-BNC connector and Housing Rear.



Heat DissipationEach electrical component will generate heat; however, the FPGA and the inductor on the 24V to 3.3V switching power supply were the major generators of heat within the system. The FPGA is expected to generate a maximum of 1.0W of heat flow. To address this, an ultra conductive copper (alloy 101) implemented as a cold finger to dissipate heat directly from the surface of the FPGA to the outside aluminum enclosure and thermal pads were used to reduce thermal contact resistance. The inductor, being on the rear of the coax board, was able to be sunk directly to the rear of the housing by a thermal pad. FEA analysis determined a factor of safety for the boards to be about 1.0, considering an ambient temperature of 105°C and a failing temperature of 125°C for the electrical components. Since this module will need to be mounted to a metal or ceramic mount, conduction through the mount will allow for the factor of safety to only increase further depending on material and geometry. The thermal resistance from the location of the FPGA to ambient was 19°C/W, while the thermal resistance from the location of the inductor to ambient air was about 21°C/W. The temperature rise at a single location can be determined using the known resistances and power generations by the inductor and FPGA using super positioning.

Figure 2 - Heat Dissipation Simulation

Modal AnalysisIn any and all applications, the system will experience frequencies created by other systems, such as the engine of an automobile. These frequencies could be damaging to the camera system if any external frequencies match the fundamental frequency of the camera. In the case of an automotive application, the engine will be assumed to be a 4-stroke 8-cylinder engine that runs on average in a range of 1500 - 1700 RPM, which is equivalent to 100 - 113.3 Hz without any damping. Through an FEA analysis study, the fundamental frequency of the camera system was determined to be 2523.56Hz. In the analysis, it is assumed that mounting screws on the camera are fixed (rotation and lateral displacement is fixed at 0.0mm), so that only the frequency of the system is calculated. Any component with a Poisson’s ratio of 0.5 is lowered to 0.4 for the analysis (The FEA software requires that all Poisson’s ratio to be less than 0.5). Several of the smaller components were simplified and any threaded holes were removed for meshing purposes. Screws and seals are also excluded from this study.

Figure 3 - Modal Analysis Simulation Results



Frequency Number

Rad/sec Hertz Seconds

1 15856 2523.6 0.000396272 15897 2530 0.00039525

Table 1- Modal Analysis Results

Electrical / Hardware Design ProcessThe electrical design of the camera is indicative of the customer’s needs. The conceptual development began with elaborate research into high-speed interfaces, and was followed by selection of an FPGA. The FPGA selection was the driving force behind much of the design. It provided the versatility to support different types of image sensors, and it provided the high-speed transceiver architecture capable of transmitting data at speeds required by the customer needs.

High-Speed Interface ResearchThe first step in the design process was to become familiar with high-speed transmission interfaces that could meet the customer specifications. An initial concern was signal attenuation from the cable, so there needed to be a transmitter circuit capable of driving the signal over long distances. The selection of the driver would then influence the communication protocol (i.e. GigEVision, CameraLink, etc.) and hence, the type of software tools. A trade and analysis was conducted between different types of interfaces and their relevant characteristics. A summarized table of the results is listed in Table 2.

Interface Speed per Channel Length (m) Input Format Output Format

Bi-Directional Applicable

LVDS Ser/Des 500 Mbps 10 LVDS LVDS Yes, I2C Yes

HD/SDI 1.5Gbps 200 SDO/SDI HD-SDI No

FPGA-Link 3.12 Gbps 20 LVDS CML No No

USB 3.0 5 Gbps 3 No

Channel Link III SERDES DS92LX

1 Gbps 10 (STP*) LVCMOS CML Yes, I2C Yes

FPD-Link III SERDES 2.55 Gbps 10 (STP*) LVDS Yes, I2C No

Camera Link HS 2.1 Gbps per Cable -8 Supported

15-300 (copper or fiber optic)

10GBASEX 10GBASEX Yes Yes

Gigabit Transceiver TLK2711A

2 to 2.5 Gbps 100 VML, TTL Yes Yes

CoaXPress 6.25 Gbps 100 Yes Yes

Table 2 - Interface trade and analysis

After careful review of each standard, the customer expressed interest in CoaXPress. CoaXPress is an asymmetric high speed point-to-point serial communication standard for the transmission of video and still images, scalable over single or multiple coaxial cables. CoaXPress boasts a high speed downlink of up to 6.25 Gbps per cable for video, images and data, plus a lower speed, 20 Mbps uplink for communications and control. The standard can also supply power over the coaxial line and can provide high quality signal integrity over cables up to 100m in length [9].

FPGA ResearchThe FPGA selection required a similar trade and analysis which entailed extensive research into available products that would satisfy the design requirements. Xilinx Inc., Altera Corporation, and Lattice Semiconductor each had FPGA packages with high-speed transceivers that could possibly meet the dimension constraint. Ultimately the decision was made to use the Altera Cyclone IV GX; an FPGA that is minimal in size (measuring only 14mm x 14mm in its smallest package), contains the transceiver architecture to transmit up to 2.5Gbps, and is power efficient. The customer required the image sensor to operate at 1080p resolution at 30 frames per second, so the data rate for a 10 bit pixel depth is ~622 Mbps. Considering the CoaXPress protocol adds information at 1.33 times



the data rate, the data rate requirement is ~829 Mbps, which is easily in the range of the transceiver. The maximum data rate from the sensor is 14 megapixels at 15 frames per second at 10 bits per pixel, which equates to 2.1Gbps.

Camera Stack-up DesignThe printed circuit board (PCB) stack-up design features four different boards. The boards are essentially segregated by function: an image sensor board, FPGA board, power distribution board, and a CoaXPress data transmission board. The component selection and layout had to be very carefully planned to meet the limited space requirements. The boards interlock using fine pitch (0.4mm) Samtec connectors that can support 14 Gbps data rates and tiny spring-loaded pins that help to provide rigid stand-off distances. All schematic building and PCB design was done in Orcad Capture CIS and Orcad PCB Editor.

Figure 4 - Actual circuit board stack-up

Image Sensor BoardThe image sensor board contains an Omnivision OV14825 14.6 megapixel image sensor. The sensor board was designed by D3 Engineering specifically for this application. The raw pixel data generated by the image sensor can be output in parallel format or CSI-2 (a differential signal protocol in electronic devices). The differential signals require 100-ohm termination, so the board was fabricated with controlled impedance requirements.

FPGA BoardThe FPGA board’s main components include the Altera Cyclone IV GX FPGA, a 32 Mbit SPI Serial Flash memory, and a 156.25 MHz LVDS oscillator. The FPGA is programmed through a JTAG connection on the board which, in turn, programs the flash memory. The flash memory then transmits the configuration file needed to program the FPGA at power-up. The FPGA only requires an 8 Mbit configuration file, but the 32 Mbit Spansion Flash was selected due to availability.

The layout design includes ground and power plane cut-outs at the pins of the high-speed transceiver trace to minimize parasitic capacitance. In addition, multiple values of decoupling capacitors were placed as close to power supply pins as possible to create a low impedance profile over a wide range of frequencies. The objective was to reduce the amount of noise in the system, an essential feature in high-speed PCB design.

Power BoardThe power board serves to supply additional voltages required by the FPGA and to provide additional space for the M3F Focus module connector. It contains two switching power supply circuits, both containing the TPS62065 from Texas Instruments. The output voltages are 1.2V and 2.5V, respectively, at a maximum current of 2A. The input voltage from the CoaXPress Board is 3.3V. The TPS62065 operates at 3MHz fixed frequency, so considerably less power is dissipated as compared to a linear regulator. The discrete components (i.e. 1 μH inductor, 10 μF output capacitor) were selected based upon recommendations from the datasheet. The power supplies were overdesigned to accommodate worst-case power consumptions. A future goal of the project is to provide control of the M3F Focus Module via I2C (inter-integrated circuit) communication, so a flat flex cable connector is located on the board with necessary traces to the FPGA board.


Coax BoardFPGA Board

Power Board Image Sensor Board Board


CoaXPress BoardThe coax board is comprised of a 24V switching power supply and a transmitter circuit that complies with the physical layer of the CoaXPress standard. Due to the complex and sensitive nature of high-speed signal integrity, the reference design for the transmitter circuit (EqcoLogic EQCO62T20.3) was closely followed. The HD-BNC connector selection is different, however, because the customer required a secure connection that was not provided by the connector in the reference design. In addition, the TPS54260 from Texas Instruments was selected for the switching power supply circuit that converts the 24V supplied by power over CoaXPress (PoCXP) to the 3.3V necessary for successive step-downs and system operation. An important aspect of the converter was its 2.5 MHz switching frequency, because the EqcoLogic datasheet warned of crosstalk with the uplink channel when a low switching frequency power supply was used.

Software Design ProcessThe software design was broken up into two major parts. The first part is data capture where the image data coming from the sensor would be captured by the FPGA. The second part is data transmission where the data that was previously captured is transmitted to the host device to be processed. This modular design allows for a third stage of processing that may be added later where the data can be manipulated and filtered before it is transmitted. The processing stage was outside the scope of this project, but it was an important element that we had to keep in mind when designing the software. Thus it was a driving factor in the design of stage 1 as the data had to be able to be consumed by the processing unit that will be made past the end of this project.

Each stage operated in its own clock domain. This means that each stage on the data path operated independently of the other. Both domains share a queue for their data with independent read and write clocks. When the data capture domain captures data from the image sensor it puts the data in the queue in order to prepare it for transmission. When data is ready in the queue, the transmission domain pulls it out of the queue, packages it, and sends it to the host device.

Stage 1 - Data CaptureThe image data coming from the image sensor is delivered in parallel on the positive edge of the image sensor clock in 10 parallel bits. Before each frame of data is queued for transmission, an image header needs to be inserted into the stream as meta data for each frame. The image header contains information about the frame that the rest of the data stream will be receiving. Before each horizontal row of pixels a line marker also needs to be inserted into the data stream. The line marker separates the lines of data and acts as an indicator that a new line is being processed. These are inserted into the queue before the pixel data. The image sensor will indicate to the FPGA when a new row and frame are about to happen. In that time, there are several clock cycles that the FPGA will use to insert that data via a controller that dictates how most of the meta data flow in these two stages are run.

Figure 5 - Software Architecture



Before the data can be transmitted the transmitter needs to know what type of data is being sent. For example, data in the image header is control data, but data from the sensor is not control data. This is done by adding an extra bit preceding each 8 bit grouping indicating the data type. Once the data has its data type indicator it is queued to be transmitted. These control bits are organized in a way that makes it easy to separate them from the relevant data, so the extra bits are not processed and the processing is thrown off.

Stage 2 - Data TransmissionOnce the data is queued it is packetized to be transmitted. This involves adding a packet header and packet footer to each packet. The packet header adds data that keeps track of how many packets have had the same unique stream ID as well as how big the amount of data the packet will contain. The packet footer contains a 32-bit CRC that is calculated over the stream data. The CRC is constantly recalculated and reinserted as new packets come. Since there is no guarantee that there will be data available for transmission the transmitter will insert an IDLE command into the data stream so the host knows that no data is available for transmission. The transmitter will always have a continuous stream of data to transmit to the host where it will be unpacked and processed properly given it adheres to the design rules and decisions made in the first two stages.

RESULTS & DISCUSSIONMechanical TestingThe prototype housing and circuit boards assembled well without interference issues. The first iteration of O-ring groove geometries allowed for a compression range of 20-40% (depending on machining tolerance). Although this compression allows for maximum sealing, it did not allow for easy assembly. Thus, the groove geometry was changed in the model, allowing for 15% compression in the most recent CAD model. Additionally, the ordered parts were slightly different dimensionally than the CAD provided on their website, which affected the seal pressure.

The simulated thermal test was supported by an experimental thermal test. Using a power resistor, the heat generation was simulated at the FPGA and inductor locations. In comparison to the simulated data, the experimental test data had 20% less thermal resistance. Several factors could have played into the lower expected temperature. The hole drilled into the housing for wires provided an exit for heated air to flow, resulting in an alternative path and reduced resistance of the system. Additionally, the power resistor used was not idealistic.

Electrical / Circuit Board TestingThe circuit boards were first tested for shorts on the power supply planes through test points included in the design. During testing, a short between the power-board-to-FPGA-board was noticed. Thus, two pins had to be removed from the connector on the FPGA side to eliminate the short and still maintain the proper connections. Next the power boards were connected to 3.3V individually to test for the appropriate voltages. After verification of the proper voltages of 1.2V and 2.5V, the FPGA board and image sensor board could be connected and tested. Then the CoaXPress board was connected to 24V through the EqcoLogic evaluation kit and the full system was verified for power.

The next tests were to verify the functionality of the JTAG connection which programs the FPGA. A clock divider program was written in Verilog HDL and the .sof file (SRAM object file) was synthesized and fit into the FPGA. After that test was successful, the programming of the flash memory was verified by converting the .sof file to a .jic (JTAG indirect configuration) file and once again programming the FPGA. The power was then cycled and the divided clock was seen on the oscilloscope after power-up, thus verifying that the flash was programmed successfully.

The next test was to verify the communication with the image sensor. The image sensor would not output data until a number of register writes had occurred through I2C communication. An open core I2C solution was used through Qsys and the pixel data output was verified through the on-chip logic analyzer, Signal Tap.

The only remaining test was to verify the signal integrity of the transceiver. The test is unable to be performed until the software is fully functional.



Software TestingEach software block was tested independently with the observation of their inputs and outputs used to validate their functionality. Several block outputs were compared to constant values dictated by the CoaXPress standard and were found to be correctly output upon the input being asserted. The data capture block was tested via sending synthetic data that represented pixel data. The output of the capture was checked against the synthetic data pattern and the results were correct. The transmitter was also tested using a synthetic data pattern. The FPGA has a built-in loopback function that allows the programmer to read back the transmitter output to the onboard receiver which was used to test the transmitter. The result was a latency of 13 clock cycles from transmission to reception and the received data was correct.

CONCLUSIONS & RECOMMENDATIONSThe intent of this design was to produce a fully functioning camera system that met ambitious customer needs. Virtually every aspect of the hardware design has met the engineering design specifications. The only shortcoming for the mechanical design was an overdesigned compression ratio on an O-ring, and the CAD model was easily refined for future iterations. The electrical design has been almost completely verified (with a few modifications), with the exception of signal integrity only fully realized with working software. Although the system is not currently displaying an image, the software can continue to mature into a working prototype. The system integration remains, but the scope of the project looks to be attainable in the near future.

Future revisions of this project could include the design of a frame grabber system that processes the data received from the camera. There are many image processing techniques that could be implemented, and multiple ruggedized cameras could be connected in parallel to a multi-core processor. There are a wide variety of commercial/industrial applications that could find a use for this camera.



References:[1] Texas Instruments, “3-MHz 2A Step Down Converter in 2x2 SON Package”, TPS62065 datasheet, Mar.

2010 [2] Texas Instruments, “3.5V to 60V INPUT, 2.5A, STEP DOWN CONVERTER WITH ECO-MODE ”,

TPS54260 datasheet, Dec. 2010 [3] EqcoLogic NV, “EQCO62T20.3 6.25 Gbps Asymmetric Coax Driver”, EQCO62T20.3 datasheet, Apr.

2010[4] Altera, ”Cyclone IV FPGA Device Family Overview”, EP4CGX22 datasheet, Feb. 2013[5] Spansion, “32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi

I/O Bus”, S25FL032P datasheet, Feb. 2009[6] OmniVision, “OV14825 Color CMOS 14 Megapixel (4416 x 3312) Image Sensor with OmniBSI

Technology”, OV14825 datasheet, Apr. 2012[7] Theodore L. Bergman. Fundementals of Heat and Mass Transfer. Wiley. [8] Green, Itzhak . STRESSES AND DEFORMATION OF COMPRESSED ELASTOMERIC

O-RING SEALS. Georgia Institute of Technology[9] JIIA, “CoaXPress Standard”, CoaXPress standard, Dec. 2010

ACKNOWLEDMENTS

D3 Engineering (sponsor) – Scott Reardon, Jason Enslin, Jim McGarvey, Alex Sojda, Ben McGee, and David Collins

Lightforce Technology – Peter Hammond

Dr. Antonio Mondragon

Altera Corporation – Bill Jenkins and Bob Spurr

Arrow Electronics, Inc. – Gary Fredericks

RIT Machine Shop Personnel


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