Vic Report

Vectored Interrupt Controller 2009-10

CHAPTER 1

INTRODUCTION

An AMBA based microcontroller typically consists of a high performance system

backbone bus, able to sustain the external memory bandwidth, on which the CPU on-chip

memory and other direct memory access [DMA] devices reside. This bus provides a high

bandwidth interface between the elements that are involved in the majority of transfers also

located on the high performance bus is a bridge to the lower bandwidth APB, where most of

the peripheral devices in the system are located vectored interrupt controller is one of the

high performance system bus slave. The figure 1.1 shows an example of AMBA based

system.

Figure 1.1:A typical AMBA system

DEPT OF E&C, SJCIT 1

UART

High-bandwidth

RAM

ARM Processor

PIO

B

R

I

D

G

High-performance

Memory interface

Vectored interrupt Controller

DMA Controller

KeypadTIMER


The AHB slave main function is an interface unit that allows AHB. Logic to initiate a data

transfer on the AHB. The AHB specifies the type transaction to be executed on the slave through a

user friendly interface. AHB is optimized to interface with VIC to initiate data transfer on the AHB.

Once the VIC received the request from AHB bus, executes the transaction on the AHB with

the AHB protocol.VIC AHB slave interface will handle only one response state interrupts.

At this point we propose a vectored interrupt controller with which having the following

specifications

Uses the AMBA AHB protocol.

Up to 32 interrupt source.

High level sensitive, interrupt source type.

Support for 32 vectored interrupts.

Fixed interrupt priority level.

Fixed IRQ and FIQ generation.

Software interrupts generation.

Interrupt enable.

Raw interrupt status.

Interrupt source get acknowledgment.

Memory space offset address start with 00.

VIC can provide an interrupt controller peripheral for AMBA based SOCs.VIC captures interrupt

requests from 32 interrupt inputs. Each interrupt input independently configures for level sensitive,

interrupt request and for active high interrupt requests. VIC supports for fixed priority scheduling

method to handle the interrupt requests. VIC support for 4 FIQ and 28 IRQ requests. VIC

acknowledges the interrupt requests.



CHAPTER 2

BLOCK DIAGRAM OF VECTORED INTERRUPT CONTROLLER (VIC)

The vectored interrupt controller is mainly divided in to three blocks namely

1. Peripheral interface

2. CPU interface

3. AHB slave interface

The Block diagram of vectored interrupt controller is shown in figure 2.1

Figure 2.1:Block Diagram of Vectored Interrupt Controller



2.1 Peripheral Interface

The Peripheral interface is composed of only one functional unit called Interrupt request logic

2.1.1 Interrupt Request Logic

The interrupt request logic receives the interrupt requests from the peripheral and

combines them with the software interrupt requests. It then makes out the interrupt requests

that are not enabled and steering logic is used to split the interrupt request into fast interrupt

request and general interrupt request two separate acknowledgements are send back for fast

interrupt request.

2.2 CPU Interface

The CPU interface consists of two sub blocks namely FIQ request handling and IRQ

request handling.

2.2.1 FIQ request handling

Here we use fixed priority logic for lower 4 bits of Intr_src and generates the nfiq

signals which is active low and selects the vector address of the respective peripheral from

vectored table to the CPU.

2.2.2 IRQ request handling

Here it was fixed priority logic for upper 28 bits of Intr_src and generates the nirq

signal which is active low and selects the vector address of the respective peripheral from

vectored table to the CPU.

2.3 AHB Slave

An AHB bus slave responds to transfers initiated by bus masters within the system.

The slave uses a HSEL select signal from the decoder to determine when it should respond to

a bus transfer. All other signals required for the transfer, such as the address and control

information, will be generated by the bus master.



2.4 Peripheral Interface

2.4.1 Interrupt Request Logic

Figure 2.2: Interrupt request logic

The interrupt request logic receiver the interrupt request from the peripheral and combines

them with the software interrupt requests to either IRQ status or FIQ status

Soft_Int [Software Interrupt Register ]:

The read and write software register, with address offset 0x080, generates

software interrupt. Soft INT is 32 bits register, setting a bit generation a software

interrupt masking. A high bit sets the corresponding bit in the VICSOFTINT register

a low bit has no effect

Enable_ Int[Interrupt Enable Register]:

The read write interrupt enable register, with address effect of 0x084, enable

the interrupt request id masking lines by masking the interrupt sources for the IRQ

interrupt



Interrupt enable register is a 32 bits register which enable the interrupt request lines

setting a bit interrupt enabled, Enable interrupt request to processor setting a bit 0

interrupts are disabled, on reset all interrupts are disabled A high bit sets the

corresponding bits in interrupt enable register, a low bit has no effect.

Int_Status [Interrupt Status Register]:

It has an address offset of 0x088, provides the status of the source interrupt,

and software interrupt to the interrupt controller.

Int _Status is 32 bit register, shows the status of the interrupts before masking by the

enable registers .A high bit indicates that the appropriate interrupt request is active

before masking.

Interrupt request logic receives 32 Intr_src lines from CPU peripherals and

combines with the software interrupt which are written by CPU on Soft_Int register and

enable the user selected interrupts by gated enabling and separate the 32 request lines into 4

fast interrupt request and 28 general interrupt request and also encode the filtered output

generates two separate request id for FIQ’s and IRQ’s.

2.5 CPU Interface

2.5.1 FIQ request handling

The FIQ request handling shown in figure 2.3 asserts the nfiq signal. i.e. if FIQ_status

is nonzero, set the nfiq as low. It selects the vectored address of the corresponding fast

interrupt request. Send it to CPU through AHB slave interface. It will select the vectored

address from the vectored address table, vectored address table is the memory configuration

space, which contain the subroutine of the each interrupt request. The vectored addresses in

the vectored table are programmable. FIQ_status acts as a select line for vectored address

selection. nfiq is active low signal for CPU.



Figure 2.3:FIQ request handling

2.5.2 IRQ Request Handling

The IRQ request handling shown in figure 2.4 Asserts the nirq signal. i.e., if

irq_status is nonzero, set the nfiq as low and selects the vectored address of the

corresponding interrupt request. Send it to CPU through AHB slave interface. It will select

the vectored address from the vectored address table, vectored address table is the memory

configuration space, which contain the subroutine of the each interrupt request. The vectored

addresses in the vectored table are programmable. IRQ_status acts as a select line for

vectored address selection. nirq is active low signal for CPU.



Figure 2.4:IRQ request handling

2.6 AHB Slave Interface

The AHB slave shown in figure 2.5 maps the memory configaration space with the interrupt

controller and perform the data transaction as AHB asserts its signal. In this block asserts

Hready_out as high and Hresp as OKAY, because we designed Interrupt controller as a

single slave.



Figure 2.5 AHB slave interface

2.7 Signal Details

2.7.1 AHB Slave Signals

Name Type Source Description

HCLK Input Clock source This clock times all bus transfers. All

signal timings are related to the rising

edge of HCLK.

HRESET Input Reset controller The bus reset signal is active HIGH



and is used to reset the system and

the bus.

HSEL Input Decoder Each AHB slave has its own slave

select signal and this signal indicates

that the current transfer is intended

for the selected slave. This signal is

simply a combinatorial decode of the

address bus.

HTRANS[1:0] Input Master Indicates the type of the current

transfer, which can be

NONSEQUENTIAL,

SEQUENTIAL, IDLE or BUSY.

HREADY_IN Input External slave Transfer done signal, generated by an

alternate slave. When HIGH,

indicates that a transfer is complete.

Can be driven LOW to extend a

transfer.

HWRITE Input Master When HIGH this signal indicates a

write transfer and when LOW a read

transfer.

HADDR[11:2] Input Master Systems address bus.

HREADY_OUT Output Slave Transfer done signal, generated by

the VIC. When HIGH, indicates that

a transfer is complete. Can be driven

LOW to extend a transfer.



HRESP[1:0] Output Slave Transfer done signal, generated by

the VIC. When HIGH, indicates that

a transfer is complete. Can be driven

LOW to extend a transfer.

HRDATA[31:0] Output Slave Read data bus, used to transfer data

from bus slaves to bus master during

read operations

Table 2.1: AHB Slave Signals

2.7.2 Peripheral Interface Signals

Name Type Source DescriptionINTR_SRC

(31 interrupt lines)Input Peripheral This is a one bit signal from each

peripheral. The signal is active

HIGH which indicates there is a

interrupt from respective peripheral.

RQST_ID_F [4:0] Output Interrupt Controller

Address bus, returns the address to

FIQ peripherals at the time of

acknowledgment.

RQST_ID_I [4:0] Output Interrupt Controller

Address bus, returns the address to

IRQ peripherals at the time of

acknowledgment.

ACK_F Output Interrupt Controller

When HIGH, Indicates the FIQ

interrupt acknowledgment to



peripherals.

ACK_I Output Interrupt Controller

When HIGH,indicates the IRQ

interrupt acknowledgment to

peripherals.

FIQ_status [4:0] Output Peripheral Interface

Indicates the FIQ signals status

IRQ_status [28:0] Output Peripheral Interface

Indicates the IRQ signals status

Table 2.2 :Peripheral Interface Signals

2.4.3 CPU Interface Signals

Name Type Source DescriptionFIQ_status [4:0] Input Peripheral

InterfaceIndicates the IRQ signals status

IRQ_status [28:0] Input Peripheral Interface

Indicates the IRQ signals status

NFIQ Output Interrupt Controller

FIQ request to processor

NIRQ Output Interrupt Controller

IRQ request to processor

VECT_ADDR[31:0] Output Interrupt Controller

Address bus ,contains vector

address of interrupt to processor

Table 2.3:CPU Interface Signals

CHAPTER 3



AMBA SPECIFICATION

On-chip communication standard for designing high performance embedded

microcontroller.

Three distinct buses are defined within the AMBA specifications

The advanced high performance bus [AHB]

The advanced system bus [ASB]

The advanced peripheral bus [APB]

A test methodology is included with the AMBA specification which provides an

infrastructure for modular macro cell test and diagnostic access.

The AMBA specification has been derived to satisfy the requirements such as

To facilitate the right first home developments of embedded microcontroller

product with one or more CPU or signal processors.

To be the only independent and ensure that highly reusable peripheral and system

macro cells can be migrated across a diverse range of IC processes and be

appropriate for full-custom, standard cell and get array technologies

To encourage modular system design to improve processor independence,

providing a development road map for advanced cached CPU cores and the

development of peripheral libraries

To minimize the silicon infrastructure required to support efficient on-chip and

off-chip communication for both operation and manufacturing test

An AMBA based microcontroller typically consists of high performance system

backbone bus, able to sustain the external memory based width, on which the CPU on-chip

memory and other direct memory access (DMA) devices reside. This bus provides a high

bandwidth interface between the elements that are involved in the majority of transfers. Also

located on the lower bandwidth APB, where most of the peripheral devices in the systems are

located.



Figure 3.1:AMBA Based SOC

3.1 AMBA AHB

AHB is a new generation of AMBA bus which is intended to address the

requirements of high-performance synthesizable designs. It is a high-performance system bus

that supports multiple bus masters and provides high-bandwidth operation.

AMBA AHB implements the features required for high-performance, high clock frequency

systems including

High performance

Pipelined operation

Multiple bus master

Burst transfers

Split transaction

An AMBA AHB design may contain one or more bus masters, typically a system would

contain at least the processor and test interface. However, it would also be common for a

Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus

masters.

3.2 AMBA ASB



ASB is the first generation of AMBA system bus. ASB sits above the current APB and

implements the features required for high-performance systems including

High performance

Pipelined operation

Multiple bus master

A typical AMBA ASB system may contain one or more bus masters( For example, at

least the processor and test interface). However, it would also be common for a Direct

Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters.

The external memory interface, APB bridge and any internal memory are the most

common ASB slaves. Any other peripheral in the system could also be included as an ASB

slave. However, low-bandwidth peripherals typically reside on the APB.

3.3 AMBA APB

The AMBA APB appears as a local secondary bus that is encapsulated as a single

AHB or ASB slave device. APB provides a low-power extension to the system bus which

builds on AHB or ASB signals directly.

The features of APB are

Low power.

Latched address and control

Simply interface

Suitable for many peripherals

An AMBA APB implementation typically contains a single APB bridge which is

required to convert AHB or ASB transfers into a suitable format for the slave devices on the

APB. The bridge provides latching of all address, data and control signals, as well as

providing a second level of decoding to generate slave select signals for the APB peripherals.

AMBA APB provides

the basic peripheral macro cell communication infrastructure. As a secondary bus from the

higher band width pipelined main system bus such peripherals typically



Have interfaces which are memory mapped register.

Have no high bandwidth interfaces.

Are accessed under programmed control

3.4 The External Memory Interface

Specific and may only here a narrow data path that may also support address access mode

which allows the internal AMBA AHB, ASB & APB modules to be tested in isolation with

system independent test sets.

Bus cycle: A bus cycle is a basic unit of one bus clock period and for the purpose of

AMBA AHB or APB protocol description is defined from rising edge transactions.

Bus signal timing is referenced to the bus cycle clock.

Bus transfer: An AMBA ASB or AHB bus transfer is a read write operation of a data

object, which may take one or more bus cycles. The bus transfer is terminated by a

completion response from the addressed slave.

The transfer sizes supported by AMBA ASB include byte (8-bit), half word (16- bit)

and word (32-bit) AMBA AHB addressing supports wider data transfer including 64-

bit and 128-bit transfers An AMBA APB bus transfer is a read or write operation of a

data object which always requires two bus cycles

Burst operation: burst operation is defined as one or more data transactions initiated

by a bus master, which have a consistent width of transaction setup per transaction is

determined by the width of transfer. No burst operation is supported on the APB.

CHAPTER 4



ARM INTERRUPT HANDLING

Interrupts which are kinds of exceptions are essential. It enables the system to deal

with external events by receiving interrupt signals telling the CPU that there is something to

be done-instead of the alternative way of doing the same operation by the pooling mechanism

which wastes the CPU time in looping forever checking some flags to know that the event

occurred.

Applies to: ARM1020/22E, ARM1026EJ-S, ARM1136, ARM720T, ARM7EJ-S,

ARM7TDMI, ARM7TDMI-S, ARM920/922T, ARM926EJ-S, ARM940T, ARM946E-S,

ARM966E-S, ARM9TDMI

Upon entry to the IRQ exception handler, the 'I' bit is set and further interrupts (IRQ)

cannot be recognized by the core until the handler explicitly re-enables further interrupts by

writing to the CPSR. Upon entry to the FIQ exception handler, both the 'I' bit and the 'F' bit is

set and further interrupts, fast or normal, cannot be recognized by the core until the handler

explicitly re-enables further interrupts by writing to the CPSR.

The IRQ/FIQ handler should not re-enable interrupts until it has acknowledged the

interrupt to whatever is driving the nIRQ/nFIQ input, otherwise the core will immediately re-

enter the interrupt handler.

Due to a pipeline hazard on later ARM cores, we should always ensure that there is plenty

of time between the acknowledgement and the re-enabling of the interrupts.

Consider the following piece of ARM code

STR r1, [r0] ; ack. interrupt by writing to the interrupt controller

MSR cpsr_c, r2; re-enable interrupt.


http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiib4wMtDXUcfr.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiKwI46gemI1o6.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kidoyUMrgIdmYd.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiWI2VbOCSnGuJ.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiHDsCpbKZZaJq.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ki7SKtKijypFF1.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiYeupZKxTQnvx.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiXeKrSgmb37l9.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiXXQR7IS2GAdK.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kialgF2khrUwab.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kidbR7AXaxRipw.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/kiQsxCmFZrVoBo.html

http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ki2k9QrE7Y96RD.html


On the ARM9TDMI and later cores, the STR write to external memory may occur as

little as one CLK cycle before the interrupts are re-enabled by the MSR instruction. Hence if

the interrupt controller takes longer than one ARM CLK cycle to clear the interrupt signals

into the core, it will re-enter the interrupt exception handler.

For this reason, ARM recommends that programmers acknowledge interrupts at the

very beginning of the exception handler. The exception handler should not re-enable

interrupts until the very end of the exception handler unless nested interrupts are being used.

If nested interrupts are being used, programmers should ensure that there is some padding

between the acknowledge and re-enable of interrupts to allow time for the interrupt signals to

change

Interrupts are enabled by clearing the I (for IRQ) or F (for FIQ) flags in the CPSR

with an MSR instruction. If an interrupt occurs as it is being enabled, the instruction

following the MSR instruction will still be executed.

The reason is that the new flags are only available to the control logic at the end of

the execution stage of the MSR instruction. The next instruction will have already been

decoded and enters the execution stage of the instruction pipeline just as the flags are being

changed.



CHAPTER 5

DESIGN OF INTERRUPT CONTROLLER

5.1 AHB Slave interface

5.1.1 State diagram

Figure 5.1:State transition diagram of AHB Slave interface.

There are 3 states IDLE, WR_DATA and RD_DATA. AHB bus asserts its signals to

set the state of the AHB slave interface. Hsel, Htrans, Haddr and Hready_in together

Qualifies the data transaction. Hwrite indicates Read or Write transaction on AHB bus.



IDLE: DATA read from registered address.

WR_DATA: Writes the current DATA to the registered address as per registered

HWRITE and register the current address.

RD_DATA: Reads the current DATA from registered address as per the registered

HWRITE and register the current address.



5.1.2 AHB Slave State Transition Table

Current state Next state Condition

Idle

Hsel=0 | Hready=0 | Htrans[1]=0

Idle

Hsel=0 & Hready=1 &

Htrans[1]=0 &Hwrite=1

HW_Data

Hsel=0 & Hready=1 & Htrans[1]=0 &Hwrite=0

HR_Data

HW_Data Hsel=0 | Hready=0 | Htrans[1]=0

Idle


HW_Data


HR_Data

HR_Data Hsel=0 | Hready=0 | Htrans[1]=0

Idle


HW_Data


HR_Data

Table 5.1: AHB Slave State Transition Table

Table 5.1 shows the state of all AHB signals while transmitting from one state to other state.



5.1.3 AHB Slave Timing Diagram

Figure 5.2: AHB Slave timing diagram

AHB slave timing diagram in figure 5.2 shows the timing analysis of AHB signal transaction. Setting Hsel=1, Htrans=10 or 11.



5.2 Interrupt Controller

5.2.1 Interrupt Controller State Machine

Figure 5.3:Interrupt controller state machine

Only two state RESOLVE and FORWARD. Interrupt controller enters the RESOLVE state

only when Hreset is high (1).

RESOLVE: Interrupt request from the peripherals are combined with software interrupts,

gated enable the interrupt request as programmer wish. Using steering logic splits the

interrupt requests into FIQ_status and IRQ_status and assert the Ack_F and Ack_I.

FORWARD: Assert the nfiq and nirq as per FIQ_status and IRQ_status respectively.



5.2.2 Interrupt Controller State Table

PRESENT STATE CONDITION NEXT STATE

RESOLVE Ack_F=0 &Ack_I=0 RESOLVE

Ack_F=1 &Ack_I=1 FORWARD

FORWARD Int_Ack_F =0 &Int_Ack_I=0 FORWORD

Int_Ack_F =1 &Int_Ack_I=1 RESOLVE

Table 5.2:Interrupt Controller State Table

5.2. 3 Interrupt Controller Timing diagram



Figure 5.4: Interrupt controller timing diagram

5.3 Summary Of Registers



REGISTER ADDRESS

OFFSET

TYPE DESCRIPTION

Vect_addr 0 00 R/W Contains ISR address for Int_src [0]



Vect_addr 3 0C R/W Contains ISR address for Int_src [3]




Vect_addr 7 1C R/W Contains ISR address for Int_src [7]



Vect_addr 10 28 R/W Contains ISR address for Int_src

[10]

Vect_addr 11 2C R/W Contains ISR address for Int_src

[11]


[12]


[13]




[14]


[15]


[16]


[17]


[18]


[19]


[20]


[21]


[22]


[23]


[24]


[25]


[26]




[27]


[28]


[29]


[30]


[31]

Sft_Int 80 R/W Setting a bit HIGH generates a

software interrupt for the selected

source before interrupt

masking.

Enable_Int 84 R/W Enables the interrupt request lines,

which allow the interrupts to reach

the processor

Int_Status 88 RO Shows the status of the raw

interrupt source inputs after

masking by the enable register

Int_ack 8C R/W Acknowledgement from CPU to

interrupt controller ,as CPU has

received the request

Vect_addr FIQ 90 RO Contains the value of the respective

vector address of nfiq when nfiq is



high

Vect_addr IRQ 94 RO Contains the value of the respective

vector address of nirq when nirq is

high

Table 5.3:Register Space of registers

CHAPTER 6



CODING

6.1 Verilog Code For Interrupt Controller

module int_cntr(hclk,hreset, int_src, nfiq,nirq,ackf,acki, rqstidf,rqstidi);

//primary input

input hclk,hreset;

input [31:0] int_src;

//primary outputs

output ackf,acki,nfiq,nirq;

output [4:0] rqstidf,rqstidi;

reg ackf,acki,nfiq,nirq;

reg [4:0] rqstidf,rqstidi;

//reg [31:0] vect_addrf,vect_addri;

//states

parameter RESOLVE=1'b0;

parameter FORWARD=1'b1;

//external register

reg [31:0] soft_int;

reg [31:0] enbl_int;

reg [31:0] int_status;

reg [3:0] fiq_status;



reg [27:0] irq_status;

reg int_ack_f;

reg int_ack_i;

reg [31:0] vectaddr [0:31];

//internal register

reg state;

reg [4:0] rqstidf_cnt=00000;

reg [4:0] rqstidi_cnt=00100;

//combinatorial logic involved

wire [31:0] fltr_int_src_wir;

wire nfiq_wir;

wire nirq_wir;

// for forloop and for ISR address assingment

integer j,i;

integer fiqaddr;

integer irqaddr;

// combinatorial logic

assign fltr_int_src_wir=(int_src|soft_int)&enbl_int;



assign nfiq_wir=~(|fiq_status);

assign nirq_wir=~(|irq_status);

always@ (posedge hclk or negedge hreset)

begin

if(~hreset)

begin

state<=RESOLVE;

ackf<=1'b0;

acki<=1'b0;

nfiq<=1'b1;

nirq<=1'b1;

end

else

//state logic

begin

case(state)

RESOLVE:

begin

ackf<=(|fltr_int_src_wir[3:0]);

acki<=(|fltr_int_src_wir[31:4]);

nfiq<=1'b1;



nirq<=1'b1;

int_ack_i<=1'b0;

int_ack_f<=1'b0;

state<=(ackf||acki)?FORWARD:RESOLVE;

end

FORWARD:

begin

ackf<=1'b0;

acki<=1'b0;

nfiq<=~(|fiq_status);

nirq<=~(|irq_status);

state=(int_ack_i && int_ack_f)?RESOLVE:FORWARD;

end

endcase

end

end

//encoder for request id genaration

always @(posedge hclk)

begin

if(state==RESOLVE)



begin

int_status=fltr_int_src_wir;

fiq_status=fltr_int_src_wir [3:0];

irq_status=fltr_int_src_wir [31:4];

for (j=0; j < 4; j = j + 1)

begin : fiq_id_loop

if(fltr_int_src_wir[j])

rqstidf=j;

disable fiq_id_loop;

end

for (i = 4; i < 32; i = i + 1)

begin : irq_id_loop;

if(fltr_int_src_wir[i])

rqstidi=i;

disable irq_id_loop;

end

fiqaddr=rqstidf;//integer convertion

irqaddr=rqstidi;//integer convertion



end

end

endmodule



6.2 Verilog Code AHB Slave

module ahb_slave (HCLK, HRESET, HREADYIN, HREADYOUT, HRESP,

HADDR, HWDATA, HRDATA, HWRITE, HTRANS, HSEL,rqst_idf,rqst_idi);

input HCLK;

input HRESET;

input HREADYIN;

input [15:0] HADDR;

input [31:0] HWDATA;

input HWRITE;

input [1:0] HTRANS;

input HSEL;

input [4:0]rqst_idf;

input [4:0]rqst_idi;

output [31:0] HRDATA;

output HREADYOUT;

output [1:0] HRESP;

// Registered outputs

reg [31:0] HRDATA;

//Internal wires used

wire Valid;



wire [31:0]HRDATA_wire;

wire [31:0] ADDR;

//Internal registers used

reg [15:0] HaddrReg;

reg HwriteReg;

reg [31:0] WdataReg;

reg [31:0] RDATAReg;

//used in State machine for AHB Slave interface

reg [1:0]State;

parameter IDLE=2'b00;

parameter WR_DATA=2'b01;

parameter RD_DATA=2'b10;

// Definition of Configuration memory space

parameter ADDR_SIZE = 64, WORD_SIZE = 32;

reg [WORD_SIZE-1:0] configure_space [0:ADDR_SIZE-1];

integer Addr_integer;

integer i;



// HTRANS transfer type signal encoding:

`define TRN_IDLE 2'b00

`define TRN_BUSY 2'b01

`define TRN_NONSEQ 2'b10

`define TRN_SEQ 2'b11

// HRESP transfer response signal encoding:

`define RSP_OKAY 2'b00

`define RSP_ERROR 2'b01

`define RSP_RETRY 2'b10

`define RSP_SPLIT 2'b11

//------------------------------------------------------------------------------

// Valid AHB transfers only take place when a non-sequential or sequential

// transfer is shown on HTRANS - an idle or busy transfer should be ignored.

assign Valid = ((HSEL == 1'b1 && HREADYIN == 1'b1 &&

(HTRANS == `TRN_NONSEQ || HTRANS == `TRN_SEQ)) ? 1'b1 : 1'b0);

always @ (negedge HRESET or posedge HCLK)



begin

if ((!HRESET))

begin

HaddrReg <= {16{1'b0}};

HwriteReg <= 1'b0;

State <= IDLE;

end

else

// AHB State logic

begin

case(State)

IDLE:

begin

if (Valid)

begin

HaddrReg <= HADDR;

HwriteReg <= HWRITE;

end

if(Valid == 1 && HWRITE == 0)



begin

HRDATA <= RDATAReg;

State <= RD_DATA;

end

else if(Valid ==1 && HWRITE == 1)

State <= WR_DATA;

end

WR_DATA:

begin

if(Valid == 1)

begin

WdataReg <= HWDATA;

HaddrReg <= HADDR;


end


State <= RD_DATA;

else if(Valid ==1 && HWRITE == 1)

State <= WR_DATA;

else if(Valid == 0)



State <= IDLE;

end

RD_DATA:

begin

if(Valid == 1)

begin

HRDATA <= RDATAReg;

HaddrReg <= HADDR;


end


State <= RD_DATA;

else if(Valid ==1 && HWRITE == 1

State <= WR_DATA;

else if(Valid == 0)

State <= IDLE;

end

endcase

end

end



// Hreadyout assignment

assign HREADYOUT = 1;

// Hresponse assignment

assign HRESP = `RSP_OKAY;

//READ DATA assignment

assign HRDATA_wire = configure_space[Addr_integer];

//----------------------------------------------------------------------

//CONFIGURATION MEMORY SPACE MAPPING

//----------------------------------------------------------------------

// ADDR assignment from HADDR

assign ADDR = HaddrReg;

// Chip select signal generation

assign CS =(~^ADDR[15:8]);

// Write enable signal generation

assign WRen = HwriteReg & CS;

always@ (posedge HCLK or negedge HRESET)

begin

if (~HRESET)

begin



for (i=0; i<=63; i =i+1)

configure_space[i]<=32'd0;

end

else

begin

configure_space[37] <= configure_space[rqst_idf];

configure_space[38] <= configure_space[rqst_idi];

Addr_integer = ADDR[7:2];//Conversion of Actual 6-bit adress for the register to integer

if(WRen == 1)

begin

if(Addr_integer == 37 && Addr_integer == 38)

begin

end

else

configure_space[Addr_integer] <= WdataReg;

end

else

RDATAReg <=HRDATA_wire;

end

end

endmodule

6.3 RTL Schematic of Interrupt Controller



6.4 RTL Schematic of AHB Slave Interface



CHAPTER 7



SIMULATION RESULTS

7.1 Interrupt Controller

Figure 7.1:Interrupt handling from IRQ peripheral

Figure 7.1 shows how vectored Interrupt Controller handles an irq request. requestidi,

acki and nirq are are asserted as per the highest priority interrupt request. requestidi is the

unique id peripheral whose request going to get the service from CPU. nirq is active low

signal which interrupt’s the CPU.



Figure 7.2:Interrupt handling from FIQ peripheral

Figure 7.2 shows how vectored Interrupt Controller handles an fiq request. requestifi,

ackf and nfiq are asserted as per the highest priority interrupt request. requestidf is the

unique id peripheral whose request going get the service from CPU. nfiq is active low signal

which interrupt’s the CPU.



Figure 7.3:Interrupt handling from IRQ and FIQ peripheral

Figure 7.3 shows how vectored Interrupt Controller handles an irq request and fiq .

requestidi, acki, nirq, requestidf, ackf and nfiq are got asserted as per the highest priority

interrupt request. requestidi and requestidf is the unique id peripheral whose request going

get the service from CPU. nirq and nfiq is active low signal which interrupt’s the CPU.



7.2 AHB Slave

Figure 7.4:AHB Data Read Operation

Figure 7.4 shows how AHB signals are asserted to perform Data read through the

AHB from Vectored Interrupt Controller. In order to read the Data Hwrite must be low. Data

read from the address which is specified on the Haddr bus through HRdata bus.



Figure 7.5:AHB Data Write Operation

Figure 7.5 shows how AHB signals got asserted to perform Data write through the

AHB to Vectored Interrupt Controller. In order to write the Data Hwrite must be high. Data

write to the address which is specified on the Haddr bus through HWdata bus.



Figure 7.6: AHB Data Read Operation

Figure 7.6 shows how AHB signals got asserted to perform Data read through the

AHB from Vectored Interrupt Controller. In order to read the Data Hwrite must be low. Data

read from the address which is specified on the Haddr bus through HRdata bus.



CHAPTER 8

CONCLUSION

We started our design with the objective of designing “A Vectored interrupt controller as

AMBA AHB slave”. Support for 32 interrupt source, AHB mapped for fastest interrupt

response, Level Sensitive interrupt input, software interrupt generation, fixed hardware

priority, interrupt enabling and fixed FIQ and IRQ generation.

Now we finished our design which meets our objective. Vectored interrupt controller what

we designed will send back acknowledgement to the peripherals to guarantees the acceptance

of interrupt request. Each peripheral which are interfaced with this vectored interrupt

controller is provided with a unique peripheral ID (Rqst_id).

Vectored interrupt can serve two interrupt request at a time, one FIQ request and one IRQ

request and it will give two separate acknowledgements for both FIQ and IRQ requests. Due

to the parallel processing of FIQ and IRQ requests the VIC has a low latency has a faster

execution speed.

We defined a memory space for registers and to store interrupt service routines, who’s

offset address start from 00H to 40H. Memory space with the address 88h, 8Ch, 90h are read

only registers stores the status of interrupt controller, vectored address of FIQ and IRQ

request respectively.



8.1 FUTURE ENHANCEMENT

Daisy chain supporting:

The daisy-chained VIC are responsible for blocking lower-level or equal-level

interrupts. It operates in two modes VIC0 and VIC1. To enable higher priority

interrupts from the daisy-chained VIC1 to be acknowledged while servicing a

lower level interrupt. When implementing the daisy chain, we have to ensure the

total propagation delay for VICIRQACK across the all the VICs is within one

clock cycle

Nested interrupt handling

To prevent the loss and delay of high-priority interrupts, the system uses nested

interrupts. Nested interrupts allow interrupt requests (IRQs) of a higher priority to

preempt IRQs of a lower priority. Nested interrupts are allowed in conjunction

with the Real-Time Priority System. ISRs of a higher priority might preempt ISRs

of a lower priority.

Multi domains interrupt handling.

Programmable FIQ and IRQ generation.


http://msdn.microsoft.com/en-us/library/aa450616.aspx


BIBILOGRAPHY

1. ARM Corporation, Prime cell Vectored interrupt controller PL192, reference

manual,2002

2. ARM Corporation ,AMBA specification 3.0, reference manual,2006

3. J. Basker,A Verilog HDL Primer 3rd Edition, 2003.

4. J. Basker,A Verilog HDL Synthesis 1st Edition,1998 .

5. http://infocenter.arm.com

6. http://www.arm.com


http://www.arm.com/

http://infocenter.arm.com/


APPENDIX


Vic Report

Documents

Transcript of Vic Report