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----------------------------------------------------------- Author : http://www.teahlab.com/---- Circuit: AND Gate---- Note : This VHDL program is a structural descriptio-- o! the iteracti"e AND Gate o teahlab.com.---- #! $ou are ew to VHDL% the otice how the-- program is desiged: &' !irst we declare the-- (NT#T)% which is where we de!ie the iputs-- ad the outputs o! the circuit. *' +ecod-- we preset the A,CH#T(CT,(% which is where-- we describe the beha"ior ad !uctio o!-- the circuit.---------------------------------------------------------

--import stdlogic !rom the #((( librar$librar$ ieeeuse ieee.stdlogic&&01.all

--(NT#T) D(CLA,AT#2N: ame% iputs% outputsetit$ adGate is port3 A% 4 : i stdlogic 5 : out stdlogic6ed adGate

--5NCT#2NAL D(+C,#7T#2N: how the AND Gate wor8sarchitecture !uc o! adGate isbegi 5 9 A ad 4ed !uc------------------------------------------------------(ND------------------------------------------------------(ND

-------------------------------------------------------------- Author : http://www.teahlab.com/---- 7rogram : AND Gate Testbech---- Note : A testbech is a program that de!ies a set-- o! iput sigals to "erit$ the operatio o!-- a circuit: i this case% the AND Gate.---- &' The testbech ta8es o iputs ad returs-- o outputs. As such the (NT#T) declaratio-- is empt$.---- *' The circuit uder "eri!icatio% here the-- AND Gate% is imported ito the testbech-- A,CH#T(CT,( as a compoet.------------------------------------------------------------

--import stdlogic !rom the #((( librar$

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librar$ ieeeuse ieee.stdlogic&&01.all

--(NT#T) D(CLA,AT#2N: o iputs% o outputsetit$ adGatetb ised adGatetb

-- Describe how to test the AND Gatearchitecture tb o! adGatetb is --pass adGate etit$ to the testbech as compoet compoet adGate is port3 A% 4 : i stdlogic 5 : out stdlogic6 ed compoet

sigal iA% i4% out5 : stdlogicbegi

--map the testbech sigals to the ports o! the adGate mappig: adGate port map3iA% i4% out56

process --"ariable to trac8 errors "ariable errCt : iteger : ; begi --T(+T & iA 9 (rrorB> se"erit$ error ed i!

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ed processed tb--------------------------------------------co!iguratio c!gtb o! adGatetb is !or tb ed !ored c!gtb---------------------------------------------------------(ND---------------------------------------------------------(ND

-------------------------------------------------------------- Author : http://www.teahlab.com/---- Circuit : 2, Gate---- Note : This VHDL program is a structural descriptio-- o! the iteracti"e 2, Gate o teahlab.com.---- #! $ou are ew to VHDL% the otice how the-- program is desiged: &' !irst we declare the-- (NT#T)% which is where we de!ie the iputs-- ad the outputs o! the circuit. *' +ecod-- we preset the A,CH#T(CT,(% which is where-- we describe the beha"ior ad !uctio o!-- the circuit.------------------------------------------------------------


--(NT#T) D(CLA,AT#2N: ame% iputs% outputsetit$ orGate is port3 A% 4 : i stdlogic 5 : out stdlogic6ed orGate

--5NCT#2NAL D(+C,#7T#2N: how the 2, Gate wor8sarchitecture !uc o! orGate isbegi 5 9 A or 4ed !uc---------------------------------------------------------(ND---------------------------------------------------------(ND

-------------------------------------------------------------- Author : http://www.teahlab.com/---- 7rogram : 2, Gate Testbech---- Note : A testbech is a program that de!ies a set

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-- o! iput sigals to "erit$ the operatio o!-- a circuit: i this case% the 2, Gate.---- &' The testbech ta8es o iputs ad returs-- o outputs. As such the (NT#T) declaratio-- is empt$.---- *' The circuit uder "eri!icatio% here the-- 2, Gate% is imported ito the testbech-- A,CH#T(CT,( as a compoet.------------------------------------------------------------


--(NT#T) D(CLA,AT#2N: o iputs% o outputsetit$ orGatetb ised orGatetb

-- Describe how to test the 2, Gatearchitecture tb o! orGatetb is --pass orGate etit$ to the testbech as compoet compoet orGate is port3 A% 4 : i stdlogic 5 : out stdlogic6 ed compoet

sigal iA% i4% out5 : stdlogicbegi --map the testbech sigals to the ports o! the orGate mappig: orGate port map3iA% i4% out56

process --"ariable to trac8 errors "ariable errCt : iteger : ; begi --T(+T & iA 9

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i4 9 (rrorB> se"erit$ error ed i!

ed processed tb--------------------------------------------co!iguratio c!gtb o! orGatetb is !or tb ed !or

ed c!gtb---------------------------------------------------------(ND---------------------------------------------------------(ND

-- Author : http://www.teahlab.com/---- Circuit : NAND Gate---- Note : This VHDL program is a structural descriptio-- o! the iteracti"e NAND Gate o teahlab.com.--

-- #! $ou are ew to VHDL% the otice how the-- program is desiged: &' !irst we declare the-- (NT#T)% which is where we de!ie the iputs-- ad the outputs o! the circuit. *' +ecod-- we preset the A,CH#T(CT,(% which is where-- we describe the beha"ior ad !uctio o!-- the circuit.------------------------------------------------------------


--(NT#T) D(CLA,AT#2N: ame% iputs% outputsetit$ adGate is port3 A% 4 : i stdlogic 5 : out stdlogic6ed adGate

--5NCT#2NAL D(+C,#7T#2N: how the NAND Gate wor8sarchitecture !uc o! adGate isbegi 5 9 A ad 4

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ed !uc---------------------------------------------------------(ND---------------------------------------------------------(ND

-------------------------------------------------------------- Author : http://www.teahlab.com/---- 7rogram : NAND Gate Testbech---- Note : A testbech is a program that de!ies a set-- o! iput sigals to "erit$ the operatio o!-- a circuit: i this case% the NAND Gate.---- &' The testbech ta8es o iputs ad returs-- o outputs. As such the (NT#T) declaratio-- is empt$.---- *' The circuit uder "eri!icatio% here the-- NAND Gate% is imported ito the testbech-- A,CH#T(CT,( as a compoet.------------------------------------------------------------


--(NT#T) D(CLA,AT#2N: o iputs% o outputsetit$ adGatetb ised adGatetb

-- Describe how to test the NAND Gate

architecture tb o! adGatetb is --pass adGate etit$ to the testbech as compoet

compoet adGate is port3 A% 4 : i stdlogic 5 : out stdlogic6 ed compoet

sigal iA% i4% out5 : stdlogicbegi --map the testbech sigals to the ports o! the adGate mappig: adGate port map3iA% i4% out56

process --"ariable to trac8 errors "ariable errCt : iteger : ; begi --T(+T & iA 9

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ed i!

--T(+T * iA 9

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--(NT#T) D(CLA,AT#2N: ame% iputs% outputsetit$ otGate is port3 i7ort : i stdlogic out7ort : out stdlogic6ed otGate

--5NCT#2NAL D(+C,#7T#2N: how the #"erter wor8sarchitecture !uc o! otGate isbegi out7ort 9 ot i7orted !uc------------------------------------------------------(ND------------------------------------------------------(ND

-------------------------------------------------------------- Author : http://www.teahlab.com/---- 7rogram : #"erter Testbech---- Note : A testbech is a program that de!ies a set-- o! iput sigals to "erit$ the operatio o!-- a circuit: i this case% the i"erter.---- &' The testbech ta8es o iputs ad returs-- o outputs. As such the (NT#T) declaratio-- is empt$.--

-- *' The circuit uder "eri!icatio% here the-- i"erter% is imported ito the testbech-- A,CH#T(CT,( as a compoet.------------------------------------------------------------


--(NT#T) D(CLA,AT#2N: o iputs% o outputsetit$ otGatetb ised otGatetb

-- Describe how to test the i"erterarchitecture tb o! otGatetb is --pass otGate etit$ to the testbech as compoet compoet otGate is port3 i7ort : i stdlogic out7ort : out stdlogic6 ed compoet

sigal go#% go2ut : stdlogicbegi

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--map the testbech sigals to the ports o! the otGate mappig: otGate port map3 go#% go2ut6

process --"ariable to trac8 errors "ariable errCt : iteger : ; begi --T(+T & go# 9

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