VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated...

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VHDL

Transcript of VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated...

Page 1: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

VHDL

Page 2: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

What is VHDL?

VHDL: VHSIC Hardware Description LanguageVHSIC: Very High Speed Integrated Circuit

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Page 3: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Entity :- The most basic building block in the design. The uppermost level of the design is the top level entity. Entity is a hardware abstration of the

actual hardware device. The entity declaration specifies the name

of the entity modeled and lists the interfaces.

An entity X, when used in another entity Y, becomes a component for the entity Y.

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Page 4: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Entity communicates with other models in its external environment through port

signals.Entity Declaration

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Page 5: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Entity Declaration For Half Adder

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Page 6: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Entity Entity Declaration:

Indicates what comes in and what goes out.

entity name port names port mode (direction)port type punctuation

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Page 7: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

The port type for this entity have been specified to be of type BIT, which means that the ports can take the values ‘0’ or ‘1’.

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Page 8: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Entity declaration for the 2-to-4 decoder circuit.

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Page 9: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

BIT_VECTOR is a predefined unconstrained array type of BIT.

entity DECODER2×4 is

Port (A, B, ENABLE: in BIT;

Z:out BIT_VECTOR(0 to 3));

end DECODER2×4;

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Page 10: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

The range ”0 to 3” for port Z specifies the array size.

An unconstrained array type is a type in which the size of the array

is not specified.

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Page 11: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Architecture – All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity.

. Each VHDL design unit comprises an "entity" declaration and one or more "architectures".

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Architecture Body

The internal details of an entity are specified by an architectural body using any of the following modeling style:

Page 13: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

4) As any combination of previous three.

3) As a set of sequential assignments (to represent behavior)

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1) As a set of interconnected components (to represent structure)

2) As a set of concurrent assignment statements (to represent dataflow)

Page 14: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Dataflow model of HALF_ADDER described usig two concurrent signal assignment statements.

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Architecture of full adder

entity name port names port mode (direction)port type

reserved words

punctuation

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Page 16: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

1) Structural style of modeling.

2) Dataflow style of modeling

3) Behavioral style of modeling

Architecture Modeling Style

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Page 17: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

In the structural style of modeling, an entity is described as a set of interconnected

components

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Page 18: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

In the structural style of modeling, the architecture body

is composed of two parts:1) The declarative part before

the keyword begin.2) The statement part after the

keyword begin.

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Page 19: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

The declared components are instantiated in the statement part of the architecture body

using component instantiation statements.

X1 and A1 are the component labels for these component

instantiation

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Page 20: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

The first component instantiation statement labeled X1, shows that signals A and B (the input ports of the HALF_ADDER) are connected

to the X and Y input ports of a XOR2 component, while output port Z of this component is connected to

output port SUM

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Page 21: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Separate entity models should be written for the components XOR2

and AND2.

The signals in the port map of a component instantiation and the port signals in the component declaration

are associated by position called positional association.

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Page 22: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

A component instantiation statement is a concurrent

statement .

The order of these statements is not important.

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Page 23: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

The structural style of modeling describes only an

interconnection of components (viewed as black boxes),

without implying any behavior of the components.

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Architecture of the DECODER2×4 using structural representation

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Page 25: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

BIT_VECTOR is a predefined unconstrained array type of BIT.

entity DECODER2×4 is

Port (A, B, ENABLE: in BIT;

Z:out BIT_VECTOR(0 to 3));

end DECODER2×4;

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Page 27: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

The architecture body contains a signal declaration that declares two signals,

ABAR and BBAR, of type BIT.These signals, which represent wires,

are used to connect components.The scope of these signals is restricted to the architecture body; and therefore these signals are not visible outside

the architecture body.

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Architecture

Defines one particular implementation of a design unit 

architecture arch_name of entity_name is        ...  declarations ...    // can be data types, constants, signals, etc begin        ...  concurrent statements …    end

Concurrent statements describe a design unit at one or more levels of modeling abstraction:

Behavioral Model: No structure implied. Usually written in sequential, procedural style.

Dataflow Model: All datapaths shown, plus all control signals. Structural Model: Interconnection of components.

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Page 30: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Let’s Start Simple

Support different description levels Structural (specifying interconnections of the gates), Dataflow (specifying logic equations), and Behavioral (specifying behavior)

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Page 31: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Arithmetic and Logical Expressions

Expressions in VHDL are similar to those of most high-level languages. Data elements must be of the type, or subtypes of the same base type. Operators include the following:

Logical: and, or, nand, nor, xor, not (for boolean or bit ops) Relational: =, /=, <, <=, >, >= Arithmetic: +, -, *, /, mod, rem, **, abs

(a mod b takes sign of b, a rem b takes sign of a) Concatenate: &

(ex. a & b makes one array) Examples    a <= b nand c;    d := g1 * g2 / 3;    Bus_16 <= Bus1_8 & Bus2_8;

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Page 32: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

VHDL Data Types

Each VHDL object must be classified as being of a specific data type.

Predefined Scalar Data Types (single objects) bit values: '0', '1' , boolean values: TRUE, FALSE integer values: -(231) to +(231 - 1) natural values: 0 to integer'high (subtype of integer) character values: ASCII characters (eg. 'A') time values include units (eg. 10ns, 20us)

Predefined VHDL Aggregate Data Types bit_vector array (natural range <>) of bit Example :signal dbus: bit_vector(15 downto 0);   Accessing element: dbus(n) example: dbus(0) string array (natural range <>) of char

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Page 33: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

VHDL Objects: Variables

A variable is declared within a block, process, procedure, or function, and is updated immediately when an assignment statement is executed.

Can be of any scalar or aggregate data type, Is utilized primarily in behavioral descriptions. Declaration syntax: variable symbol: type [:= initial_value]; Example:

process        variable count: integer  := 0;

       variable rega: bit_vector(7 downto 0);    begin       

...        count := 7;      -- assign values to variables       

rega  := x"01";        end;

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Page 34: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

VHDL Objects: Signals

A signal is an object with a history of values (related to "event" times, i.e. times at which the signal value changes).

Signals are declared via signal declaration statements or entity port definitions, and may be of any data type.

Declaration syntax : signal sig_name: data_type [:=initial_value];

Example:   signal clock: bit; Signal assignment statement: A <= B after 10ns;

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Page 35: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Modeling Flip-Flops Using VHDL Processes

Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time

General form of process

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Page 36: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

D Flip-flop Model

Bit values are enclosed in single quotes

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Page 37: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

JK Flip-Flop Model

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Page 38: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

JK Flip-Flop Model

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Page 39: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Backup

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Page 40: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Object Attributes

An object attribute returns information about a signal or data type. Signal Condition Attributes (for a signal S)

S'DELAYED(T) - value of S delayed by T time units S'STABLE(T) - true if no event on S over last T time units S'QUIET(T) - true if S quiet for T time units S'LAST_VALUE - value of S prior to latest change S'LAST_EVENT - time at which S last changed S'LAST_ACTIVE - time at which S last active S'EVENT - true if an event has occurred on S in current cycle S'ACTIVE - true if signal S is active in the current cycle S'TRANSACTION - bit value which toggles each time signal S changes

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Page 41: VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

Constants

• A constant associates a value to a symbol of a given data type

• Declaration syntax:

constant symbol: type := value;• Example: 

constant  zero4: bit_vector(0 to 3) := ('0','0','0','0');

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