VHDL Symbolic simulator in OCaml

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VHDL Symbolic simulator in OCaml Florent Ouchet florent.ouchet @ imag.fr TIMA Labs – GINP – UJF – CNRS – VDS group OCaml Meeting 2009 Grenoble – France 04/02/2009

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VHDL Symbolic simulator in OCaml. Florent Ouchet [email protected] TIMA Labs – GINP – UJF – CNRS – VDS group. OCaml Meeting 2009 Grenoble – France 04/02/2009. Outline. VSYML – Vhdl Symbolic Simulator in ocaML: Symbolic simulation goals Why OCaml? - PowerPoint PPT Presentation

Transcript of VHDL Symbolic simulator in OCaml

Page 1: VHDL Symbolic simulator in OCaml

VHDL Symbolic simulator in OCaml

Florent Ouchet [email protected] Labs – GINP – UJF – CNRS – VDS group

OCaml Meeting 2009Grenoble – France

04/02/2009

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Florent Ouchet – OCaml meeting 2009 – Grenoble – France2

Outline

VSYML – Vhdl Symbolic Simulator in ocaML:

• Symbolic simulation goals• Why OCaml?• Application structure and limitations of OCaml in

this context• Perspectives• Conclusion

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Symbolic simulation goals

Model is needed for:

– Model checking: equivalence of IC implementation and specification;

– Other formal methods based on the model: (ANR project FME3) analysis of error consequences using formal methods.

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Symbolic simulation goalsIntegrated circuit synthesis flow:

Modeling level

RegisterTransfert Level

Gate Level

Layout

Chips

FSM, complex types

Explicit time,behavioral

Boolean type

Drawing of transistorsand wires

Manual refinements

Automatic synthesis

Placing and routing

Manufacturing

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Symbolic simulation goalsExisting symbolic simulators:

Modeling level

Register TransfertLevel

Gate Level

Layout

Chips

FSM, complex types

Explicit time,behavioral

Boolean type

Drawing of transistorsand wires

VOSS/Forte(Intel CAD Labs)

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Symbolic simulation goalsExisting symbolic simulators:

Modeling level

Register TransfertLevel

Gate Level

Layout

Chips

FSM, complex types

Explicit time,behavioral

Boolean type

Drawing of transistorsand wires

VSYML

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Symbolic simulation goals

Integrated CircuitDescription

Design Under Test(DUT)

Xt=0 ns

Xt=1 ns

…Yt=0 ns

Yt=1 ns

Xt=0 + Yt=1 ?

Description written in VHDL (IEEE Std 1076.1TM – 2007)Symbolic values depend on the time.

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Why OCaml?

Expression patterns:– X@1ns– 1– unary_operator X (not – abs)– X assoc_operator Y (+ * and or xor xnor)– X binary_operator Y (nand nor ^ = /= < > <= >=)– X other_operator Y (mod rem / -)– … (total of 28 patterns)

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Why OCaml?

type formula = | FormulaSymbol of symbol | FormulaImmediateInt of big_int | FormulaUnaryOperator of (unary_operator*formula) | FormulaAssociativeOperator of (assoc_operator*formula list) | FormulaBinaryOperator of (binary_operator*formula*formula) | FormulaOtherOperator of (other_operator*formula*formula list) | …

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Why OCaml?

• Known expression patterns are rewritten (numeric evaluation);

• As in the standard, the simulation algorithm is intrinsically free of side effects.

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Why OCaml?

ProcessA

ProcessB

ProcessC

The next value of each signal is computed from current values.

DUT

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Why OCaml?

ProcessA

ProcessB

ProcessC

The processes are executed until the design is stabilized.

DUT

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Why OCaml?

ProcessA

ProcessB

ProcessC

The processes are executed until the design is stabilized.

DUT

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Why OCaml?

ProcessA

ProcessB

ProcessC

The processes are executed until the design is stabilized.

DUT

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Why OCaml?

ProcessA

ProcessB

ProcessC

The processes are executed until the design is stabilized.

DUT

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Why OCaml?

ProcessA

ProcessB

ProcessC

The processes are executed until the design is stabilized.

DUT

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Why OCaml?

ProcessA

ProcessB

ProcessC

The processes are executed until the design is stabilized.

DUT

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Why OCaml?

• Strong type checking (compared to C, Pascal…): confidence in computations;

• Lexer/parser generator;

• « Free » software, its ancestor was written in Mathematica;

• Lightweight and easy to redist (Java, C#, F#).

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Application structure

VSYMLVHDL

source filesDesign model

parameters

Standalone and automated application.

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Application structure

• Some facts:– Over 26500 lines of code– 24 dedicated modules (types, basics, lexer,

parser, resources, evaluators, converters, volume extrusion, top-level…)

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Application structure

• Straightforward conversion from BNF rules (language spec)

• No syntax for optional tokens

• Debugging conflicts is a nightmare

VHDL source files(thousands lines)

Lexer(59 states, 1058 transitions)

Parser(695 grammar rules,1318 states)

Abstractsyntax tree

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Application structure

• Some basic functions are missing in OCaml standard libraries

• Issue 4662 closed as « won’t fix »

Abstractsyntax tree

Design elaboration

Simulationstructure tree

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Application structure

• A function to map a list of functions to the same parameter:

(‘a -> ‘b) list -> ‘a -> ‘b list

• A function to remove the n first list elements:

‘a list -> int -> ‘a list

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Application structure

• Unbounded integers in VHDL (32 bits at least -"Time" requires 64 bits)

• Simulation of design on n bits

Big_int

Abstractsyntax tree

Design elaboration

Simulationstructure tree

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Application structure

• Big_int is an abstract type

• (=) (<) (>) on Big_int raise runtime exceptions

• Associative list functions based on (=)

Abstractsyntax tree

Design elaboration

Simulationstructure tree

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Application structure

• Many executions of the functional structure with different evaluation contexts

Simulationstructure tree

Simulation algorithm

Simulation results

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Application structure

• Signature of process simulation function:process -> structure_context ->

evaluation_context -> changed_object list

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• Prototype of process simulation function:process -> structure_context ->

evaluation_context -> changed_object list

• Functors for efficiency (+50%)

Application structure

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Application structure

• Prototype of process simulation function:process -> structure_context ->

evaluation_context -> changed_signal list

• evaluation_context = {

simulation_time: Big_int;

currentvalues: (signal*formula) list; … }

• Test with array, hashtbl and references

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Application structure

• Some timings: FIR filter simulation, 1000 clock cycles.

Parsing + elab.

Simulation Output Process

memory

GC bytes

assoc 40 ms 9.60 s 1.20 s 2.4 Mo 1189 Mo

array 40 ms 1.82 s 1.20 s 2.4 Mo 910 Mo

hashtbl 40 ms 2.00 s 1.17 s 2.3 Mo 921 Mo

ref 40 ms 1.76 s 1.25 s 2.3 Mo 899 Mo

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Application structure

ProcessA

ProcessB

ProcessC

DUT

Load averaging for a multi-thread simulation.Communication efficiency for a distributed simulation.

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Perspectives

• Spread the simulation over cores and computers: an integrated circuit is a fixed finite set of concurrent process

concurrent simulation but:– lots of rendez-vous and communications– Irregular load

• Mathematics: loop invariants…

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Conclusion

• Development for project FME3 is now finished.

• Research prototype for parallel computations?

• Release to the public? CeCill Licence?

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Questions?

Thanks for your attention