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Functions Functions A function accepts a number of arguments and returns a result. A function accepts a number of arguments and returns a result. Each of the arguments and the result in a function definition or Each of the arguments and the result in a function definition or function call have a predetermined type.function call have a predetermined type. When a function is called, the actual parameters in the function call When a function is called, the actual parameters in the function call are substituted for the formal parametersare substituted for the formal parametersWhen a function is called from within an architecture, a value of When a function is called from within an architecture, a value of the type return-type is returned in place of the function callthe type return-type is returned in place of the function callA function may define its own local types, constants, variables and A function may define its own local types, constants, variables and nested functions and proceduresnested functions and proceduresThe keywords The keywords beginbegin and and end end enclose a series of “sequential enclose a series of “sequential statements” that are executed when the function is calledstatements” that are executed when the function is called

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A simple example A simple example

entity Inhibit is -- a.k.a. “but-not” as in “X but not Y”

port (X,Y: in BIT;

Z: out BIT);

end Inhibit; -- end of entity declaration

architecture Inhibit_arch of Inhibit is

begin

Z <= ‘1’ when X=‘1’ and Y=‘0’ else ‘0’;

end Inhibit_arch -- end of architecture declaration

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But-not gate using a functionBut-not gate using a function

architecture Inhibit_archf of Inhibit is

function ButNot (A,B: bit) return bit is

begin

if B = ‘0’ then return A;

else return ‘0’;

end if;

end ButNot;

begin

Z <= ButNot(X,Y);

end Inhibit_archf

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LibrariesLibrariesAA VHDL VHDL library is a place where the compiler stores information library is a place where the compiler stores information about a particular design project, including intermediate files that are about a particular design project, including intermediate files that are used in the analysis, simulation and synthesis of the design. used in the analysis, simulation and synthesis of the design. Library location is implementation-dependentLibrary location is implementation-dependent For a given VHDL design, the compiler automatically creates and For a given VHDL design, the compiler automatically creates and uses a uses a library named “work”.library named “work”.When compiler analyzes each file in the design, it puts the results When compiler analyzes each file in the design, it puts the results there.there.A complete VHDL design usually has multiple files, each containing A complete VHDL design usually has multiple files, each containing different design units including entities and architectures.different design units including entities and architectures.Not all the information needed in a design may be in the “work” Not all the information needed in a design may be in the “work” library.library.

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LibrariesLibrariesA designer may rely on common definitions or functional modules A designer may rely on common definitions or functional modules across a family of different projects.across a family of different projects. Even small projects may use a standard library such as the one Even small projects may use a standard library such as the one containing IEEE standard definitionscontaining IEEE standard definitionsThe designer can specify the name of such a library using a The designer can specify the name of such a library using a librarylibrary clause at the beginning of the design file. clause at the beginning of the design file.For example one can specify the IEEE library asFor example one can specify the IEEE library aslibrary IEEE;library IEEE; Specifying a library name in a design gives it access to any Specifying a library name in a design gives it access to any previously analyzed entities and architectures stored in the library, previously analyzed entities and architectures stored in the library, but does not give access to type definitions and the like. This is but does not give access to type definitions and the like. This is the function of “packages” and “use clauses”the function of “packages” and “use clauses”

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Library statement in VHDLLibrary statement in VHDL

librarylibrary ieee; ieee;

-- needed if you want to use the ieee library-- needed if you want to use the ieee library

librarylibrary unisim; unisim;

-- will see this in Xilinx-generated files-- will see this in Xilinx-generated files

librarylibrary work; work;

-- -- implicitlyimplicitly included in every VHDL file included in every VHDL file

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What’s in a package?What’s in a package?

A package is a file containing definitions of A package is a file containing definitions of “objects” that can be used in other programs“objects” that can be used in other programs

Is an ADA conceptIs an ADA conceptLike the Like the entity-architectureentity-architecture pair, the pair, the packagepackage is another is another precursor to the OOP idea!precursor to the OOP idea!““object” here means signals, types, constants, object” here means signals, types, constants, functions, procedures, components declarations, etc. functions, procedures, components declarations, etc. NOT objects as in OOP.NOT objects as in OOP.

The kind of objects are The kind of objects are signal, type, signal, type, constant, function, procedure,constant, function, procedure, and and component component declarationsdeclarations

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PackagesPackagesSignals Signals that are defined in a package are “global” signals, that are defined in a package are “global” signals, available to any VHDL entity that uses the packageavailable to any VHDL entity that uses the packageTypesTypes and and constantsconstants defined in a package are known in any defined in a package are known in any file that uses the package file that uses the package Likewise Likewise functionsfunctions and and proceduresprocedures defined in a package can defined in a package can be called in files that use the package and be called in files that use the package and componentscomponents can be can be “instantiated” in architectures that use the package.“instantiated” in architectures that use the package.To use a package you say “use” … for example:To use a package you say “use” … for example:useuse ieee.std_logic_1164.all; ieee.std_logic_1164.all; -- use all -- use all definitions in pkgdefinitions in pkguseuse ieee.std_logic_1164.std_ulogic ieee.std_logic_1164.std_ulogic -- use -- use just def std_ulogic typejust def std_ulogic type

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PackagesPackagesA design can use a package by including a A design can use a package by including a useuse clause at the clause at the beginning of the design filebeginning of the design file To use all the definitions in the IEEE standard 1164 package one To use all the definitions in the IEEE standard 1164 package one would writewould writeuseuse ieee.std_logic_1164.all; ieee.std_logic_1164.all;Here “Here “ieeeieee” is the name of the library which has previously been ” is the name of the library which has previously been given in the given in the librarylibrary clause clauseWithin the library , the file named “Within the library , the file named “std_logic_1164std_logic_1164”” contains contains the desired definitions and the suffix “the desired definitions and the suffix “allall” tells the compiler to use ” tells the compiler to use all of the definitions in this file all of the definitions in this file Package is not limited to standard bodies, anyone can write a Package is not limited to standard bodies, anyone can write a package using the proper syntaxpackage using the proper syntax

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VHDL Design StylesVHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral

• Registers• State machines• Test benches

Sequential statements

Subset most suitable for synthesis

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VHDL ExampleVHDL Example

Entity declaration for the 2 to 1 MUXEntity declaration for the 2 to 1 MUX

ENTITY mux2_1 IS PORT (in0, in1, sel: IN STD_LOGIC; yout: OUT STD_LOGIC);END mux2_1;

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VHDL ExampleVHDL Example

Logic circuit for a 2-1 MUX deviceLogic circuit for a 2-1 MUX device

Helpful for understanding architectureHelpful for understanding architecture

in0

in1sel

yout

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Behavioral architecture for the 2 to 1 MUXBehavioral architecture for the 2 to 1 MUX

ARCHITECTURE a1 OF mux2_1 IS P1: PROCESS (sel, in0, in1) BEGIN IF (sel = ‘0’) THEN yout <= in0; ELSE yout <= in1; END IF; END P1;END a1;

in0

in1sel

yout

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Structural architecture for the 2 to 1 MUXStructural architecture for the 2 to 1 MUX

ARCHITECTURE a2 OF mux2_1 IS SIGNAL sel_not, in0_and, in1_and: STD_LOGIC; COMPONENT OR_GATE PORT(x,y: IN STD_LOGIC; z: OUT STD_LOGIC); COMPONENT AND_GATE PORT (x,y: IN STD_LOGIC; z: OUT STD_LOGIC); COMPONENT INV_GATE PORT (x: IN STD_LOGIC; z: OUT STD_LOGIC);BEGIN U1: AND_GATE PORT MAP (in0, sel_not, in0_and); U2: AND_GATE PORT MAP (in1, sel, in1_and); U3: INV_GATE PORT MAP (sel, sel_not); U4: OR_GATE PORT MAP (in0_and, in1_and, yout);END a2;

in0

in1sel

youtIn0_and

In1_and

sel_not

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Dataflow architecture for the 2 to 1 MUXDataflow architecture for the 2 to 1 MUX

ARCHITECTURE a3 OF mux2_1 ISBEGIN yout <= ((in0 AND NOT(sel)) OR (in1 AND sel));END a3;

In0

In1sel

yout

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Half Adder CircuitHalf Adder Circuit

Looking at the truth table for a half adder, it is easy Looking at the truth table for a half adder, it is easy to visualize the circuitto visualize the circuit

BA

S

C

A B C S

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Full Adder CircuitFull Adder Circuit

The circuit at right shows a The circuit at right shows a full adder constructed from full adder constructed from two half adders.two half adders.

XOR generates the sum XOR generates the sum outputoutput

AND generates the carry AND generates the carry outputoutput

half adder

half adder

BACBABAC BACBACBA

BACBCA

CBAS

-- Dataflow model for a full adder circuit-- Library Statement declares the ieee synthesis library LIBRARY ieee;         USE ieee.std_logic_1164.ALL;

-- Entity declaration ENTITY fulladder IS PORT(Ain, Bin, Cin:  IN STD_LOGIC; Cout, Sout:  OUT STD_LOGIC);END fulladder;

-- Architecture defines the function -- In this case the function is defined using Boolean equationsARCHITECTURE dataflow OF fulladder ISBEGIN -- Concurrent Signal Assignment Statements Sout <= Ain XOR Bin XOR Cin; Cout <= (Ain AND Bin) OR (Ain AND Cin) OR (Bin AND Cin);END dataflow;

-- Structural architecture is defined by a circuit ARCHITECTURE structural OF fulladder IS COMPONENT AND2  PORT( A, B: IN STD_LOGIC; F: OUT STD_LOGIC);END COMPONENT; COMPONENT OR3  PORT( A, B, C: IN STD_LOGIC; F: OUT STD_LOGIC);END COMPONENT; COMPONENT XOR2  PORT( A, B: IN STD_LOGIC; F: OUT STD_LOGIC);END COMPONENT; SIGNAL AXB, AB, BC, AC: STD_LOGIC; BEGIN F1: XOR2 port map (Ain, Bin, AXB); --Port Map Statements F2: XOR2 port map (AXB, Cin, Sout);      F3: AND2 port map (Ain, Bin, AB);    F4: AND2 port map (Bin, Cin, BC); F5: AND2 port map (Ain, Cin, AC); F6: OR3 port map (AB, BC, AC, Cout);END structural;

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Binary Addition: 4-Bit NumbersBinary Addition: 4-Bit Numbers

The following example illustrates the addition of two The following example illustrates the addition of two 4-bit numbers A(A4-bit numbers A(A33AA22AA11AA00) and B(B) and B(B33BB22BB11BB00): ):

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Binary Addition: 4-Bit NumbersBinary Addition: 4-Bit Numbers

The addition can be split-up in bit The addition can be split-up in bit slices slices

Each slice performs the addition of Each slice performs the addition of the bits Athe bits Aii, B, Bii and the Carry-in bit C and the Carry-in bit Cii

CCii <= carry-out bit of the previous slice <= carry-out bit of the previous slice

Each slice is simply a full adder Each slice is simply a full adder

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4-Bit Binary Adder4-Bit Binary Adder

Circuit for a 4-bit parallel binary adder constructed Circuit for a 4-bit parallel binary adder constructed from full adder building blocksfrom full adder building blocks

LIBRARY ieee;USE ieee.std_logic_1164.ALL; -- VHDL model of a 4-bit adder using four full addersENTITY four_bit_adder_st ISPORT (A, B : IN STD_LOGIC_VECTOR(3 downto 0); SUM : OUT STD_LOGIC_VECTOR(3 downto 0); CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC);END four_bit_adder_st;

Cin

Cout

Internal Signals

-- The architecture is a structural one. ARCHITECTURE structural OF four_bit_adder_st IS-- First all the components are declared. The full adder-- is declared only once, even though it will be used 4 times.COMPONENT fulladder PORT(Ain, Bin, Cin:  IN STD_LOGIC;         Cout, Sout:  OUT STD_LOGIC);END COMPONENT; -- The full adders are connected by carry signals. These-- must be declared also.        SIGNAL C : STD_LOGIC_VECTOR(1 to 3); -- Port map statements are used to define full adder-- instances and how they are connected.         BEGIN        F1: fulladder port map (A(0),B(0),CIN,C(1),SUM(0)); F2: fulladder port map (A(1),B(1),C(1),C(2),SUM(1)); F3: fulladder port map (A(2),B(2),C(2),C(3),SUM(2)); F4: fulladder port map (A(3),B(3),C(3),COUT,SUM(3));END structural;

-- The architecture in this case is a dataflow oneARCHITECTURE dataflow OF four_bit_add_df IS-- Again there will be internal carry signals that are not -- inputs or outputs. These must be declared as signals.SIGNAL C : STD_LOGIC_VECTOR(1 to 3);-- Concurrent signal assignments can be used to describe-- each of the 4 outputs and the carry signals.BEGIN SUM(0) <= A(0) XOR B(0) XOR Cin; C(1) <= (A(0) AND B(0)) OR (A(0) AND Cin) OR (B(0) AND Cin); SUM(1) <= A(1) XOR B(1) XOR C(1); C(2) <= (A(1) AND B(1)) OR (A(1) AND C(1)) OR (B(1) AND C(1));

SUM(2) <= A(2) XOR B(2) XOR C(2); C(3) <= (A(2) AND B(2)) OR (A(2) AND C(2)) OR (B(2) AND C(2));

SUM(3) <= A(3) XOR B(3) XOR C(3); COUT <= (A(3) AND B(3)) OR (A(3) AND C(3)) OR (B(3) AND C(3));END dataflow;

D latch with an async clear and level sensitivity

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library IEEE;use IEEE.Std_logic_1164.all;entity latch_wc is port (CLK, D, CLR: in Std_logic; Q: out Std_logic);end latch_wc;Architecture design of latch_wc isbegin process (CLK, D, CLR) begin if CLR = '1' then -- CLR active High Q <= '0'; elsif CLK = '1' then -- CLK active High Q <= D; -- note that Q is not assigned

a value for CLK = '0' end if; end process;end design;

CLR

D latch with asynch clear and rising-edge triggered

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library IEEE;use IEEE.Std_logic_1164.all;entity dff_wac is port (CLK, D, CLR: in Std_logic; Q: out Std_logic);end dff_wac;Architecture design of dff_wac isbegin process (CLK, D, CLR) begin if CLR = '1' then -- asynchronous CLR active High Q <= '0'; elsif (CLK'event and CLK='1') then

Q <= D; -- CLK rising edge, CLK'event and CLK = '1' can be replaced by the "function" rising_edge (CLK)

end if; end process;end design;

CLR

T f-f with an asynch clear and rising edge triggered

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library IEEE;use IEEE.Std_logic_1164.all;entity t_ff is port (T, CLK, CLR: in std_logic; Q: buffer std_logic); end t_ff;architecture design of t_ff is begin process (CLK, CLR, T) begin if (CLR = '1') then Q <= '0'; elsif rising_edge (CLK) then case T is when '0' => Q <= Q; when '1' => Q <= not Q; when others => Q <= '0'; end case; end if; end process;end design;

CLR

JK f-f with an asynch reset and rising edge triggered

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library IEEE;use IEEE.Std_logic_1164.all;

entity JK_FF isport (clock, J, K, reset: in std_logic;

Q, Qbar: out std_logic);end JK_FF;

architecture behv of JK_FF is signal state: std_logic; -- define the useful

signals here signal input: std_logic_vector(1 downto 0);

reset

JK f-f with an asynch reset and rising edge triggered

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begin input <= J & K; -- combine inputs into 2-bit vector p: process(clock, reset) is begin

if (reset='1') then state <= '0';elsif (rising_edge(clock)) then case (input) is -- compare to the truth table

when "11" => state <= not state;when "10" => state <= '1';when "01" => state <= '0';when others => null;end case;

end if; end process; -- concurrent statements Q <= state; Qbar <= not state;end behv; reset

JK f/f with enable using if-then-else structure

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JK_FF_VHDL is port( J,K: in std_logic; Reset: in std_logic; Clock_enable: in std_logic; Clock: in std_logic; Output: out std_logic); end JK_FF_VHDL;

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architecture Behavioral of JK_FF_VHDL is signal temp: std_logic; begin process (Clock) begin if Clock'event and Clock='1' then if Reset='1' then temp <= '0'; elsif Clock_enable ='1' then if (J='0' and K='0') then temp <= temp; elsif (J='0' and K='1') then temp <= '0'; elsif (J='1' and K='0') then temp <= '1'; elsif (J='1' and K='1') then temp <= not (temp); end if; end if; end if; end process; Output <= temp; end Behavioral;

JK f/f with enable using if-then-else structure