VHDL FPGA Applications
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Transcript of VHDL FPGA Applications
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Patterson D6A 1
VHDL/FPGA Applications inSignal Processing andCommunications
By: Robert Patterson and Ismail Jouny
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Overview of Presentation
n Description of an FPGA
n Description of VHDL
n Applications– Error Control Coding
– CDMA Communications
– Master/Slave And Token Ring Networks
– Pattern Classification With A Hopfield NeuralNet
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Design Options
n TTL logic chips– Difficult for large designs
– Customized board
n PLD– Limited by power consumption and time delay
n ASIC/MPGA– Custom masks required for wiring
– Expensive
– Long turnaround time
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What is an FPGA?
n Field Programmable Gate Array
n Consists of:n An array of configurable logic blocks
n Programmable I/O blocks
n Programmable interconnects
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Benefits of Using an FPGA
n Programmed by users at their site usingprogramming hardware
n Can implement tens of thousands of gates oflogic on a single IC
n Can be programmed many times
n Short development time
n Low cost
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What is VHDL?
n VHSIC Hardware Definition Language
n Common Language for Designers (> 50%)
n High-Level Language
n Simulation and Synthesis Tools areAvailable
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Error Control System Overview
A/D converter
Encoder
Introduction of Error
Decoder
D/A converter
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Error Control Coding Overview
n By adding redundancy in the signal, errorscan be detected and corrected
n Signals are broken up into blocks of data
n Parity calculations add extra bits to signal
n Receiver tries to detect and correct the errorthrough the use of the parity bits
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(7,4) Hamming Code
n 4 data bits => 7-bit code word
n Minimum distance between codes is 3
n All single bit errors can be corrected
- or -
n All single and double bit errors can bedetected
A B
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What is CDMA?
n Code Division Multiple Access
n Multiple users can use a wide slice of thebandwidth
n A unique code accesses the user’sinformation
n Codes are made orthogonal as much aspossible to reduce cross correlation
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CDMA Design Overview
Encoder
Encoder
Pn1
Pn2
Decoder
Decoder
Pn1
Pn2
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Spectrum Spreading
n Data signal
n PN-code
n Coded signal
Received signal at Decoder #1 = (M1•Pn1 + M2•Pn2)•Pn1
= M1•Pn1•Pn1 + M2•Pn1•Pn2
= M1 + M2•Pn1•Pn2
= M1
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Master/Slave Network Overview
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Token Ring Network Overview
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Hopfield Neural Net
n An artificial network that is capable ofrecalling certain stored patterns from a setof inputs
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Hopfield Neural Net (cont.)
n The weight matrix is formed fromexemplars
∑
≤≤
≠
1-N j ,i 0 j , = i ,0
j i xx = t
, sj
si
1-M
0 = sij
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Problems Encountered
n VHDL à Synthesis/Implementation
n Memory in FPGA
n Speed of computer in the synthesis ofdesign
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Conclusions
n VHDL/FPGA combination is a verypowerful design tool– Versatile
– Adaptable
– Efficient
– Economic