VHDL - Enumerated Types (Part 3)
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1 Enumerated Types Enumerated Types The first style is used most often to define The first style is used most often to define cases or states for a state machine cases or states for a state machine type type CAR_STATE CAR_STATE is is (back, stop, slow, medium, (back, stop, slow, medium, fast); fast); VHDL VHDL also allows users to create subtypes of a also allows users to create subtypes of a type type The values in the subtype must be a contiguous range The values in the subtype must be a contiguous range of values of the base type from start to end of values of the base type from start to end Subtype Subtype GO_KART GO_KART is is CAR_STATE CAR_STATE range range stop to medium; stop to medium; VHDL VHDL has two predefined integer subtypes has two predefined integer subtypes Subtype Subtype natural natural is is integer integer range range 0 to highest 0 to highest integer; integer; Subtype Subtype positive positive is is integer integer range range 1 to highest 1 to highest integer; integer;
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Lecture 12
Transcript of VHDL - Enumerated Types (Part 3)
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Enumerated TypesEnumerated Types
The first style is used most often to define cases or states The first style is used most often to define cases or states for a state machinefor a state machine
typetype CAR_STATE CAR_STATE isis (back, stop, slow, medium, fast); (back, stop, slow, medium, fast);
VHDL VHDL also allows users to create subtypes of a typealso allows users to create subtypes of a typeThe values in the subtype must be a contiguous range of values The values in the subtype must be a contiguous range of values of the base type from start to endof the base type from start to end
SubtypeSubtype GO_KART GO_KART isis CAR_STATE CAR_STATE rangerange stop to medium; stop to medium;
VHDL VHDL has two predefined integer subtypes has two predefined integer subtypes SubtypeSubtype natural natural isis integer integer rangerange 0 to highest integer; 0 to highest integer;
SubtypeSubtype positive positive isis integer integer rangerange 1 to highest integer; 1 to highest integer;
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Enumerated TypesEnumerated Types
BITBIT – can be ‘0’ or ‘1’ (note single quotes) – can be ‘0’ or ‘1’ (note single quotes)
STD_LOGICSTD_LOGICHas NINE legal values:Has NINE legal values:
‘‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’
Example Subtype DeclarationsExample Subtype DeclarationsSubtypeSubtype twoval_logic twoval_logic isis std_logic std_logic rangerange ‘0’ to ‘1’; ‘0’ to ‘1’;
SubtypeSubtype fourval_logic fourval_logic isis std_logic std_logic rangerange ‘X’ to ‘Z’; ‘X’ to ‘Z’;
SubtypeSubtype negint negint isis integer integer rangerange -2147483647 to -1; -2147483647 to -1;
SubtypeSubtype bitnum bitnum isis integer integer rangerange 31 downto 0; 31 downto 0;
IEEE std_logic_1164 packageIEEE std_logic_1164 package
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ConstantsConstantsThey contribute to readability, maintainability and They contribute to readability, maintainability and portability of programs in any languageportability of programs in any languageThe syntax is as shown The syntax is as shown constant BUS_SIZE: integer := 32; -- constant BUS_SIZE: integer := 32; -- width of componentwidth of component
constant MSB: integer := BUS_SIZE - 1; -- constant MSB: integer := BUS_SIZE - 1; -- bit number of MSB bit number of MSB
constant Z: character := ‘Z’; -- synonym constant Z: character := ‘Z’; -- synonym for Hi-Z valuefor Hi-Z valueThe value of a constant can be a simple expressionThe value of a constant can be a simple expressionConstants can be used anywhere the corresponding value Constants can be used anywhere the corresponding value can be used and they can be put to good use in type can be used and they can be put to good use in type definitionsdefinitions
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ArraysArrays
Another very important category of user-defined typesAnother very important category of user-defined types
Ordered set of elements of the same type, where each element is Ordered set of elements of the same type, where each element is selected by an array indexselected by an array index
Syntax for VHDL array definitionsSyntax for VHDL array definitionstype type-name is array (start to end) of element-type;
type type-name is array (start downto end) of element-type;
type type-name is array (range-type) of element-type;
type type-name is array (range-type range start to end) of element-type;
type type-name is array (range-type range start downto end) of element-type;
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Array declarationsArray declarations
type monthly_count is array (1 to 12) of integer;
type byte is array (7 downto 0) of STD_LOGIC;
constant WORD_LEN: integer := 32;
type word is array (WORD_LEN - 1 downto 0) of STD_LOGIC;
constant NUM_REGS: integer := 8;
type reg_file is array ( 1 to NUM_REGS ) of word;
type traffic_light_state is (reset, stop, wait, go);
type statecount is array (traffic_light_state) of integer;
Array elements are considered to be ordered from left to right in Array elements are considered to be ordered from left to right in the same direction as index rangethe same direction as index range
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Array declarationsArray declarations
type monthly_count is array (1 to 12) of integer; 1
type byte is array (7 downto 0) of STD_LOGIC; 7
Constant WORD_LEN: integer := 32;
type word is array (WORD_LEN - 1 downto 0) of STD_LOGIC; 31
Constant NUM_REGS: integer := 8;
type reg_file is array ( 1 to NUM_REGS ) of word; 1
Type traffic_light_state is (reset, stop, wait, go);
type statecount is array (traffic_light_state) of integer; reset
Left most elements of arrays are shown in blueLeft most elements of arrays are shown in blue
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Array elements and literalsArray elements and literals
Within VHDL program statements, individual array elements are accessed using the array name and the element’s index in parentheses.
If M, B, W, R, and S are signals of variables of the five array types defined in the previous slides then M(11), B(5), W(WORD_LEN – 5), R(0,0), R(0) and S(reset) are all valid elements.
Array literals can be specified by listing the element values in parentheses. The byte variable B could be set to all ones by the statement
B := (‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’);
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Array elements and literalsArray elements and literals
VHDL also has a shorthand notation that allows you to specify values by index.
To set word variable W to all ones except for zeroes in the LSB of each byte
W := (0 => ‘0’, 8 => ‘0’, 16 => ‘0’, 24 => ‘0’, others => 1);
The methods work for arrays with any element type, but the easiest way to write a literal of type STD_LOGIC is to use a “string”
VHDL string is an array of ISO characters enclosed in double quotes such as “Hello”
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StringString
A string is just an array of characters.
A STD_LOGIC array of a given length can be assigned the value of a string of the same length, as long as the characters in the string are taken from the set of nine characters defined as the possible values of the STD_LOGIC elements like ‘0’, ‘1’, ‘U’
The two previous examples can be rewritten as
B := “11111111”;
W := “11111110111111101111111011111110”;
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Example: LogicFcnExample: LogicFcn
entity architecture
A
B
C Y
ports
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Entity Declaration for LogicFcnEntity Declaration for LogicFcnlibrary IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is
port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end entity LogicFcn;
ABC
Y
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Parts of Architecture BodyParts of Architecture Body
architecture ARCH_NAME of ENTITY_NAME is
<declarative section : list internal signals, variables, and components here. For each component used show the port map, (unless port map defined is in a “package”) >
begin
<statement section : all concurrent statements and components and processes in this section execute at the same time, NOT sequentially>
end ARCH_NAME;
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Architecture BodyArchitecture Body
Specifies the internal circuit of an entity, using any Specifies the internal circuit of an entity, using any one of the following modeling styles:one of the following modeling styles:
1.1. As a set of interconnected components, as wired As a set of interconnected components, as wired (called (called structuralstructural modeling) modeling)
2.2. As a set of concurrent signal assignment As a set of concurrent signal assignment statements (called statements (called dataflowdataflow modeling) modeling)
3.3. As a set of sequential assignment statements, As a set of sequential assignment statements, i.e., a “process” (called i.e., a “process” (called behavioralbehavioral modeling) modeling)
4.4. As any combination of the above (called As any combination of the above (called mixedmixed modeling)modeling)
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Architecture Body (Dataflow)Architecture Body (Dataflow)
architecture dataflow of LogicFcn is
begin
Y <= (not A and not B) or C;
end dataflow;
With a signal assignment statement:
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Architecture Body (Dataflow)Architecture Body (Dataflow)
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
With a conditional signal assignment statement:
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Architecture Body (Behavioral)Architecture Body (Behavioral)architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C)
begin
wait on A,B,C;
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
“Label:”Name of process
Sensitivity List - The Process will be executed anytime there is an EVENT (change of state) on one of these signals.
WAIT ON statement - has same effect as sensitivity list. CANNOT USE BOTH. Processes with WAIT statements cannot have sensitivity lists !!
Statements within Processes are executed sequentially. (This is a single IF statement)The process, however, executes concurrently with other processes and concurrent statements in the architecture.
process
Values are assigned to signals when process suspends
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Architecture Body (Structural)Architecture Body (Structural)
A
B
C Y
entity architecture
Internal signals are LOCAL to the Architecture, and Internal signals are LOCAL to the Architecture, and cannot cannot be seen outside itbe seen outside it ! !
notA
notB
andSignal
signals
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Architecture Body (Structural)Architecture Body (Structural)architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
LOCAL SIGNALS are declared within the architecture and they have no MODE (IN, OUT, etc.)
COMPONENT declarations may go here
These are COMPONENT INSTANTIATIONS
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Components for Structural ModelComponents for Structural Modellibrary IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end primitive;
these are component declarations
