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Digital Design — Chapter 7 — Processor Basics 12 October 2007
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Digital Design:An Embedded Systems Approach Using VHDL
Chapter 7Processor Basics
Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
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VHDL
Embedded Computers
A computer as part of a digital systemPerforms processing to implement or control the system’s function
ComponentsProcessor coreInstruction and data memoryInput, output, and input/output controllers
For interacting with the physical world
AcceleratorsHigh-performance circuit for specialized functions
Interconnecting buses
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VHDL
Memory Organization
Von Neumann architectureSingle memory for instructions and data
Harvard architectureSeparate instruction and data memoriesMost common in embedded systems
CPU
…
AcceleratorInstructionmemory
Inputcontroller
Outputcontroller
I/Ocontroller
Datamemory
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VHDL
Bus Organization
Single bus for low-cost low-performance systemsMultiple buses for higher performance
CPU
Accelerator
Instructionmemory
Inputcontroller
Outputcontroller
I/Ocontroller
Datamemory
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VHDL
Microprocessors
Single-chip processor in a packageExternal connections to memory and I/O busesMost commonly seen in general purpose computers
E.g., Intel Pentium family, PowerPC, …
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VHDL
Microcontrollers
Single chip combiningProcessorA small amount of instruction/data memoryI/O controllers
Microcontroller familiesSame processor, varying memory and I/O
8-bit microcontrollersOperate on 8-bit dataLow cost, low performance
16-bit and 32-bit microcontrollersHigher performance
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VHDL
Processor Cores
Processor as a component in an FPGA or ASICIn FPGA, can be a fixed-function block
E.g., PowerPC cores in some Xilinx FPGAs
Or can be a soft coreImplemented using programmable resourcesE.g., Xilinx MicroBlaze, Altera Nios-II
In ASIC, provided as an IP blockE.g., ARM, PowerPC, MIPS, Tensilica coresCan be customized for an application
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VHDL
Digital Signal Processors
DSPs are processors optimized for signal processing operations
E.g., audio, video, sensor data; wireless communication
Often combined with a conventional core for processing other data
Heterogeneous multiprocessor
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VHDL
Instruction Sets
A processor executes a programA sequence of instructions, each performing a small step of a computation
Instruction set: the repertoire of available instructions
Different processor types have different instruction sets
High-level languages: more abstractE.g., C, C++, Ada, JavaTranslated to processor instructions by a compiler
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VHDL
Instruction Execution
Instructions are encoded in binaryStored in the instruction memory
A processor executes a program by repeatedly
Fetching the next instructionDecoding it to work out what to doExecuting the operation
Program counter (PC)Register in the processor holding the address of the next instruction
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VHDL
Data and Endian-nessInstructions operate on data from the data memoryByte: 8-bit data
Data memory is usually byte addressed16-bit, 32-bit, 64-bit words of data
0
least sig. byte
Little endian Big endian
8-bit data
16-bit data
32-bit data
most sig. byte
least sig. byte
most sig. byte
m
m + 1
n
n + 2
n + 3
n + 1
0
least sig. byte
8-bit data
16-bit data
32-bit data
most sig. byte
least sig. byte
most sig. byte
m
m + 1
n
n + 2
n + 3
n + 1
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VHDL
The Gumnut Core
A small 8-bit soft coreCan be used in FPGA designs
Instruction set illustrates features typical of 8-bit cores and processors in generalPrograms written in assembly language
Each processor instruction written explicitlyTranslated to binary representation by an assembler
Resources available on companions web site
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VHDL
Gumnut Storage
r0 0r1r2r3r4r5r6r7
PC
CZ
General-Purpose Registers Condition Code Registers
012
254255
Data Memory(256 × 8-bit, 8-bit addresses)
012
40944095
Instruction Memory(4K × 18-bit, 12-bit addresses)
Program Counter
CarryZero
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VHDL
Arithmetic Instructions
Operate on register data and put result in a registeradd, addc, sub, subcCan have immediate value operand
Condition codesZ: 1 if result is zero, 0 if result is non-zeroC: carry out of add/addc, borrow out of sub/subc
addc and subc include C bit in operation
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VHDL
Arithmetic Instructions
Examplesadd r3, r4, r1
add r5, r1, 2
sub r4, r4, 1
Evaluate 2x + 1; x in r3, result in r4add r4, r4, r3 ; double xadd r4, r4, 1 ; then add 1
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VHDL
Logical Instructions
Operate on register data and put result in a registerand, or, xor, mask (and not)Operate bitwise on 8-bit operandsCan have immediate value operand
Condition codesZ: 1 if result is zero, 0 if result is non-zeroC: always 0
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VHDL
Logical Instructions
Examplesand r3, r4, r5
or r1, r1, 0x80 ; set r1(7)
xor r5, r5, 0xFF ; invert r5
Set Z if least-significant 4 bits of r2 are 0101and r1, r2, 0x0F ; clear high bitssub r0, r1, 0x05 ; compare with 0101
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VHDL
Shift Instructions
Logical shift/rotate register data and put result in a registershl, shr, rol, rorCount specified as a literal operand
Condition codesZ: 1 if result is zero, 0 if result is non-zeroC: the value of the last bit shifted/rotated past the end of the byte
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VHDL
Shift Instructions
Examplesshl r4, r1, 3
ror r2, r2, 4
Multiply r4 by 8, ignoring overflowshl r4, r4, 3
Multiply r4 by 10, ignoring overflowshl r1, r4, 1 ; multiply by 2shl r4, r4, 3 ; multiply by 8add r4, r4, r1
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VHDL
Memory Instructions
Transfer data between registers and data memory
Compute address by adding an offset to a base register value
Load register from memoryldm r1, (r2)+5
Store from register to memorystm r1, (r4)-2
Use r0 if base address is 0ldm r3, 23 ≡ ldm r3, (r0)+23
Condition codes not affected
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VHDL
Memory Instructions
Increment a 16-bit integer in memoryLittle-endian: address of lsb in r2, msb in next locationldm r1, (r2) ; increment lsbadd r1, r1, 1stm r1, (r2)ldm r1, (r2)+1 ; increment msbaddc r1, r1, 0 ; with carrystm r1, (r2)+1
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VHDL
Input/Output Instructions
I/O controllers have registers that govern their operation
Each has an address, like data memoryGumnut has separate data and I/O address spaces
Input from I/O registerinp r3, 157 ≡ inp r3, (r0)+157
Output to I/O registerout r3, (r7) ≡ out r3, (r7)+0
Condition codes not affectedFurther examples in Chapter 8
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VHDL
Branch Instructions
Programs can evaluate conditions and take alternate courses of action
Condition codes (Z, C) represent outcomes of arithmetic/logical/shift instructions
Branch instructions examine Z or Cbz, bnz, bc, bncAdd a displacement to PC if condition is trueSpecifies how many instructions forward or backward to skip
Counting from instruction after branch
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VHDL
Branch Example
Elapsed seconds in location 100Increment, wrapping to 0 after 59ldm r1, 100add r1, r1, 1sub r0, r1, 60 ; Z set if r1 = 60bnz +1 ; Skip to store ifadd r1, r0, 0 ; Z is 0stm r1, 100
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VHDL
Jump Instruction
Unconditionally skips forward or backward to specified address
Changes the PC to the addressExample: if r1 = 0, clear data location 100 to 0; otherwise clear location 200 to 0
Assume instructions start at address 1010: sub r0, r1, 011: bnz +212: stm r0, 10013: jmp 1514: stm r0, 20015: ...
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VHDL
Subroutines
A sequence of instructions that perform some operation
Can call them from different parts of a program using a jsb instructionSubroutine returns with a ret instruction
subroutine
instructions
……
…
ret
mjsb m
…
jsb m
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VHDL
Subroutine ExampleSubroutine to increment second count
Address of count in r2ldm r1, (r2)add r1, r1, 1sub r0, r1, 60bnz +1add r1, r0, 0stm r1, (r2)ret
Call to increment locations 100 and 102add r2, r0, 100jsb 20add r2, r0, 102jsb 20
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VHDL
Return Address Stack
The jsb saves the return address for use by the ret
But what if the subroutine includes a jsb?
Gumnut core includes an 8-entry push-down stack of return addresses
return addr for first call
return addr for second call
return addr for first call
return addr for second call
return addr for third call
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VHDL
Miscellaneous Instructions
Instructions supporting interruptsSee Chapter 8reti Return from interruptenai Enable interruptsdisi Disable interruptswait Wait for an interruptstby Stand by in low power mode until
an interrupt occurs
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VHDL
The Gumnut Assembler
Gasm: translates assembly programsGenerates memory images for program text (binary-coded instructions) and dataSee documentation on web site
Write a program as a text fileInstructionsDirectivesCommentsUse symbolic labels
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VHDL
Example Program; Program to determine greater of value_1 and value_2
textorg 0x000 ; start here on resetjmp main
; Data memory layout
datavalue_1: byte 10value_2: byte 20result: bss 1
; Main program
textorg 0x010
main: ldm r1, value_1 ; load valuesldm r2, value_2sub r0, r1, r2 ; compare valuesbc value_2_greaterstm r1, result ; value_1 is greaterjmp finish
value_2_greater: stm r2, result ; value_2 is greater
finish: jmp finish ; idle loop
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VHDL
Gumnut Instruction Encoding
Instructions are a form of informationCan be encoded in binary
Gumnut encoding18 bits per instructionDivided into fields representing different aspects of the instruction
Opcodes and function codesRegister numbersAddresses
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VHDL
Gumnut Instruction Encoding
1 1 01 1 1 fn disp6 2 2 8
Branch
Arith/LogicalRegister
Arith/LogicalImmediate
Shift
Memory, I/O
1 1 01 fnrd rs rs24 3 33 3 2
0 fn rd rs immed1 83 3 3
1 1 0 fnrd rs count3 31 23 3 3
1 0 fn rd rs offset2 2 3 3 8
1 1 1 1 0
0
fn addr5 1 12
Jump
1 1 1 1 1 1 fn7 3 8
Miscellaneous
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VHDL
Encoding Examples
Encoding for addc r3, r5, 24Arithmetic immediate, fn = 001
0 fn rd rs immed
0 00 1 10 1 01 1 0 0 10 1 00 0
1 83 3 3
Instruction encoded by 2ECFC
1 1 01 1 1 fn disp6 2 2 8
1 1 0 0 01 1 1 1 1 1 1 11 1 0 01
Branch bnc -4
05D18
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VHDL
Other Instruction Sets
8-bit cores and microcontrollersXilinx PicoBlaze: like Gumnut8051, and numerous like it
Originated as 8-bit microprocessorsInstructions encoded as one or more bytesInstruction set is more complex and irregularComplex instruction set computer (CISC)C.f. Reduced instruction set computer (RISC)
16-, 32- and 64-bit coresMostly RISCE.g., PowerPC, ARM, MIPS, Tensilica, …
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VHDL
Instruction and Data Memory
In embedded systemsInstruction memory is usually ROM, flash, SRAM, or combinationData memory is usually SRAM
DRAM if large capacity needed
Processor/memory interfacingGluing the signals together
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VHDL
Example: Gumnut Memory
inst_adr_oinst_dat_i
rst_i
gumnut dataSRAM
inst_cyc_oinst_stb_o
inst_ack_i
data_adr_o
data_dat_idata_dat_o
data_cyc_odata_stb_o
data_ack_i
data_we_o
adr
dat_odat_i
en
weadr
dat_o
en
clk_iclk_i
instructionROM
clk_i
D Q
clk
DQ
clk
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VHDL
Example: Gumnut Memory
IMem : process (clk) isbegin
if rising_edge(clk) thenif inst_cyc_o = '1' and inst_stb_o = '1' then
inst_dat_i <=instr_ROM(to_integer(inst_adr_o(10 downto 0)));
inst_ack_i <= '1';else
inst_ack_i <= '0';end if;
end if;end process IMem;
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VHDL
Example: Gumnut Memory
DMem : process (clk) isbegin
if rising_edge(clk) thenif data_cyc_o = '1' and data_stb_o = '1' then
if data_we_o = '1' thendata_RAM(to_integer(data_adr_o)) <= data_dat_o;data_dat_i <= data_dat_o;data_ack_i <= '1';
elsedata_dat_i <= data_RAM(to_integer(data_adr_o));data_ack_i <= '1';
end if;else
data_ack_i <= '0';end if;
end if;end process DMem;
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VHDL
Example: Microcontroller Memory
A(15..8)
A(7..0)
CE
WE
OE
D
A(16)
D
LE
P2
Q
PSEN
ALE
8051 SRAM
RD
WR
P0
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VHDL
32-bit Memory
Four bytes per memory wordLittle-endian: lsb at least addressBig-endian: msb at least address
0 1 2 34 5 6 78 9 10 11
Partial-word readRead all bytes, processor selects those needed
Partial-word writeUse byte-enable signals
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VHDL
Example: MicroBlaze Memory
D_in
A
SSRAM
en
wr
D_out
clk
D_in
A
SSRAM
en
wr
D_out
clk
D_in
A
SSRAM
en
wr
D_out
clk
D_in
A
SSRAM
en
wr
D_out
clk
0:7
8:15
16:23
24:31
0:7
2:16
8:15
16:23
24:31
Addr
Data_Write
AS
Read_Strobe
Ready
Clk
Data_Read
Write_Strobe
Byte_Enable(0)
Byte_Enable(1)
Byte_Enable(2)
Byte_Enable(3)
+V
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VHDL
Cache Memory
For high-performance processorsMemory access time is several clock cyclesPerformance bottleneck
Cache memorySmall fast memory attached to a processorStores most frequently accessed items, plus adjacent itemsLocality: those items are most likely to be accessed again soon
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VHDL
Cache Memory
Memory contents divided into fixed-sized blocks (lines)
Cache copies whole lines from memoryWhen processor accesses an item
If item is in cache: hit - fast accessOccurs most of the time
If item is not in cache: missLine containing item is copied from memorySlower, but less frequentMay need to replace a line already in cache
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VHDL
Fast Main Memory Access
Optimize memory for line access by cacheWide memory
Read a line in one access
Burst transfersSend starting address, then read successive locations
PipeliningOverlapping stages of memory accessE.g., address transfer, memory operation, data transfer
Double data rate (DDR), Quad data rate (QDR)Transfer on both rising and falling clock edges
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VHDL
Summary
Embedded computerProcessor, memory, I/O controllers, buses
Microprocessors, microcontrollers, and processor coresSoft-core processors for ASIC/FPGAProcessor instruction sets
Binary encoding for instructionsAssembly language programsMemory interfacing