VHDL Configurations Tutorial

Active-HDL Help Copyright Aldec, Inc.

VHDL Configurations Tutorial

Table Of Contents VHDL Configurations Tutorial.......................................................................................................... 1

Introduction .................................................................................................................................. 1 Loading sample project................................................................................................................ 1 Changing implementation of the BCD counter ............................................................................ 5 Adding a new architecture to the design...................................................................................... 8 Creating a new configuration ..................................................................................................... 11 Changing implementation by using symbol properties .............................................................. 17

i


Introduction

In VHDL, an entity is bound to a single architecture and this association is done by means of the default bindings. However, designers often use several implementations for selected parts of a project making the default binding mechanism insufficient to enable all implementations from a design since it binds an entity to the most recently compiled architecture. When your design requires the use of several architecture bodies for the same entity, you can specify VHDL configuration in your design. VHDL configuration is a collective description of bindings between a real interface and the corresponding architecture bodies for component instantiations in a project. VHDL configuration is also a separate design unit that can be simulated and analyzed apart from other units. VHDL configurations can be used if you need to find out which of the available implementations meets your primary objectives (e.g. a project is faster or uses less device resources), preserve the synthesis or implementation attributes and directives, use components from external libraries, and check their influence on simulation, synthesis, or implementation of your design. Active-HDL allows you to create multiple architectures and bind them by means of VHDL configurations; this tutorial will be used to show how to create and use configurations in Active-HDL. The tutorial is based on the freq_meter design that is shipped with Active-HDL as a sample project.

Loading sample project

1. The first step of the tutorial is to load the freq_meter workspace. To load it, open the Workspace/Design Explorer window (File | Open Workspace/Design Explorer). Then, double-click the freq_meter workspace icon (Samples | VHDL_Designs). Figure 1 shows its default location.

Figure 1. Default location of freq_meter. 2. The workspace you have just opened contains the design that has to be compiled before you proceed with the simulation phase. To compile it, choose the menu command Design | Compile All. After the successful compilation, the Console window should display a line: # Compile success 0 Errors 0 Warnings Analysis time : 1.0 [s] and you will be prompted to set up the top-level unit. In our tutorial, we select testbench_cnt_bcd_conf as the top-level unit, as it is illustrated in the Figure 2. Next, you can

1


click the OK button to close the window. The freq_meter sample project already has a pre-defined configuration; however, the following steps will show you how to modify it (existing configuration) and then how to add the new one on another level of the hierarchy of the design.

Figure 2. Setting up the top-level unit of the design. 3. After all files have been compiled successfully and testbench_cnt_bcd_conf has been selected as the top-level unit, open the testbench_cnt_bcd_conf.vhd file. It should contain the VHDL code presented in Figure 4.

Figure 3. Freq_meter with testbench_cnt_bcd_conf set as top-level. The configuration file stores information on bindings between instances (U0-U5) and entities as well as corresponding architecture bodies found in the current working library. Each of the listed instances can be "re-configured" by using an alternative implementation. The freq_meter sample project has been equipped with an additional implementation of the BCD counter (CNT_BCD2.bde). configuration testbench_cnt_bcd_conf of testbench is for stimulusfromfile for UUT : freq_top use entity work.freq_top (freq_top); for freq_top for U1 : cnt_bcd use entity work.cnt_bcd (cnt_bcd);

2


end for; for U2 : hex2led use entity work.hex2led (hex2led); end for; for U3 : hex2led use entity work.hex2led (hex2led); end for; for U4 : hex2led use entity work.hex2led (hex2led); end for; for U5 : hex2led use entity work.hex2led (hex2led); end for; for U0 : control use entity work.control (control_arch); end for; end for; end for; end for; end testbench_cnt_bcd_conf; Figure 4. The contents of the testbench_cnt_bcd_conf.vhd file 4. To see both implementations of the U1 counter instantiated in the freq_top(freq_top) unit (freq_top.bde), open the CNT_BCD.bde and CNT_BCD2.bde files. The first one contains four instances of the CNT_4B component coming from the design library and three AND gates coming from the Built-in symbols library (this is a library of primitives that can be viewed in the Block Diagram Editor's Symbols Toolbox window).

Figure 5. The basic implementation of the BCD counter (CNT_BCD.bde). The second implementation consists of seven graphical objects: four representing processes (counters) and three representing assignments of signals used to build the CLOCK ENABLE signal (AND gates).

3


NOTE: For more information on Graphical Processes, refer to the Graphical Process/Always Blocks topic in the On-line Documentation (Active-HDL Help - Active-HDL Tools - Block Diagram Editor - Block Diagram Items) or type in Graphical Process/Always Blocks in the Type in the keyword to find field of the Index tab.

Figure 6. The new implementation of the BCD counter (CNT_BCD2.bde). 5. If required, you can freely modify the code of each process by double-clicking the Graphical Process/Signal Assignment object or choosing the Edit option from the context menu. Figures 7 and 8 present the contents of the selected Graphical Process blocks.

Figure 7. The contents of Graphical Process block CNT1.

Figure 8. The contents of Graphical Signal Assignments block AND1.

The following steps will explain how to change the implementation of the BCD counter from CNT_BCD.bde to CNT_BCD2.bde.

4


Changing implementation of the BCD counter

Before we change the project's configuration, let us see how the structure of our design is displayed in the Structure tab of the Design Browser window. By default, after the top-level unit has been set, the Design Browser displays only a simulation top-level unit and declared packages (Figure 9). Active-HDL also allows designers to show all specified design units coming from different levels of the project's hierarchy. 6. To change the view, right click on the upper part of the Structure tab and choose the Show/Hide option.

Figure 9. By default, the Design Browser displays only the selected top-level unit and declared packages. The Show/Hide window presented in Figure 10 allows users to change the settings of the displayed structure. The following options are available:

The display of all design units regardless of the project's hierarchy The display of the top-level unit and all instantiated components The display of the selected design units

Figure 10. The Show/Hide window. 7. To continue our tutorial, select Show all and press OK. Now, the structure of the freq_meter sample design should be the same as shown in Figure 11.

5


Figure 11. The structure of the freq_meter sample design after the selection of the Show all option. This setting additionally allows you to observe the changes made in the design's structure and graphically present the differences between the default bindings resulting from the current working library and configurations specified for the top-level unit. To see an example of such a difference, let us look at the cnt_bcd (cnt_bcd2) component displayed in Figure 11 and /UUT/U1 instance from Figure12. Note that this component has two different implementations since the binding for cnt_bcd (cnt_bcd2) results from the change discussed below and cnt_bcd (cnt_bcd) comes from the testbench_cnt_bcd_conf design configuration stored in the testbench_cnt_bcd_conf.vhd file. 8. Expand the structure of selected top-level and right-click the instance U1 (U1: cnt_bcd(cnt_bcd)). 9. Choose the Select Architecture/Configuration option from the context menu as it is shown in Figure 12.

Figure 12. The context menu of the Structure tab allows designers to make changes in the configuration of their projects. 10. In the Select Architecture/Configuration dialog, select the cnt_bcd2 architecture and then click OK. Note the change that takes place in the design configuration; the Console window displays the following message: # Design: The 'testbench_cnt_bcd_conf' configuration from .\src\testbench_cnt_bcd_conf.vhd has been changed and should be recompiled.

6


Figure 13. The Select Architecture/Configuration window. In the first configuration, you can observe that the structure is displayed by the Hierarchy Viewer. Now, the cnt_bcd entity is bound to the cnt_bcd2 architecture (Figure 14); previously, it was bound to cnt_bcd.

Figure 14. The change in the design configuration. The updated testbench_cnt_bcd_conf.vhd configuration file can be viewed from the Files tab in the second configuration. 11. To see the changes in the testbench_cnt_bcd_conf.vhd configuration file, double-click its icon or name in the Design Browser window.

Figure 15. After the configuration has been updated, the configuration file needs to be re-compiled. 12. Two general changes have been made in the updated configuration file (Figure 16):

Several lines of comments have been added

7


The configuration of the U1 instance has been changed

Figure 16: The updated testbench_cnt_bcd_conf.vhd configuration file. Since now, whenever you set testbench_cnt_bcd_conf as top-level you will simulate the freq_meter sample design with the cnt_bcd entity bound to cnt_bcd2 architecture. However, to make the change described above, you need to have another implementation ready-to-use. Otherwise, a new implementation has to be created. Active-HDL allows designers to create new architectures (implementations), define, and manage VHDL Configurations to make the re-configuration of the design or its selected part fast and easy during the development or testing process. Let us try to create a new implementation for the hex2led entity and use it in the Creating a New Configuration chapter of our tutorial.

Adding a new architecture to the design

13. To create a new implementation, point to the hex2led entity that intend to bind a new architecture, right-click on it and choose the Add New Architecture option from the context menu.

Figure 17. The Add New Architecture option is available in the pop-up menu of the Files tab. 14. In the Add New Architecture window, enter the name of a new architecture, choose the type of source file for a new implementation, and specify its location. Next, press OK.

8


Figure 18. The Create New Architecture window. 15. The newly created hex2led10.vhd file (empty template of the new architecture) should be added to the design tree.

Figure 19. The design with a newly created architecture added.

The next steps will show how to modify the original HEX2LED converter for this tutorial's purposes.

16. Load the hex2led.vhd file and select the part of the code shown in Figure 20. with HEX select LED


"0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --B "1000110" when "1100", --C "0100001" when "1101", --D "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0

Figure 20. The implementation of the HEX2LED converter. 17. Copy the selection and paste it into the hex2led10.vhd source file. Modify the code to the form presented in Figure 21. Note that now HEX2LED converts only vectors with the range from "0000" to "1001". Other input vectors are converted to the "E" character. Additionally, the code of digit "7" has been modified.

library IEEE; use ieee.std_logic_1164.all; --}} End of automatically maintained section architecture hex2led10 of hex2led is begin -- enter your statements here -- with HEX select LED


Figure 22. The contents of the modified freq_meter sample design. 19. Switch to the Structure tab and expand the hierarchy of the freq_top unit. Note that all instances of hex2led (U2-U5) have been bound to the hex2led10 architecture and U2-U5 instantiated in UUT are still bound to the hex2led architecture.

Figure 23. The Hierarchy Viewer presents different implementations of instances U2-U5.

Creating a new configuration

When the new implementation for the hex2led entity has been compiled into the current working library, we can proceed to the creation of the new configuration for the freq_top unit. 20. To do so, choose Create New Configuration from the pop-up menu.

11


Figure 24. To create a configuration for the selected unit, right-click it and choose Create New Configuration from the pop-up menu. 21. Enter the name of the configuration for the freq_top unit and close the window by clicking OK.

Figure 25. The Create New Configuration window. The new configuration freq_top_conf : freq_top(freq_top) is displayed by the Hierarchy Viewer (Figure 26) and the freq_top_conf.vhd file has been added to the design (Figure 27).

12


Figure 26. The new configuration freq_top_conf : freq_top(freq_top) is displayed by the Hierarchy Viewer. 22. Let us see the contents of the newly created configuration file and load it into the HDL Editor window.

Figure 27. The freq_top_conf.vhd file has been added to the design. The contents of the newly created configuration file is shown in Figure 28. configuration freq_top_conf of freq_top is for freq_top end for; end freq_top_conf; Figure 28. The contents of the newly created freq_top_conf.vhd configuration file.

In the next step, we will modify the configuration of freq_top by changing the implementation of two instantiated components: U3 and U5.

23. Right-click the U3 : hex2led(hex2led10) component and choose the Select Architecture/Configuration option.

13


Figure 29. Selecting a new implementation of the U3 : hex2led(hex2led10) component. 24. Point to the hex2led architecture and close the window by clicking the OK button.

Figure 30. The Select Architecture/Configuration window. 25. Right-click the U5 : hex2led(hex2led10) component, then choose the Select Architecture/Configuration option and repeat step #24. Note the change that takes place in the freq_top_conf.vhd configuration file (see Figure 4); the Console window displays the following message: # Design: The 'freq_top_conf' configuration from ..\src\freq_top_conf.vhd has been changed and should be recompiled. configuration freq_top_conf of freq_top is for freq_top for U3 : hex2led use entity work.hex2led (hex2led); end for; for U5 : hex2led use entity work.hex2led (hex2led); end for; end for; end freq_top_conf;

14


Figure 31. The freq_top_conf.vhd configuration file with changes resulting from the selection of the hex2led architecture for U3 and U5. 26. Compile the freq_top_conf.vhd configuration file into the current working library.

In the following steps, we will learn how to manage configurations and see how the Hierarchy Viewer displays units configurations of which have already been specified. Let us note a couple of important facts here. Up to now we: 1. Changed the default and pre-defined configuration stored in the testbench_cnt_bcd_conf.vhd file. 2. This configuration has been modified in step 9 and is shown in Figure 12. 3. Created a new additional architecture for the HEX2LED component in step 13. 4. Created a new configuration for freq_top (freq_top_conf) in the Creating a New Configuration section - step 20. 5. Changed this configuration by specifying the hex2led architecture (instead of hex2led10) for the components U3 and U5 in step 23.

We will now change the configuration of the UUT : freq_top(freq_top) unit instantiated in testbench (stimulusfromfile). 27. Right-click the UUT : freq_top(freq_top) unit and choose the Select Architecture/Configuration option as it is shown in Figure 32.

Figure 32. Selecting the configuration for UUT : freq_top(freq_top). 28. Choose freq_top_conf in the Select Architecture/Configuration window and then click OK. Please note that the testbench for the simulation top-level unit has been modified once again after you chose freq_top_conf. This change is also denoted by the Console window:

15


# Design: The 'testbench_cnt_bcd_conf' configuration from .\src\testbench_cnt_bcd_conf.vhd has been changed and should be recompiled.

Figure 33. The Select Architecture/Configuration window. 29. Compile the testbench_cnt_bcd_conf.vhd configuration file into the current working library. Since now, the project configuration is stored and specified in two files: freq_top_conf.vhd and testbench_cnt_bcd_conf.vhd.

Figure 34. The change in the project configuration is displayed in the Structure tab. 30. Open the testbench_cnt_bcd_conf.vhd configuration file and compare its contents with the code presented in Figure 4. The modified configuration for testbench(stimulusfromfile) now points to another configuration that stores information on how entities of appropriate components are bound to their corresponding architectures. configuration testbench_cnt_bcd_conf of testbench is for stimulusfromfile for UUT : freq_top use configuration work.freq_top_conf; end for; end for; end testbench_cnt_bcd_conf;

16


Figure 35. The modified testbench_cnt_bcd_conf configuration. Active-HDL's Hierarchy Viewer also facilitates the analysis of the project's configuration. Designers can both view/display a configuration of the whole project and automatically generate files describing the project's configuration. The Hierarchy Viewer allows designers to present configurations, manage them by using Active-HDL's graphical interface and to create and/or update files containing the VHDL source code. Let us see now how the Hierarchy Viewer presents bindings in our sample project. 31. In the Structure tab, right-click the simulation top-level unit (testbench_cnt_bcd_conf) and choose the View Architecture/Configuration option.

Figure 36. The View Architecture/Configuration window. 32. Point to stimulusfromfile and then click OK.

Figure 37. The Hierarchy Viewer also displays project configurations of units other than simulation top-level. After you have selected another implementation/configuration (not the one distinguished as Simulation Top-Level), the Hierarchy Viewer restores the information on different bindings, which allows you to, e.g. find and/or compare differences among several configurations of the design.

Changing implementation by using symbol properties

17


If your projects are based on block diagrams, you can change an implementation of selected components by changing their architecture specification(s) in the Symbol Properties window.

NOTE: To modify a configuration of the project by using this method, a new implementation must be compiled to the current working library first. This version of Active-HDL does not support architectures coming from a library other than the current working one.

33. To change the implementation for a selected instance, right-click a component in the Block Diagram Editor window (freq_top.bde) and select the Properties option. Let us change the implementation of U5.

Figure 38. The Symbol Properties window. 34. In the General tab, point to the new hex2led10 implementation available from the Architecture drop-down list. Next, save the change by choosing OK. The consequence of the change that is displayed in Figure 39 is the modified source code listed in Figure 40.

18


Figure 39. U5 with the changed implementation (now, its entity is bound to the hex2led10 architecture). 35. Compile the modified configuration (freq_top_conf.vhd) to update the design library. configuration freq_top_conf of freq_top is for freq_top for U3 : hex2led use entity work.hex2led (hex2led); end for; for U5 : hex2led use entity work.hex2led (hex2led10); end for; end for; end freq_top_conf; Figure 40. The updated freq_top_conf.vhd configuration file. If all resource files are compiled, the design is ready for simulation. You can now initialize simulation and simulate your newly configured freq_meter sample design. Thank you for using Active-HDL!

19

VHDL Configurations Tutorial Introduction Loading sample project Changing implementation of the BCD counter Adding a new architecture to the design Creating a new configuration Changing implementation by using symbol properties

VHDL Configurations Tutorial

Documents

Transcript of VHDL Configurations Tutorial