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Hello All..

I have problem in my code. I have created code for 8 bit shift register right..

ie my input is 11001011

then in

1st clock :- output should be :- 011001012nd clock :- output should be :- 00110010

3rd clock :- output should be :- 00011001

4th clock :- output should be :- 000011005th clock :- output should be :- 00000110

6th clock :- output should be :- 000000017th clock :- output should be :- 00000000(Ie at the end of clock 8, it should be 0h)

Please correct my code :-

library ieee;use ieee.std_logic_1164.all;

entity shift is

port(C, SI : in std_logic;SO : out std_logic);

end shift;architecture archi of shift is

signal tmp: std_logic_vector(7 downto 0);begin

process (C)

beginif (C'event and C='1') thenfor i in 0 to 6 loop

tmp(i+1) = tmp(i);end loop;tmp(0) = SI;

end if;

end process;SO = tmp(7);end archi;

Thanks a lot

#2July 21st, 2007, 12:27 AM

AvatarAltera Guru

Join Date: May 2007Posts: 352Rep Power: 2295

Re: VHDL code for Right Shift register

Your vector is std_logic_vector(7 downto 0) Left to Right, corrrect.

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7/30/2019 Vhdl Codes (3)

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In your loop process, you are looping first with index value as 0.

So, tmp(0+1) = tmp (0); will result in tmp(1) getting written with tmp(0).

This will take the second from right location and load it with the right most location.

I do not believe this will accomplish your desired shift to the right, it will move the right

most value into all the locations to the left.

You will then be loading the right most location with the SI value.

Just draw out step by step what you are trying to do and you will see that you might wantto;

SO = tmp(0);for i in 1 to 7 loop

tmp (i-1) = tmp(i);

end loop;tmp(7) = SI;

and also, where is tmp declared as a register, not just as a signal?Tmp needs to hold the value, right.

I hope this helps.

#3July 21st, 2007, 06:40 AM

shah_Satish2002Altera Scholar

Join Date: Jul 2007Posts: 25Rep Power: 1620

Re: VHDL code for Right Shift register

Hi..Avataar,

I am really really thankful to you..

Last edited by shah_Satish2002; July 21st, 2007 at06:11 PM..

#4July 23rd, 2007, 11:51 AM

Joe DAdministrator

Join Date: Jan 2007Posts: 151Rep Power: 1

Re: VHDL code for Right Shift register

shash_satish2002, its great that you are getting responses, but my advice is that if you

keep using forums to help with homework and labs, you'll never do well during your exams

or in your post-university career.

These questions can be answered by debug simulation and books...

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7/30/2019 Vhdl Codes (3)

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#5

July 23rd, 2007, 12:23 PM

shah_Satish2002Altera Scholar

Join Date: Jul 2007Posts: 25Rep Power: 1620

Re: VHDL code for Right Shift register

Hello Sir,

I am sorry..But actually i am doing project in company and i am just beginner in this field

but this forum help me lot.

Thank you sir.

#6

July 23rd, 2007, 10:30 PM

AvatarAltera Guru

Join Date: May 2007Posts: 352Rep Power: 2295

Re: VHDL code for Right Shift register

Shah,

Where are you located, or, if you like, adjust your profile setting to allow mw to send you aprivate e-mail?

#7June 12th, 2010, 03:50 PM

wadheraswatiAltera Pupil

Join Date: Jun 2010Posts: 18Rep Power: 532

Re: VHDL code for Right Shift register

This is a 8 BIT shift register with synchronous set SISO

library ieee;use ieee.std_logic_1164.all;

entity shift is

port(C, SI, S : in std_logic;SO : out std_logic);

end shift;

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7/30/2019 Vhdl Codes (3)

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architecture archi of shift is

signal tmp: std_logic_vector(7 downto 0);beginprocess (C, S)

beginif (C'event and C='1') then

if (S='1') thentmp '1');

else

tmp

7/30/2019 Vhdl Codes (3)

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