UNIT-3

DESIGN COMBINATIONAL CKT USING ARCHITECTURE MODEL(a) DATA-FLOW MODEL

(b) BEHAVIOR MODEL(c) STRUCTURAL MODEL

VHDL CODE FOR MULTIPLEXER WITH DATA FLOW MODEL . library IEEE;use IEEE.STD_LOGIC_1164.all;

entity MUX_4X1 is port(

A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC; S : in STD_LOGIC_VECTOR(1 down to 0); Y : out STD_LOGIC

);end MUX_4X1;architecture MUX_DATA of MUX_4X1 isbeginY<= A WHEN S(1)='0' AND S(0)='0' ELSE B WHEN S(1)='0' AND S(0)='1' ELSE C WHEN S(1)='1' AND S(0)='0' ELSE

D WHEN S(1)='1' AND S(0)='1' ;end MUX_DATA;

VHDL CODE FOR MULTIPLEXER WITH BEHAVIORAL-MODEL DESIGN

library IEEE;use IEEE.STD_LOGIC_1164.all;entity MUX_4X1 is

port( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC;

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S : in STD_LOGIC_VECTOR(1 down to 0); Y : out STD_LOGIC

);end MUX_4X1;architecture MUX_BEH of MUX_4X1 isbegin

PROCESS(A,B,C,D,S) BEGIN

CASE S IS WHEN "00" => Y<= A; WHEN "01" => Y<= B; WHEN "10" => Y<= C; WHEN "11" => Y<= D; WHEN OTHERS => NULL;

END CASE; END PROCESS;

end MUX_BEH;

VHDL CODE FOR MULTIPLEXER WITH structural style model library IEEE;use IEEE.STD_LOGIC_1164.all;

entity MUX4X1 is port(

A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC; S0 : in STD_logic; S1 : IN STd_logic; Y : out STD_LOGIC

);end MUX4X1;architecture MUX_STRU of MUX4X1 is

COMPONENT AND3PORT( L,M,O: IN STD_LOGIC; N: OUT STD_LOGIC);

END COmponent;COMPONENT OR4

PORT( H,I,J,K: IN STD_LOGIC; H1: OUT STD_LOGIC);

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END COmponent;COMPONENT INV_1

PORT( E: IN STD_LOGIC; F: OUT STD_LOGIC);END COmponent;

for v0:and3 use entity work.and3(and3);for v4:or4 use entity work.or4(or4);for u0:inv_1 use entity work.inv_1(inv_1);

SIGNAL S0BAR,S1BAR,W,X,G,Z: STD_LOGIC;BEGIN

U0: INV_1 PORT MAP (S0,S0BAR);U1: INV_1 PORT MAP (S1,S1BAR);V0: AND3 PORT MAP (A,S1BAR,S0BAR,W); V1: AND3 PORT MAP (B,S1BAR,S0 ,X);V2: AND3 PORT MAP (C,S1 ,S0BAR,G);V3: AND3 PORT MAP (D,S1 ,S0 ,Z);V4: OR4 PORT MAP ( W,X,G,Z,Y);

end MUX_STRU;--1-bit comparator using behavioral style.entity comp is

port ( a: in bit_vector(0 to 1);e: out bit_vector(2 downto 0));end entity;

architecture comp_beha of comp isbegin

process(a)variable temp : bit;begin

case a iswhen "00" => e <="100";when "01" => e <="010";when "10" => e <="001";when "11" => e <="100";when others => null;end case;

end process;end architecture;

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--1-bit comparator using structural style model

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity COMP_1 is port(

A : in STD_LOGIC; B : in STD_LOGIC; E : out STD_LOGIC; L : out STD_LOGIC; G : out STD_LOGIC

);end COMP_1;

architecture COMP_STRU of COMP_1 iscomponent xnor2

port(l, m: in STD_LOGIC; n: out STD_LOGIC);end component; component and2

port(x, y: in STD_LOGIC; z: out STD_LOGIC);end component;component inv

port( s: in STD_LOGIC; t: out STD_LOGIC);end component; for A1:and2 use entity work.and2(and2);

for X1:xnor2 use entity work.xnor2(xnor2);for I1:inv use entity work.inv(inv);

signal abar,bbar: STD_LOGIC;begin

I1: INV PORT MAP( A, ABAR);I2: INV PORT MAP (B,BBAR);X1: xnor2 port map ( a, b, e);A1: and2 port map( abar,b,l);A2: and2 port map(a,bbar,g);

end COMP_STRU;

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--4-bit comparator using data flow model. use IEEE.STD_LOGIC_1164.all;

entity \4_bit\ is port(

a : in STD_LOGIC_VECTOR(0 to 3); b : in STD_LOGIC_VECTOR(0 to 3); agtb : out STD_LOGIC; aeqb : out STD_LOGIC; altb : out STD_LOGIC

);end \4_bit\;

architecture \4_bit_data\ of \4_bit\ isbeginaeqb <= '1' when a=b else '0';agtb<= '1' when a>b else '0';altb <= '1' when a<b else'0';

end \4_bit_data\;

--4-bit comparator using behavioral style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity \4_comp\ is port(

a : in STD_LOGIC_VECTOR(0 to 3); b : in STD_LOGIC_VECTOR(0 to 3); agtb : out STD_LOGIC; altb : out STD_LOGIC; aeqb : out STD_LOGIC

);end \4_comp\;

architecture \4_comp_beh\ of \4_comp\ is

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begin process(a,b)begin

if(a>b) thenagtb<= '1';aeqb<='0';altb<= '0';elsif(a<b) thenagtb<= '0';aeqb<='0';altb<= '1';elsif(a=b)then agtb<= '0';aeqb<='1';altb<= '0';end if;end process;

end \4_comp_beh\;

--4-bit comparator using structural style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity \4_comp_stru\ is port(

a : in STD_LOGIC_VECTOR(0 to 3); b : in STD_LOGIC_VECTOR(0 to 3); aeqb : inout STD_LOGIC; agtb : inout STD_LOGIC; altb : out STD_LOGIC

);end \4_comp_stru\;

architecture \4_comp_str\ of \4_comp_stru\ iscomponent xnor2

port(l,m: in std_logic;n: out std_logic);

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end component;component and2

port(x,y: in std_logic; z: out std_logic);end component;component inv

port (u: in std_logic; v: out std_logic);end component;component and3

port(l,m,o: in std_logic;n: out std_logic);end component;component or4

port(m1,m2,m3,m4: in std_logic; mf: out std_logic);end component; component and4

port(q1,q2,q3,q4: in std_logic; qf: out std_logic);end component; component and5

port (e1,e2,e3,e4,e5: in std_logic; ef: out std_logic);end component;component nor2

port(l1,l2: in std_logic; lf: out std_logic);end component;signal i0,i1,i2,i3,j0,j1,j2,j3,j4,j5,h0,h1,h2,h3: std_logic;begin

m1: inv port map (b(3),i3);m2: inv port map (b(2),i2);m3: inv port map (b(1),i1);m4: inv port map (b(0),i0);m5: xnor2 port map (a(3),b(3),j3);m6: xnor2 port map (a(2),b(2),j2);m7: xnor2 port map (a(1),b(1),j1);m8: xnor2 port map (a(0),b(0),j0);m9: and2 port map (a(3),i3,h3);m10: and3 port map (a(2),i2,j3,h2);m11: and4 port map (a(1),i1,j2,j3,h1);m12: and5 port map (a(0),i0,j1,j2,j3,h0);m13: and4 port map (j0,j1,j2,j3,aeqb);m14: or4 port map (h0,h1,h2,h3,agtb);m15: nor2 port map (aeqb,agtb,altb);

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end \4_comp_str\;--vhdl code for halfadder using data flow style model.entity ha is

port( a, b: in bit; sum,carry: out bit);end entity;architecture ha1 of ha isbegin

sum<= a xor b;carry<= a and b;end architecture;

--vhdl code for halfadder using structural style model.library IEEE;use IEEE.STD_LOGIC_1164.all;entity ha is

port( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC

);end ha;

architecture ha_stru of ha is component xor2

port(l,m: in STD_LOGIC; n: out STD_LOGIC);end component; component and2

port(x,y: in STD_LOGIC; z: out STD_LOGIC);end component; for x1: xor2 use entity work.xor2(xor2);

for a1: and2 use entity work.and2(and2);begin

x1: xor2 port map( a, b, sum);a1: and2 port map(a,b,carry); end ha_stru;

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--vhdl code for halfadder using Behavioral style model.entity ha is

port( a, b: in bit; sum,carry: out bit);end entity;architecture ha1 of ha isbegin

process (a,b)beginif (a ='0' and b='0') then

sum <= '0';carry<='0';

elsif( a='0' and b='1')thensum<= '1';carry<='0';

elsif( a='1' and b='0')thensum<= '1';carry<='0';elsif( a='1' and b='1')thensum<= '0';carry<='1';end if;

end process;end architecture;

--vhdl code for half subtractor using Behavioral style model.entity ha is

port( a, b: in bit; sum,borrow: out bit);end entity;architecture ha1 of ha isbegin

process (a,b)beginif (a ='0' and b='0') then

sum <= '0';borrow<='0';

elsif( a='0' and b='1')thensum<= '1';borrow<='1';

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elsif( a='1' and b='0')thensum<= '1';borrow<='0';elsif( a='1' and b='1')thensum<= '0';borrow<='0';end if;

end process;end architecture; --vhdl code for half subtractor using data flow style model.

entity ha isport( a, b: in bit; sum,borrow: out bit);

end entity;architecture ha1 of ha isbegin

sum<= a xor b;carry<= not a and b;end architecture;

--vhdl code for half-subtractor using structural style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity hs is port(

a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; borrow : out STD_LOGIC

);end hs;

architecture hs_stru of hs is component inv

port(u: in STD_LOGIC; v: out STD_LOGIC);end component;component xor2

port(l,m: in STD_LOGIC; n: out STD_LOGIC);

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end component; component and2

port(x,y: in STD_LOGIC; z: out STD_LOGIC);end component;for i1: inv use entity work.inv(inv);

for x1: xor2 use entity work.xor2(xor2);for a1: and2 use entity work.and2(and2);

signal nota: STD_LOGIC;begin i1:inv port map(a, nota);

x1: xor2 port map( a, b, sum);a1: and2 port map(nota,b,borrow);

end hs_stru;

--vhdl code for full-adder using Behavioral style model.entity fa is

port( a, b: in bit;carry: inout bit; sum: out bit);end entity;architecture fa1 of fa isbegin

process (a,b,carry)beginif (a ='0' and b='0'and carry='0') then

sum <= '0';carry<='0';

elsif(a ='0' and b='1'and carry='0') thensum <= '1';carry<='0';

elsif( a='1' and b='0'and carry = '0')thensum <= '1';carry <='0';elsif( a='1' and b='1'and carry= '0')thensum <= '0';carry <='1';elsif( a='0' and b='0'and carry= '1')thensum <= '1';carry <='0';elsif( a='0' and b='1'and carry= '1')thensum <= '0';

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carry <='1';elsif( a='1' and b='0'and carry= '1')thensum <= '0';carry <='1';elsif( a='1' and b='1'and carry= '1')thensum <= '1';carry <='1';

end if;end process;end architecture;

--vhdl code for full-adder using structural style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity fa is port(

a : in STD_LOGIC; b : in STD_LOGIC; c: in std_logic; sum : out STD_LOGIC; carry : out STD_LOGIC

);end fa;

architecture fa_stru of fa is component xor2

port( l,m:in std_logic;n: out std_logic);end component;component and2

port( x,y:in std_logic; z:out std_logic);end component;component or2

port (e,f: in std_logic; g: out std_logic);end component;for x1 : xor2 use entity work.xor2(xor2);

for x3: and2 use entity work.and2(and2);for x5: or2 use entity work.or2(or2);

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signal a1,a2,a3: std_logic;begin

x1: xor2 port map(a,b,a1);x2: xor2 port map ( a1,c,sum);x3: and2 port map (a,b,a2);x4: and2 port map (a1,c,a3);x5: or2 port map (a3,a2,carry);

end fa_stru;

--vhdl code for full-adder using data-flow model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity fa1 is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC

);end fa1;

architecture fa_data1 of fa1 isbegin

sum <= a xor b xor c;carry <= (a and b) or (c and (a xor b));end fa_data1;

--vhdl code for full-subtractor using data-flow model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity fs is port(

a : in STD_LOGIC;

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borrow<= '1'; elsif(a="011") then diff <= '0'; borrow<= '1'; elsif(a="100") then diff <= '1'; borrow<= '0'; elsif(a="101") then diff <= '0'; borrow<= '0'; elsif(a="110") then diff <= '0'; borrow<= '0'; elsif(a="111") then diff <= '1'; borrow<= '1'; end if; end process;

end fs_beh;

--vhdl code for full-Created by bsaitm btractor using structural style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity fsub is port(

a : in STD_LOGIC; b : in STD_LOGIC; c: in std_logic; diff : out STD_LOGIC; borrow : out STD_LOGIC

);end fsub;

architecture fs_str of fsub iscomponent xor2

port(l,m: in std_logic;n: out std_logic);end component;

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component and2port(x,y: in std_logic; z: out std_logic);

end component;component inv

port (u: in std_logic; v: out std_logic);end component;component or2

port(e,f: in std_logic; g: out std_logic);end component; for b1: xor2 use entity work.xor2(xor2);for b3: inv use entity work.inv(inv);for b5: and2 use entity work.and2(and2);for b7: or2 use entity work.or2(or2);signal q1,q2,q3,q4,q5: std_logic; begin

b1:xor2 port map ( a,b,q3);b2:xor2 port map ( q3,c,diff);b3:inv port map ( a,q1);b4:inv port map ( q3,q4);b5:and2 port map ( q1,b,q2);b6:and2 port map ( q4,c,q5);b7: or2 port map (q5,q2,borrow);

end fs_str;--vhdl code for B2G code converter using data-flow model.library IEEE;use IEEE.STD_LOGIC_1164.all;

entity b2g is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; w : out STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC

);

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end b2g;

architecture b2g_data of b2g isbegin

w<= a;x<= a xor b;y<= b xor c;z<= c xor d;

end b2g_data;

--vhdl code for B2G code converter using behavioral model.

entity b2g is port(

b : in STD_LOGIC_VECTOR(3 downto 0); g : out STD_LOGIC_VECTOR(3 downto 0)

);end b2g;

architecture b2g_beh of b2g isbegin

process (b)begin

case b iswhen "0000"=> g<="0000";when "0001"=> g<="0001";when "0010"=> g<="0011";when "0011"=> g<="0010";when "0100"=> g<="0110";when "0101"=> g<="0111";when "0110"=> g<="0101";when "0111"=> g<="0100";when "1000"=> g<="1100";when "1001"=> g<="1101";when "1010"=> g<="1111";when "1011"=> g<="1110";when "1100"=> g<="1010";

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when "1101"=> g<="1011";when "1110"=> g<="1001";when "1111"=> g<="1000";when others=> null;

end case;end process;end b2g_beh;

--vhdl code for B2G code converter using structural style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;entity b2g is

port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; w : out STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC

);end b2g;architecture b2g_stru of b2g is component xor2

port (l,m: in Std_logic; n: out std_logic);end component;component buff

port (u: in std_logic; v:out std_logic);end component;for x1: buff use entity work.buff(buff);

for x2: xor2 use entity work.xor2(xor2);begin

x1: buff port map (a,w);x2: xor2 port map (a,b,x);x3: xor2 port map (b,c,y);x4: xor2 port map (c,d,z);

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end b2g_stru;

--vhdl code for G2B code converter using data-flow model.library IEEE;use IEEE.STD_LOGIC_1164.all;

entity g2b is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; w : out STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC

);end g2b;architecture g2b_data of g2b isbegin

w <= a;x <= a xor b;y <= a xor b xor c;z <= a xor b xor c xor d;

end g2b_data;

--vhdl code for G2B code converter using behavioral model.

entity g2b is port(

g : in STD_LOGIC_VECTOR(3 downto 0); b : out STD_LOGIC_VECTOR(3 downto 0)

);end g2b;

architecture g2b_beh of g2b is

begin process (g)

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begincase b is

when "0000"=> b<="0000";when "0001"=> b<="0001";when "0011"=> b<="0010";when "0010"=> b<="0011";when "0110"=> b<="0100";when "0111"=> b<="0101";when "0101"=> b<="0110";when "0100"=> b<="0111";when "1100"=> b<="1000";when "1101"=> b<="1001";when "1111"=> b<="1010";when "1110"=> b<="1011";when "1010"=> b<="1100";when "1011"=> b<="1101";when "1001"=> b<="1110";when "1000"=> b<="1111";when others=> null;

end case;end process;

end g2b_beh;

--vhdl code for G2B code converter using structural style model.library IEEE;use IEEE.STD_LOGIC_1164.all;

entity g2b is port(

w : in STD_LOGIC; x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC

);end g2b;

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architecture g2b_stru of g2b is component xor2

port (l,m: in Std_logic; n: out std_logic);end component;component buff

port (u: in std_logic; v:out std_logic);end component;for x1: buff use entity work.buff(buff);

for x2: xor2 use entity work.xor2(xor2);begin

x1: buff port map (w,a);x2: xor2 port map (w,x,b);x3: xor2 port map (x,y,c);x4: xor2 port map (y,z,d);

end g2b_stru;

--vhdl code for Bcd27-segment code converter using data-flow model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity bcd_7 is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC; h : out STD_LOGIC; i : out STD_LOGIC; j : out STD_LOGIC; k : out STD_LOGIC

);end bcd_7;

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architecture bcd_7_data of bcd_7 isbegin

e<= a or ( c and d) or ( b and d) or (not b and not d);f<= not b or (not c and not d)or (c and d);g<= b or not c or d;h<= (not b and not d)or (c and not d)or (not b and c) or( b and not c and d);i<= (not b and not d)or ( c and not d);j<= a or (not c and not d)or (b and not c)or (b and not d);k<= a or (b and not c) or (c and not d)or (not b and c);

end bcd_7_data;

--vhdl code for Bcd2 7-segment code converter using behavioral model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity bcd_seven is port(

bcd : in STD_LOGIC_VECTOR(3 downto 0); segment : out STD_LOGIC_VECTOR(6 downto 0)

);end bcd_seven;

architecture bcd_beh of bcd_seven isbegin

process(bcd) begincase bcd iswhen "0000"=>segment<="1111110";when "0001"=>segment<="0110000";when "0010"=>segment<="1101101";when "0011"=>segment<="1111001";when "0100"=>segment<="0110011";when "0101"=>segment<="1011011";when "0110"=>segment<="0011111";when "0111"=>segment<="1110000";when "1000"=>segment<="1111111";when "1001"=>segment<="1110011";

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when others => null;end case;end process;end bcd_beh;

--vhdl code for Bcd2 7-segment code converter using structural style model.library IEEE;use IEEE.STD_LOGIC_1164.all;

entity bcd is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC; h : out STD_LOGIC; i : out STD_LOGIC; j : out STD_LOGIC; k : out STD_LOGIC

);end bcd;

architecture bcd_stru of bcd iscomponent or4

port(a1,a2,a3,a4: in std_logic; af:out std_logic);end component;component and2

port(x,y: in std_logic;z: out std_logic);end component;component and3

port(l,m,o:in std_logic;n : out std_logic);end component;component inv_1

port(e: in std_logic; f: out std_logic);end component;component or3

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port(k1,k2,k3: in std_logic;k4: out std_logic);end component;component or2

port (m1,m2: in std_logic;m3: out std_logic);end component;

for x1: or4 use entity work.or4(or4);for a1:and2 use entity work.and2(and2);for b1: and3 use entity work.and3(and3);for i1: inv_1 use entity work. inv_1(inv_1);for z1: or3 use entity work.or3(or3);for l1: or2 use entity work.or2(or2);signal n1,n2,n3: std_logic;signal b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12:std_logic;

begini1: inv_1 port map(b,n1);i2: inv_1 port map (c,n2);i3: inv_1 port map (d,n3);a1: and2 port map (c,d,b2);a2: and2 port map (b,d,b3);a3: and2 port map (n1,n3,b4);a4: and2 port map (n3,n2,b5);a5: and2 port map (n1,n3,b6);a6: and2 port map (c,n3,b7);a7: and2 port map (c,n1,b8);a8: and2 port map (b,n3,b9);a9: and2 port map (b,n2,b10);a10: and2 port map (n2,n3,b11);b1: and3 port map(b,n2,d,b12);x1: or4 port map (a,b2,b3,b4,e);z1:or3 port map (n1,b2,b5,f);z2:or3 port map (b,n2,d,g);x2:or4 port map (b6,b7,b8,b12,h);l1:or2 port map (b6,b7,i);x3:or4 port map (a,b9,b10,b11,j);x4:or4 port map (a,b7,b8,b10,k);

end bcd_stru;

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--vhdl code for Bcd-2-excess3 code converter using data-flow model.library IEEE;use IEEE.STD_LOGIC_1164.all;

entity bcd_3 is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; w : out STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC

);end bcd_3;

architecture bcd_xce3_data of bcd_3 isbegin

w<= a or ( b and c) or (b and d);x<= (not b and c)or (not b and d)or (b and not c and not d);y<=(c and d)or (not c and not d);z<= not d;

end bcd_xce3_data;

--vhdl code for Bcd-2-excess3 code converter using behavioral model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity bcd_excess is port(

b : in STD_LOGIC_VECTOR(3 downto 0); excess3 : out STD_LOGIC_VECTOR(3 downto 0)

);end bcd_excess;

architecture bcd_excess_beh of bcd_excess is

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beginprocess (b)begin

case b iswhen "0000"=>excess3<="0011"; when "0001"=>excess3<="0100";when "0010"=>excess3<="0101";when "0011"=>excess3<="0101";when "0100"=>excess3<="0111";when "0101"=>excess3<="1000";when "0110"=>excess3<="1001";when "0111"=>excess3<="1010";when "1000"=>excess3<="1011"; when "1001"=>excess3<="1100";when "1010"=>excess3<="1110"; when others => null;

end case;end process;

end bcd_excess_beh;

--vhdl code for Bcd-2-excess3 code converter using structural style model.library IEEE;use IEEE.STD_LOGIC_1164.all;

entity bcd_excess is port(

a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; w : out STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC

);end bcd_excess;

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architecture bcd_exces_stru of bcd_excess is component or2

port(m1,m2: in std_logic; m3: out std_logic);end component;component and2

port(x,y: in std_logic; z: out std_logic);end component;component inv_1

port(e: in std_logic; f: out std_logic);end component;for x1: or2 use entity work.or2(or2);for x5: inv_1 use entity work.inv_1(inv_1);for x8: and2 use entity and2(and2);signal a1,a2,a3,a4:std_logic;signal n1,n2,n3: std_logic ;begin

x1: or2 port map (a,a1,w);x2:or2 port map (a2,a3,x);x3:or2 port map (n2,a4,y);x4: or2 port map (c,d,n3);x5:inv_1 port map (d,z); x6:inv_1 port map (b,n1);x7:inv_1 port map (n3,n2);x8: and2 port map (b,n3,a1);x9: and2 port map (n1,n3,a2);x10: and2 port map (b,n2,a3);x11: and2 port map (c,d,a4);

end bcd_exces_stru;

--VHDL Code for decoder 2X4 using data flow model. library IEEE;use IEEE.STD_LOGIC_1164.all;

entity decoder2_4 is port(

s0 : in STD_LOGIC; s1 : in STD_LOGIC;

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en : in STD_LOGIC; z : out STD_LOGIC_VECTOR(3 downto 0)

);end decoder2_4;architecture decoder_data of decoder2_4 is signal s0bar,s1bar:std_logic;begin

s0bar<= not s0;s1bar<= not s1;z(3)<= s0bar and s1bar and en;z(2)<= s0bar and s1 and en;z(1)<= s0 and s1bar and en;z(0)<= s0 and s1 and en;

end decoder_data;

--VHDL Code for decoder 2X4 using behavioral model.library IEEE;use IEEE.STD_LOGIC_1164.all;entity decoder is

port( en : in STD_LOGIC; s0 : in STD_LOGIC; s1 : in STD_LOGIC; z : out STD_LOGIC_VECTOR(3 downto 0)

);end decoder;architecture decoder_beh of decoder isbegin

process(s0,s1,en)variable s0bar,s1bar: std_logic;begin

s0bar:= not s0;s1bar:= not s1;if (en='1')then

z(3)<= s0bar and s1bar;z(2)<=s0bar and s1;z(1)<= s0 and s1bar;z(0)<= s0 and s1;

elsez<="0000";

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end if;end process;

end decoder_beh;--VHDL Code for decoder 2X4 using structural style modellibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity decoder is

port( en : in STD_LOGIC; s0 : in STD_LOGIC; s1 : in STD_LOGIC; z : out STD_LOGIC_VECTOR(0 to 3)

);end decoder;

architecture decoder_stru of decoder is component and3

port(l,m,o:in std_logic; n: out std_logic);end component; component inv_1

port(e: in std_logic; f: out std_logic);end component;for x1: and3 use entity work.and3(and3);for x5: inv_1 use entity work.inv_1(inv_1);signal s0bar,s1bar: std_logic;

beginx1: and3 port map (s0bar,s1bar,en,z(0));x2: and3 port map (s0bar,s1,en,z(1));x3: and3 port map (s0,s1bar,en,z(2));x4: and3 port map (s0,s1,en,z(3));x5: inv_1 port map (s0,s0bar);x6: inv_1 port map (s1,s1bar);

end decoder_stru;

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--VHDL Code for encoder 8X3 using data flow model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity \encoder 8x3\ is port(

a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : in STD_LOGIC_VECTOR(0 to 7)

);end \encoder 8x3\;

architecture encoder_data of \encoder 7x3\ isbegin

a <= d(4)or d(5)or d(6)or d(7);b <= d(2) or d(3)or d(6) or d(7);c <=d(1) or d(3) or d(5) or d(7);

end encoder_data;

--VHDL Code for encoder 8X3 using behavioral model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity encoder is port(

d : in STD_LOGIC_VECTOR(0 to 7); a : out STD_LOGIC_vector(0 to 2 ) );

end encoder;

architecture encoder_beh of encoder is

begin process (d)begincase d is

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when "10000000"=> a<= "000";when "01000000"=> a<="001";when "00100000"=> a<="010";when "00010000"=> a<="011";when "00001000"=> a<="100";when "00000100"=> a<="101";when "00000010"=> a<="110";when "00000001"=> a<="111";when others => null;

end case;end process;

end encoder_beh;--VHDL Code for parity encoder 8X3 using structural style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity encoder is port(

d : in STD_LOGIC_VECTOR(0 to 3); a : out STD_LOGIC_VECTOR(0 to 1); en: out std_logic

);end encoder;

architecture encoder_stru of encoder iscomponent or2

port(m1,m2: in std_logic; m3: out std_logic);end component;component or3

port (k1,k2,k3: in std_logic;k4: out std_logic);end component; component and2

port(x,y: in std_logic; z: out std_logic);end component;component inv

port (u: in std_logic; v: out std_logic);end component;for x1:or2 use entity work.or2(or2);

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for x3: or3 use entity work.or3(or3);for x4: and2 use entity work.and2(and2);for x5:inv use entity work.inv(inv);signal a1,a2,a3:std_logic; beginx1: or2 port map (d(3),a2,a(1));x2: or2 port map (d(3),d(2),a(0));x3: or3 port map (a3,d(1),d(0),en);x4: and2 port map (a1,d(1),a2);x5: inv port map ( d(2),a1);end encoder_stru;

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--VHDL Code for parity generator using behavioral model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity parity is port(

d : in STD_LOGIC_VECTOR(3 downto 0); par_even : out STD_LOGIC; par_odd : out STD_LOGIC);

end parity;architecture parity of parity isbegin

p1:process(d)begin

case d iswhen "0000"=> par_even<='0';par_odd<='1';when "0001"=> par_even<='1'; par_odd<='0';when "0010"=> par_even<='1'; par_odd<='0';when "0011"=> par_even<='0'; par_odd<='1';when "0100"=> par_even<='1'; par_odd<='0';when "0101"=> par_even<='0'; par_odd<='1';when "0110"=> par_even<='0'; par_odd<='1';when "0111"=> par_even<='1'; par_odd<='0';when "1000"=> par_even<='1'; par_odd<='0';when "1001"=> par_even<='0'; par_odd<='1';when "1010"=> par_even<='0'; par_odd<='1';when "1011"=> par_even<='1'; par_odd<='0';when "1100"=> par_even<='0'; par_odd<='1';when "1101"=> par_even<='1'; par_odd<='0';when "1110"=> par_even<='1'; par_odd<='0';when "1111"=> par_even<='0'; par_odd<='1';when others=> null;

end case;end process;

end parity;

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--VHDL Code for parity generator using data flow model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity parity_gen_data is port(

d0 : in STD_LOGIC; d1 : in STD_LOGIC; d2 : in STD_LOGIC; d3 : in STD_LOGIC; parity_even : inout STD_LOGIC; parity_odd : out STD_LOGIC

);end parity_gen_data;

--}} End of automatically maintained section

architecture parity_gen_data of parity_gen_data is

signal d4,d5: std_logic;begin

d4 <= d0 xor d1;d5 <= d4 xor d2;parity_even <= d5 xor d3;parity_odd <= not parity_even;

end parity_gen_data;

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--VHDL Code for parity generator using structural style model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity parity_gen_stru is port(

d0 : in STD_LOGIC; d1 : in STD_LOGIC; d2 : in STD_LOGIC; d3 : in STD_LOGIC; parity_even : inout STD_LOGIC; parity_odd : out STD_LOGIC

);end parity_gen_stru;

--}} End of automatically maintained section

architecture parity_gen_stru of parity_gen_stru is component xor2

port(a,b: in std_logic; c: out std_logic);end component;component inv

port (i: in std_logic; j: out std_logic);end component;for x1: xor2 use entity work.xor2(xor2);

for i1: inv use entity work.inv(inv);

signal d4,d5: std_logic;begin

x1: xor2 port map (d0,d1,d4);x2: xor2 port map (d4,d2,d5);x3: xor2 port map (d5,d3,parity_even);i1: inv port map (parity_even ,parity_odd);

end parity_gen_stru;

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--VHDL Code for parity checker(even-parity) using data flow model.

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity perity_checker is port(

d3 : in STD_LOGIC; d2 : in STD_LOGIC; d1 : in STD_LOGIC; d0 : in STD_LOGIC; parity_even : in STD_LOGIC; parity_even_checker : out STD_LOGIC

);end perity_checker;

--}} End of automatically maintained section

architecture perity_checker of perity_checker issignal d4,d5,d6: std_logic;begin

d4 <= d3 xor d2;d5<= d4 xor d1;d6<= d5 xor d0;parity_even_checker <= d6 xor parity_even;

-- enter your statements here --

end perity_checker;

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