An All CMOS 743MHz Variable Gain Amplifierfor UWB Systems

Quoc-Hoang Duong, Student Member, IEEE, T.-J. Park, E.-J. Kim, and Sang-Gug Lee, Member, IEEE

Information and Communications University119-Mujro, Daejeon, Republic of Korea, 305-714.

ABSTRACT- A newly proposed variable gain amplifier respectively [3, 5, 7]. Owing to the limitation of the gain(VGA) that offers wide bandwidth and gain variation range in recent researches, the multiple-stage VGAs arecharacteristics is described for ultra wideband system used to satisfy the required dynamic gain range ofapplications. The proposed VGA combines a cascade- communication systems (for example; to satisfy 60dB ofinput stage and bandwidth-extension loads to obtain a the gain variation range, 3 gain stages for signal-summingwide bandwidth. The VGA is simulated in 0.13tm CMOS and master-slave control techniques, 4 gain stages fortechnology and simulations show a gain variation range of pseudo-exponential generator VGA, and 5 gain stages for54dB in a single-stage VGA and a minimum 1-dB Taylor concept approach must be used). Obviously, thebandwidth of743MHz at the maximum gain of 20dB. The multistage VGAs result in a high power consumption and1-dB bandwidth improvement of 58% compared to a large chip size (or high cost), which is not compatibleconventional VGAs at the same supply current is obtained. with low-voltage low-power small-chip size portable radioIn addition, the newly proposed control stage results in a transceiver integrated circuit.compact VGA, which leads to low power consumption. Due to the limitation of the gain variation range inThe VGA dissipates an average supply current of 4.5mA conventional VGA designs, a new approximation functionfrom 1.8V supply voltage. that can provide a wider dB-linear variation range has

been introduced in [8]. However, the previously reportedKeywords: Variable gain amplifier (VGA), automatic gain works show limited bandwidth at a high gain setting [5, 7,control (AGC), amplifier, UWB 8, 9, 10]. Consequently, these VGA designs can be

implemented in narrow band application only.I. INTRODUCTION In this paper, the new VGA topology with bandwidth

enhancement techniques is proposed. The gain of theVariable gain amplifier (VGA) is an indispensable proposed VGA is the same form of expression as in [8]

block at the front end of many communication systems to such that a wide variation range VGA is obtained. Themaximize the dynamic range of the receivers. VGAs are proposed VGA is compact, which leads to low-poweralso used in the transmitter part of communication consumption.transceivers to control the transmission signal power. TheVGA is usually embedded in an automatic gain control II. CONVENTIONAL VGA DESIGNSamplifier (AGC) loops to provide constant output signalamplitudes regardless of variations in the input signal. The conventional VGA topology that is widely used in

Recently, many approaches to achieve dB-linear gain previously reported works is depicted in Fig. 1 [5, 7, 8, 9,variation characteristics of the VGA in CMOS technology 10]. As shown in Fig. 1, the core of the VGA consists of ahave been reported; such as master-slave control [1] and differential amplifier (M12) and diode-connected loadssignal-summing techniques [2], or using Taylor concept (M3,4). The differential gain of this VGA is equal[3] and pseudo-exponential generator [4, 5, 7, 9, 10] for to gm,_2 X Rou where gm-M1,2 is the transconductancerealizing the dB-linear gain characteristic. The signal- Mhe i ut'summing VGA has the advantages of high frequency of the input differential pair andRion is the outputoperation, low-noise, and low-distortion; but the gain impedance. Sinceathe output is diode-connected loads,tRhecontrol range of the one-stage VGA is limited to less than is proportional to l/gm-M3,4, where gm-M3,4 is the20 dB and the gain error is large [2]. The master-slave transconductance of the loads (M34). Since thecontrol technique has a gain variation range of less than transconductance is a function of the bias current, the gain20dB per one-stage VGA [2]. The VGAs that adopt the variation is obtained by control the bias currents of theTaylor concept and the pseudo-exponential generator input-pair (Ml 2) and loads (M3,4). The gain of the VGAeven exhibits less amount of gain control range, which is shown in Fig. 1 iS given as12 and 15dB with a gain error of less than ±0.5dB,

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4 (WI L)M M implemented in applications limited to 40MHz. AsX=gm Ml,2 - (WI L)Ml, 'M3,4 (1) . reported in [9], the cascade input stage was also adopted;gm-A13,4 (WI L)M3,4 IM3,4

Considering the frequency response of the circuit VDDshown in Fig. 1, the bandwidth of the VGA is dominatedby the input and output poles. Since the output loads arediode-connected transistors, the output pole is mainly V'.tdependent on the bias current of the transistors M3,4. At a .,E,lower gain setting, IM3,4 and the bandwidth are extended. * .t+

However, at a higher gain setting, IM3,4 is reduced, leadingto a reduction of the bandwidth [8]. The input pole is a D 2 M1 M2 -a M3 M4function of input capacitances. In Fig. 1, the total kj +lcapacitances at the input node of M1 is equal to CGS plusthe Miller multiplication of CGD: CGS + (1±+ IAI)CGD,where CGS and CGD are gate-source and gate-draincapacitances of transistor M1, A, is given in (1).Consequently, the input pole is proportional to the gain A,such that the bandwidth is reduced significantly at highergain settings; for example, reference [8] shows a max/min

3-dB bandwidth of 1G/40M at.theminimumand Fig. 1 Schematic of the core pseudo-exponential3-dB bandwidth of IGHz/40MHz at the minimum andaprxmto-aeVGs[,7 910]* * * 1 1 r . . app~~aroximation-based VGAs [5 7 8 9 10]maximum gains, respectively. Therefore, [8] can only be '[

,-----------------_-VDD

MlM2 M~~~~~~~~~~~~~~~~~V1/17 N/I8

'BIAS fz t CMFB |Bandwidth extension load- vZloadL

IZ;O'ftjC2vazut M7 L> M 8 | vou/t _+

VBIAS D- 4 -C M10

D+%nI+ MlW W in - Vte.f CAM2 BEC- M, I M2 1 1 .

Cascode stage _ - Control stage

VCTRLD VCTRL-D--JM15 IO O 1

|- - Variable gain circuit - *| [4 Common-mode feedback circuit -*Fig. 2 The complete schematic of the newly proposed VGA

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however, the gain of the input different pair remains high, bandwidth. The load Zo given in (2) and shown in Fig. 3so that no reduction of the Miller multiplication is realized by the solid line leads to the shift of the dash-dotted line tosuch that the input pole reduces the bandwidth at higher the dash-dot-dotted line, which provides additionalgain settings significantly. bandwidth improvement.

In Fig. 2, the control stage is newly proposed with aIII. NEWLY PROPOSED VGA TOPOLOGY differential control signal, VCTRL+ = VBJAS + VCTRL and

VCTRLJ VBJAS - VCTRL, where VBJAS is a bias voltage andThe newly proposed circuit schematic of the VGA is VCTRL the differential control voltage. Transistors M15 and

illustrated in Fig. 2, which is composed of a variable gain M16 are biased in saturation mode. The bias currents ofthecircuit and a common-mode feedback circuit. The input pair (M11,14) and loads (M12,13) are respectivelyvariable gain circuit utilizes a cascade input stage and a given asbandwidth extension loads for bandwidth improvements. l

C +VCTRL WVh +I0In Fig. 2, due to the cascade input stage, by setting the IM411,14 = n(3)size of Mg equally to M1l, the gain from the gate to drain 2 o0 Lterminals of transistor Ml, is equal to gmmll/gm-mg = 1, I- C (-{V -V -V )2 + I (4therefore the Miller multiplication is minimized so that M12,13-2 L CTRL h 0the input capacitances reaches the smallest value. where Vth is the threshold voltages of NMOS transistorsConsequently, the input pole is moved to a higher M1516, Io the bias current. From (1), (3), and (4), the gainfrequency, leading to a wider bandwidth. of the proposed VGA shown in Fig. 2 is given as

m 1 M2 'gmMA412,13 (W!/ L)M1213 I4'12,13: I + X Cl I : M3 1FAssuming that (W/L)Mj1 l4= (W/L)M11,14, from (3), (4), and

(5), the gain of the proposed VGA is calculated as

Bandwidth extension load AI c't i (V -v V)+ Iol I _ < lU~~~~~~~~~~~~~~~~~~~~nCo,BIAS CTRL Vth O\_________________' Zpoj - IL

2 1/2Zl,.dA Due toZo | I +I1+ VCR AIK(VBIASth )2 VBIAS iVth

Due to cascode I/\input stage and ZO IO°I +1 VCTRL

K(VBS-1h)Y VBVS h ) )Inutouu Input-output Pole /2

Ptou \ " due to cascode input k+(+X2 (6)Fig. 3 Bandwidth extension due to cascade input stage where k Io/K(VBJAs - Vth) 1(a = I(VBAS- Vth), and Kand bandwidth extension loads. /in C0xW/2L. As reported in [8], the proposed VGA can

In Fig. 2, the load impedance is equal to ZO//ZM13 -Z. achieved 60dB gain variation for k 0.15.From [9], the input impedance of the bandwidth extension IV. SIMULATION RESULTSloads can be given as

Z ~1 (1+ s ) (2) The proposed VGA is simulated in 0.13gm CMOSz0 = gmMMlc )2 technology and dissipates 4.5mA from the supply voltageof 1.8V. Fig. 4 shows the simulated gain versus control

Equation (2) shows a "zero" at the output node, leading to voltage VCTRL at 100MHz. As expected, the proposedthe extension of the bandwidth. The summary of the VGA shows a verywide gain variation range of 54dB.bandwidth extension techniques is depicted in Fig. 3. In To verify the validity of the bandwidth enhancementFig. 3, the conventional VGAs is depicted by the dashed techniques, two VGAs are designed; one with cascadeline, by utilizing the cascade input stage, the dashed line input stage and bandwidth extension loads and the otheris moved to the dash-dotted line, resulting in a wider (the conventional one) without any bandwidth enhance-

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ment techniques at the same supply current. Fig. 5 shows TABLE I. SUMMARY OF SIMULATION RESULTSthe frequency response of the proposed VGA and theconventional one at different gain settings. As shown in Conventional ProposedFig. 5 by the dashed lines, at a high gain mode, the VGA VGAbandwidth of the conventional VGA is reduced. The 1- Technology 0.13tm 0.13tmdB bandwidths of the conventional VGA (dashed line)and the proposed VGA (solid line) at a gain of 20dB are Power 4.5mA/1.8V 4.5mA/1.8Vrespectively 470 and 743MHz. The bandwidth consumptionimprovement of 58% compared to the conventional one bandwidth 470MHz 743MHzis achieved, while dissipating the same bias current.

The comparisons of the proposed VGA with the Gain range -34-20dB -34dB 20dBconventional one is given in Table. 1. Gain error ±0.5dB ±0.5dB

30 ACKNOWLEGENMENT

20

/0 This work was supported by SAMSUNG ELECTRO-10 MECHIANICS CO., LTD under the SRC/ERC program

0 o / ofMOST/KOSEF (Intelligent Radio Engineering Center).SAMSUNG ELECTRO-MEC1ANICS CO., LTD. 314,

-10/Maetan3-Dong, Yeongtong-Gu, Suwon, Gyunggi-Do,-20 Korea 443-743.

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