Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Real-time data sparsification of...

Vertex 2008 conference, July 27thVertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Swede-August 1st 2008 Gruvbyn, Swedenn

Real-time data Real-time data sparsification of MAPS sparsification of MAPS

detectors for HEP detectors for HEP experiments and beyondexperiments and beyond

Marcin Jastrzab (Como University, AGH Krakow) Marcin Jastrzab (Como University, AGH Krakow) Angelo Cotta Ramusino (INFN Ferrara) Angelo Cotta Ramusino (INFN Ferrara)

Massimo Caccia (Como University, INFN Milano)Massimo Caccia (Como University, INFN Milano)Antonio Bulgheroni (INFN Milano) et al.Antonio Bulgheroni (INFN Milano) et al.

[email protected]


OutlineOutline

Motivation for data sparsificationMotivation for data sparsification Solutions for sparsification implementationSolutions for sparsification implementation Monolithic Silicon Pixel Detectors – MAPSMonolithic Silicon Pixel Detectors – MAPS DAQ applicationsDAQ applications DAQ system architectureDAQ system architecture Preliminary resultsPreliminary results Future plansFuture plans


Motivation for data Motivation for data sparsificationsparsification

High data rate from the state-of-the-art silicon sensorsHigh data rate from the state-of-the-art silicon sensors High granularity - large number of sensor channels to be readoutHigh granularity - large number of sensor channels to be readout Low sensor occupancy often non exceeding a few %Low sensor occupancy often non exceeding a few %

As an example let us consider the pixel sensor being readout @ 40MHz frequency. In many cases the sensor area is divided by 4 quadrants (columns) As an example let us consider the pixel sensor being readout @ 40MHz frequency. In many cases the sensor area is divided by 4 quadrants (columns) readout in parallel to increase the readout speed and reduce the integration time. In such a case the bandwidth necessary to transfer of the data is readout in parallel to increase the readout speed and reduce the integration time. In such a case the bandwidth necessary to transfer of the data is ~320MB/s for one detector only!~320MB/s for one detector only!

The most popular The most popular interfaces characteristicsinterfaces characteristics:: Ethernet: 1Gbit/s (125MB/s), 10Gbit/s (1.25GB/s)Ethernet: 1Gbit/s (125MB/s), 10Gbit/s (1.25GB/s) VME 64x: up to 160MB/sVME 64x: up to 160MB/s USB 2.0: 60MB/sUSB 2.0: 60MB/s FireWire 800: 100MB/sFireWire 800: 100MB/s


Motivation for data Motivation for data sparsificationsparsification

Sparsification offers the Sparsification offers the possibility to avoid the possibility to avoid the overhead and run at the overhead and run at the full speed without dead-full speed without dead-time.time.

Data storage volume Data storage volume becomes much less becomes much less important issue.important issue.

Instead of using equipment Instead of using equipment computer farm, the data is computer farm, the data is being reducedbeing reduced at the DAQ at the DAQ level.level.


Computer farm on-line sparse data Computer farm on-line sparse data identificationidentification

DAQ based sparse DAQ based sparse data recognitiondata recognition – – hardware (Atlas DAQ, EUDRB (EUDET project))hardware (Atlas DAQ, EUDRB (EUDET project))

On-chip implementation (SUZE-01 On-chip implementation (SUZE-01 (IPHC/Strasbourg), Deep N-well 130nm (IPHC/Strasbourg), Deep N-well 130nm (Pavia,Bergamo,Pisa,Bologna) – token (Pavia,Bergamo,Pisa,Bologna) – token architecture by R. Yarema (FNAL).architecture by R. Yarema (FNAL).

Sparsification – possible Sparsification – possible solutionssolutions

Basically there are 3 feasibile solution for Basically there are 3 feasibile solution for sparsification algorithm implementationsparsification algorithm implementation


MAPS – Monolithic Active Pixel MAPS – Monolithic Active Pixel SensorsSensors

Sparsification is not simple. Especially because Sparsification is not simple. Especially because algorithm results, reduced data volume and high algorithm results, reduced data volume and high speed have not to affect the quality of the recorded speed have not to affect the quality of the recorded information.information.

The sensor used in The sensor used in thethe measurements is a Mimosameasurements is a Mimosa 5 5 CMOS by LEPSICMOS by LEPSI (IPHC (IPHC Strasbourg)Strasbourg)..The charge carrier generated The charge carrier generated in the epitaxial layer 15 in the epitaxial layer 15 m m thick - signal (~80 e-h thick - signal (~80 e-h pairs/pairs/m).m).

MAPS in CMOS technology has been pioneered in LEPSI in the late 90’s


MAPS – Monolithic Active Pixel MAPS – Monolithic Active Pixel SensorsSensors

The charge collection The charge collection mechanism mechanism in CMOS MAPS in CMOS MAPS sensors sensors is based on is based on thethediffusion diffusion mechanism. Tmechanism. The sensitive he sensitive volume is not depleted and volume is not depleted and charge cluster spreads over ~ 50 charge cluster spreads over ~ 50 m.m.

Detector pixel sizeDetector pixel size for Mimosa 5 for Mimosa 5 sensorsensor = 17 = 17 m.m.

Collected charge vs. No of pixels in cluster


DAQ applicationsDAQ applicationsThe DAQ system based on the The DAQ system based on the

Altera FPGA chip (EUDRB) is Altera FPGA chip (EUDRB) is being used in the EUDET ILC being used in the EUDET ILC project (see the details on the project (see the details on the subsequent slides and the subsequent slides and the EUDET presentation). EUDET presentation).

EUDRB is a base DAQ systemEUDRB is a base DAQ systemfor the EUDET telescope for the EUDET telescope composed of 6 planes for high composed of 6 planes for high precision particle tracking.precision particle tracking.

The zero suppresion mechanism The zero suppresion mechanism has been implemented for has been implemented for MimoStar2, MimoTel and MimoStar2, MimoTel and Mimosa18 sensor. Mimosa18 sensor.

The result obtained at DESY in August 2007

Eudet telescope


DAQ applicationsDAQ applications

Tritium samples imaging Tritium samples imaging with Mimosa 5 sensor with Mimosa 5 sensor has been done using has been done using Sucima Imager DAQ Sucima Imager DAQ system, developed system, developed during Sucima EU during Sucima EU project. project.

Tritium imaging relies on Tritium imaging relies on single particle single particle interaction measurement interaction measurement and 10and 105-5-101066 frames are to frames are to be collected to obtain be collected to obtain good quality image. good quality image.

Seed pixel signal distribution

Ring 3 (3x3 crown) signal distribution


DAQ applicationsDAQ applications

Image of the RPA506 standard acquired with the MIMOSA5 sensor over a 2 hours exposure time

Ring 5 (5x5 crown) signal distribution


DAQ (EUDRB) ArchitectureDAQ (EUDRB) ArchitectureThe EUDET Data Reduction board was developed at INFN-The EUDET Data Reduction board was developed at INFN-Ferrara inFerrara in collaboration with University of Insubria-Como and collaboration with University of Insubria-Como and INFN-Roma 3 to INFN-Roma 3 to read outread out Monolithic Active Pixel Sensors (MAPS).Monolithic Active Pixel Sensors (MAPS). EUDRB is EUDRB is based on based on ALTERA CycloneIIALTERA CycloneII FPGA FPGA chip chip (clock rate: 80MHz)(clock rate: 80MHz).. Two readout modes:Two readout modes:Zero SuppressedZero Suppressed readout to minimize the readout to minimize the readout dead-time while readout dead-time while in normal data taking.in normal data taking.Non Zero SuppressedNon Zero Suppressed readout of multiple readout of multiple frames for debugging or frames for debugging or off-line pedestal and off-line pedestal and noise calculationsnoise calculationsThe EUDRB has been so The EUDRB has been so farfar employed with the employed with the IPHC MIMOSA-5, IPHC MIMOSA-5, MIMOSTAR 2 andMIMOSTAR 2 and MIMOTelMIMOTel devices.devices.


DAQ (EUDRB) ArchitectureDAQ (EUDRB) ArchitectureThe FPGA handles the operations related to data collection, The FPGA handles the operations related to data collection, trigger servicing and I/Otrigger servicing and I/O port interfacing with sequencers and port interfacing with sequencers and logic blocks described in VHDL code or schematiclogic blocks described in VHDL code or schematic diagrams.diagrams.

Ovierview of Data Flow for ZS operation of EUDRB


DAQ (EUDRB) ArchitectureDAQ (EUDRB) ArchitectureEUDRB performs in ZS mode fetching of “hit” data without EUDRB performs in ZS mode fetching of “hit” data without stopping detector scan and frame buffer update. Four firmware stopping detector scan and frame buffer update. Four firmware submodules perform the “hit”extraction in parallel (CDS and submodules perform the “hit”extraction in parallel (CDS and comparison with threshold after perdestal subtraction), one for comparison with threshold after perdestal subtraction), one for each submatrix).each submatrix).This processor controls local FIFOs to store hit information until This processor controls local FIFOs to store hit information until the output FIFO is available for receiving a new event data the output FIFO is available for receiving a new event data packet. The event data packet contains “hit” signal amplitude packet. The event data packet contains “hit” signal amplitude and pixel address encompassed within a Header and a Trailer.and pixel address encompassed within a Header and a Trailer.

EUDRB contains EUDRB contains NIOS II, 32 bit “soft” NIOS II, 32 bit “soft” microcontroller (clock rate: 40Mz) implemented microcontroller (clock rate: 40Mz) implemented in the FPGA forin the FPGA for „ „on board diagnosticson board diagnostics” and ” and remote configuration of the FPGA via RS-232, remote configuration of the FPGA via RS-232, VME, USB2.0VME, USB2.0


EUDRB Cluster Search ZS EUDRB Cluster Search ZS ArchitectureArchitecture

The Cluster Search algorithm has been implemented into the The Cluster Search algorithm has been implemented into the EUDRB DAQ using VHDL code. EUDRB DAQ using VHDL code. The EUDRB equipment as a external FIFO memory together with The EUDRB equipment as a external FIFO memory together with the NIOS II processor external memory are the necesessary for the NIOS II processor external memory are the necesessary for the seed driven cluster search algorithm.the seed driven cluster search algorithm.

The architecture of the ZS firmware is build in such a way that The architecture of the ZS firmware is build in such a way that the cluster search is being done during the current detector the cluster search is being done during the current detector readout and the data memory is being updated for four quarters readout and the data memory is being updated for four quarters independently. In the same time, the pixels hit (clusters) during independently. In the same time, the pixels hit (clusters) during the previous readout is being transfered to the output FIFO buffer the previous readout is being transfered to the output FIFO buffer to be sent out to the storage.to be sent out to the storage.

The visualization of the implemented mechanism is shown on the The visualization of the implemented mechanism is shown on the next slide.next slide.


Seed pixel

address FIFO

Cluster builder3x3 or 5x5

pixels

Current framePrevious frame Noise Pedestal

DATA MEMORY

DETECTOR MATRIX scan N

Single DATA MEMORY cell

CLUSTER PIXEL FLAG MEMORY

DETECTOR MATRIX scan N+1

DATA MEMORY – FLAG MEMORY ADDRESS BUS

OUTPUT FIFO MEMORYSIGNAL?

DATA MEMORY

EUDRB Cluster Search ZS EUDRB Cluster Search ZS mechanismmechanism


Cluster Search ZS preliminary Cluster Search ZS preliminary resultsresults

The Cluster Search algorithm is being commissioned The Cluster Search algorithm is being commissioned and the very and the very preliminary results has been obtained. The mesaurements with IR preliminary results has been obtained. The mesaurements with IR laser, laser, 33H samples and the test beam is foreseen.H samples and the test beam is foreseen.

Test setup with PLS 500 Picoquant, fast LED head system has been performed.

PLS 500 – signal frequency 1MHz, emmiting power 7,8μW


Future plansFuture plans Algorithm qualification with IR laser and Algorithm qualification with IR laser and 33H H

Amersham standardsAmersham standards Pedestal and noise update implementationPedestal and noise update implementation Hot pixels on-line masking implementationHot pixels on-line masking implementation Test beam – Mimosa 5 as a DUTTest beam – Mimosa 5 as a DUT

Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Real-time data sparsification of...

Documents

Transcript of Vertex 2008 conference, July 27th-August 1st 2008 Gruvbyn, Sweden Real-time data sparsification of...