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Summary of Key Verilog Features (IEEE 1364)

ModuleEncapsulates functionality; may be nested to any depth

module m od ul e n am e ( l i s t o f p o r t s ) ;// D e c l a r a t i o n s Port modes : input , output , inout i d e n t i f i e r ;Nets ( e . g . , wire A [ 3 : 0 ] ; )R e g i s t e r v a r i a b l e ( e . g . , re g B[ 3 1 : 0 ] ; )Constants : ( e . g . , parameter s i z e =8 ; )Named eve nt sC o n ti n u o us a s s i g n m e n ts ( e . g . assign sum = A + B ; )B e h a v i o r s always ( c y c l i c ) , i n i t i a l ( s i n g l e pas s )s p e c i f y . . . endspecifyfunction . . . endfunctiontask . . . endtask// I n s t a n t i a t i o n s

p r i m i t i v e smodulesendmodule

Multi-Input Primitives

and ( o u t , i n1 , i n2 , . . . , inN ) ;

nand ( o ut , i n1 , i n2 , . . . , inN ) ;or ( o ut , i n1 , i n2 , . . . , inN ) ;nor ( o u t , i n1 , i n2 , . . . , inN ) ;xor ( o u t , i n1 , i n2 , . . . , inN ) ;xnor ( o ut , i n1 , i n2 , . . . , inN ) ;

Three-State Multioutput Primitivesbuf ( o u t 1 , o ut 2 , . . . , outN , i n ) ; // b u f f e r not ( o u t 1 , o ut 2 , . . . , outN , i n ) ; // i n v e r t e r

Written by Zafar M. Takhirov and Schuyler Eldridge, ICSG@BU

Three-State Multioutput Primitivesb u f i f 0 ( o ut , i n , c o n t r o l ) ; b u f i f 1 ( o ut , i n , c o n t r o l ) ;n o t i f 0 ( o ut , i n , c o n t r o l ) ; n o t i f 1 ( o ut , i n , c o n t r o l ) ;

Pullups and Pulldowns

pullup ( o u t y ) ; pulldown ( o u t y ) ;

Propagation DelaysS i n g l e d e l a y : and #3 G1 ( y , a , b , c ) ;Ri se / f a l l : and # (3 , 6) G2 ( y , a , b , c ) ;Rise / f a l l / tu rn of f : b u f i f 0 # ( 3 , 6 , 5 ) ( y , x i n , e n ) ;Min : typ : Max: b u f i f 1 # ( 3: 4: 5 , 4 : 5 : 6 , 7 : 8 : 9 )

( y , x i n , en ) ;

Command line options for single delay value simulation: +maxdelays, +typde-lays, +mindelays

Concurrent Behavioral StatementsMay execute a level-sensitive assignment of value to a net (keyword: assign), ormay execute the statements of a cyclic (keyword: always) or single-pass (key-

word:initial) behavior. The statements execute sequentially, subject to level-sensitive or edge-sensitive event control expressions.

Syntax

assign n et n am e = [ e x p r e s s i o n ] ;always begin [ p r o c e d u r a l s t a t e m e n t s ] endi n i t i a l begin [ p r e c e d u r a l s t a t e m e n t s ] end

Cyclic(always) and single-pass (initial) behaviors may be level sensitive and/or

edge sensitive

Edge sensitive

always @ ( posedge c l o c k )q

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Level sensitive

always @ ( e n a b l e or d a t a )q y ) = 2 ; // s t a t e dep( posedge c l k => ( y : d i n ) ) = ( 3 , 4 ) ; / / e d g e

endspecify

Example: Timing Checkss p e c i f y

specparam t s e t up = 3 : 4 : 5 , t h o l d = 4 : 5 : 6 ;$ s e t u p ( d a t a , posedge c l oc k , t s e t u p ) ;$ ho ld ( posedge c l oc k , da ta , t h o l d ) ;

endspecify

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MemoryDeclares an array of words.

Example: Memory declaration and readout

module m e m o ry r e a d d i s p l a y ( ) ;re g [ 3 1 : 0 ] mem array [ 1 : 1 0 2 4 ] ;

integer k ;i n i t i a l beg in

// r ea d c o n t e n t s o f mem a rray f ro m // a f i l e i n h ex f o rm a t $readmemh( mem contents . dat , mem array ) ;// d i s p l a y c o n t en t s o f mem array f o r ( k = 1 ; k

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Example:

module o r m o d el ( y , a , b ) ;output y ;input a , b ; i f d e f c o n t a s s i g n

// u s e s c o n ti n u ou s a s si g nm e nt

assign y = a | b ; e l s e

or G1 ( y , a , b ) ; // u se s p r i m i t iv e e n d i f

endmodule

Simulation Output

$display ( s t r i n g o f i n f o %d , v a r i ab l e ) ;integer K;i n i t i a l K = $fopen ( o u t p u t f i l e ) ;always @ ( e v e n t c o n t r o l e x p r e s si o n ) // dump databegin

$fdisplay (K, %h , dat a [ 7 : 0 ] ) ;. . .$ f c l o s e ( o u t p u t f i l e ) ;

$monitor ( $time , out 1=%b , out 2=%b , out 1 , out 2 ) ;$monitor (K, so me va lu e=%h , ad dr es s [ 1 5 : 0 ] ) ;$monitoron ;$monitoroff;

end

Simulation Data Control

i n i t i a l begin/ / d ump s i m u l a t i o n d a t a i n t o m y da ta . dump :$du mpf ile ( my data .dump ) ;/ / dump a l l s i g n a l s :$dumpvars ;// dump v a r i a b l e s i n m od ul e t o p :$dumpvars (1 , top ) ;/ / dump v a r i a b l e s 2 l e v e l s b e l o w t o p . mod1 :$dumpvars(2 , top .mod1);// s t o p dump a f t e r 1000 t im e u n i t s :#1000 $dumpoff ;// s t a r t / r e s t a r t dump a f t e r 500 t im e u n i t s :#500 $dumpon ;// s u sp e nd s i m u l a t i o n :$stop ;

// t e rm i na t e s i m u la t i o n a f t e r 1000 t im e u n i t s :#1000 $ f i n i s h ;

end

Parameter Redefinition

In-line (instance-based)module Something ( ) ;

parameter s i z e = 4 ;parameter w i d t h = 8 ;. . .

endmodule. . .S o me thi n g # (8 , 3 2 ) M1 ( ) ;. . .

Indirect (hierarchical dereferencing):module Annotate ( ) ;

. . .defparam . Something . width = 16 ;. . .

endmodule

Constructs to Avoid in Synthesis time, real, realtime variables named event triand, trior, tri0, tri1 nets vector ranges for integers single-pass (initial) behavior

assign ... deassign procedural continuous assignment force ... release procedural continuous assignment fork ... join block (parallel activity flow) defparam parameter substitution Operators: Modulus(%) and Division(/), except for division by 2 ===, !=== Primitives: pullup, pulldown, tranif0, tranif1, rtran, rtranif0, rtranif1 Hierarchical pathnames Compiler directives

This material is used while creating the current document:

1. IEEE 1364 Verilog-2001 Standard description.2. Advanced Digital Design with the Verilog HDL by Michael D.

Ciletti