verilog implementation of Gaussion Random Number Generator using boxmuller method ,full verilog Code
VERILOG CODE FOR CODE CONVERTERS
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![Page 1: VERILOG CODE FOR CODE CONVERTERS](https://reader030.fdocuments.in/reader030/viewer/2022013118/55cf986a550346d033977d09/html5/thumbnails/1.jpg)
Aim : To write a program in verilog to implement digital code converters (binary to
gray,gray to binary and BCD to gray).
Description :
Digital code converters are used to convert digital code from one format to another.The code may be in
binary,gray,BCD format.We only represent numbers from (0-9) in binary into BCD code and it will be
simply their binary representation.While in case of gray code,MSB of binary code of any decimal number is
kept same and on moving to right bit is added with its previous bit (or doing xor operation).In this case carry
is neglected and the resulting sequence is known as gray code for an decimal number.
Gray code is a binary numeral system where two successive values differ in only one bit.
Code for (binary to gray) code conversion :
module bin_gry(B, G);
input [3:0] B;
output [3:0] G;
reg [3:0]G;
always@(B)
begin
case(B)
4'h0:G=4'h0;
4'h1:G=4'h1;
4'h2:G=4'h3;
4'h3:G=4'h2;
4'h4:G=4'h6;
4'h5:G=4'h7;
4'h6:G=4'h5;
4'h7:G=4'h4;
4'h8:G=4'hC;
4'h9:G=4'hD;
4'hA:G=4'hF;
4'hB:G=4'hE;
4'hC:G=4'hA;
4'hD:G=4'hB;
4'hE:G=4'h9;
4'hF:G=4'h8;
endcase
end
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endmodule
Test fixture code:
module bin_gyr_txt_v;
// Inputs
reg [3:0] B;
// Outputs
wire [3:0] G;
// Instantiate the Unit Under Test (UUT)
bin_gry uut (
.B(B),
.G(G)
);
initial begin
// Initialize Inputs
B=4'h0;
#60;
B=4'h1;
#60;
B=4'h2;
#60;
B=4'h3;
#60;
B=4'h4;
#60;
B=4'h5;
#60;
B=4'h6;
#60;
B=4'h7;
#60;
B=4'h8;
#60;
B=4'h9;
#60; // TIME DELAY
B=4'hA;
#60;
B=4'hB;
#60;
B=4'hC;
#60;
B=4'hD;
#60;
B=4'hE;
#60;
B=4'hF;
#60;
$stop;
// Add stimulus here
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end
endmodule
RTL Schematic for (binary to gray) code conversion :
Simulation Result for ( binary to gray) code conversion :
Code for (gray to binary) code conversion :
module gray_binary(g, b);
input [3:0] g;
output [3:0] b;
reg [3:0]b;
always@(g)
begin
b[3]=g[3];
b[2]=b[3]^g[2];
b[1]=b[2]^g[1];
b[0]=b[1]^g[0];
end
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endmodule
RTL Schematic for (gray to binary) code conversion :
Simulation Result for (gray to binary) code conversion :
Code for (BCD to gray) code conversion :
module bcd_gry(BCD, G);
input [3:0] BCD;
output [3:0] G;
reg [3:0]G;
always@(BCD)
begin
G[3]=BCD[3];
G[2]=BCD[3]^BCD[2];
G[1]=BCD[2]^BCD[1];
G[0]=BCD[1]^BCD[0];
end
endmodule
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Test fixture code:
initial begin
BCD=4'b0000;
#100;
BCD=4'b0001;
#100;
BCD=4'b0010;
#100;
BCD=4'b0011;
#100;
BCD=4'b0100;
#100;
BCD=4'b0101;
#100;
BCD=4'b0110;
#100;
BCD=4'b01110;
#100;
BCD=4'b1000;
#100;
BCD=4'b1001;
#100;
$stop;
end
Simulation Result for (BCD to gray) code conversion :