Verilog Code for Basic Logic Gates

EX. NO: 1 DATE:

IMPLEMENTATION OF BASIC LOGIC GATES IN FPGA

AIM: To design, synthesize, simulate, implement and program the basic logic gates in FPGA.

TOOLS REQUIRED: SOFTWARE:

XILINX ISE 9.1iHARDWARE:

XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, GPIO card - II

ALGORITHM:1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.5. Write the functionality of the gates.6. Terminate the program.

THEORY:

AND GATE:The AND gate performs logical multiplication which is most commonly known as

the AND junction. The operation of AND gate is such that the output is high only when all its inputs are high and when any one of the inputs is low the output is low.

Y = a & bOR GATE:

The OR gate performs logical addition which is most commonly known as the OR junction. The operation of OR gate is such that the output is high only when any one of its input is high and when both the inputs are low the output is low.

Y = a | bNOT GATE:

The Inverter performs a basic logic gate function called Inversion or Complementation. The purpose of an inverter is to change one logic level to opposite level. When a high level is applied top an inverter, the low level will appear at the output and vice versa.

Y = ~a

NAND GATE:The term NAND is derived from the complement of AND. It implies the AND

junction with an inverted output. The operation of NAND gate is such that the output is low only when all its inputs are high and when any one of the inputs is low the output is high.

Y = ~(a & b)

1

NOR GATE:The term NOR is derived from the complement of OR. It implies the OR junction

with an inverted output. The operation of NOR gate is such that the output is high only when all its inputs are low and when any one of the inputs is high the output is low.

Y = ~(a | b)EX-OR GATE:

The output is high only when the inputs are at opposite level.Y = a ^ b

EX-NOR GATE:The output is high only when the inputs are at same level.

Y = ~(a ^ b)

PROGRAM:

Verilog Code for basic logic gates

module allgates(A, B, not1, or2, and3, nor4, nand5, xor6, xnor7);input A;input B;output not1;output or2;output and3;output nor4;output nand5;output xor6;output xnor7;

reg not1;reg or2;reg and3;reg nor4;reg nand5;reg xor6;reg xnor7;

always@(A or B)begin

not1 = ~ A;or2 = A | B;and3 = A & B;nor4 = ~ (A | B);nand5 = ~ (A & B);xor6 = (A ^ B);xnor7 = ~ (A ^ B);

end

endmodule

2

UCF file (User constraint file)

NET "A" LOC = "p34" ;NET "and3" LOC = "p61" ;NET "B" LOC = "p35" ;NET "nand5" LOC = "p62" ;NET "nor4" LOC = "p63" ;NET "not1" LOC = "p64" ;NET "or2" LOC = "p65" ;NET "xnor7" LOC = "p66" ;NET "xor6" LOC = "p67" ;

PROCEDURE:

Software part

1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module.3. Check syntax, view RTL schematic and note the device utilization summary by

double clicking on the synthesis in the process window.4. Perform the functional simulation using Xilinx ISE simulator.5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.6. Implement the design by double clicking on the implementation tool selection.7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part

1. Connect the power supply cable to the FPGA kit using power supply adapter.2. Connect FPGA board to parallel port of PC using parallel port cable.3. Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC

cable.4. Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC

cable.

3

RTL Schematic Representation – Top Level

RTL Schematic Representation – Gate Level

4

SIMULATION REPORT:

TRUTH TABLE:

RESULT:Thus the basic logic gates were designed using Verilog HDL and it was simulated,

synthesized, implemented and programmed in the FPGA device.

5

Input Output

A B not1 or2 and3 nor4 nand5 xor6 xnor7

0 0 1 0 0 1 1 0 1

0 1 1 1 0 0 1 1 0

1 0 0 1 0 0 1 1 0

1 1 0 1 1 0 0 0 1

EX. NO: 2DATE:

IMPLEMENTATION OF HALF ADDER IN FPGA

AIM:

To design, synthesize, simulate, implement and program the Half Adder in FPGA.

TOOLS REQUIRED:

SOFTWARE:XILINX ISE 9.1i

HARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, GPIO card - II

ALGORITHM:

1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.5. Terminate the program.

THEORY:

HALF ADDER:

The half adder consists of two input variables designated as Augends and Addend bits. Output variables produce the Sum and Carry. The ‘carry’ output is 1 only when both inputs are 1 and ,sum’ is 1 if any one input is 1. The Boolean expression is given by, sum = x ^ y

carry = x & y

6

PROGRAM:

Verilog code for half adder

module halfadder(a, b, sum, carry);

input a;input b;output sum;output carry;

reg sum,carry; always@(a or b)

begin sum=a^b;

carry=a&b; end

endmodule


NET "a" LOC = "p34" ;NET "b" LOC = "p35" ;NET "carry" LOC = "p61" ;NET "sum" LOC = "p62" ;

7

PROCEDURE:

Software part



Hardware part



cable.


8


SIMULATION REPORT

9

TRUTH TABLE:

Input Output

A B sum carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

RESULT:

Thus the half adder is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

10

EX. NO: 3 DATE:

IMPLEMENTATION OF FULL ADDER IN FPGA

AIM:

To design, synthesize, simulate, implement and program Full adder in FPGA.

TOOLS REQUIRED:



ALGORITHM:

1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog

code.5. Terminate the program.

THEORY:

FULL ADDER:

A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. It consists of 3 inputs and 2 outputs. The third input is the carry from the previous Lower Significant Position. The two outputs are designated as Sum (S) and Carry (C). The binary variable S gives the value of the LSB of the Sum. The output S=1 only if odd number of 1’s are present in the input and the output C=1 if two or three inputs are 1.

sum = x ^ y ^ zcarry= (x & y) | (y & z) | (x & z)

11

PROGRAM:

Verilog code for full adder

module fulladder(a, b, cin, sum, cout);

input a;input b;input cin;output sum;output cout;

reg sum,cout;

always@(a or b or cin)

begin sum=a^b^cin;

cout=(a&b)|(b&cin)|(cin&a); end

endmodule


NET "a" LOC = "p34" ;NET "b" LOC = "p35" ;NET "cin" LOC = "p61" ;NET "cout" LOC = "p62" ;NET "sum" LOC = "p63" ;

12

PROCEDURE:

Software part



Hardware part



cable.


13


SIMULATION REPORT

14

TRUTH TABLE:

RESULT:

Thus the full adder is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. NO: 4

15

Input Output

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

DATE:

IMPLEMENTATION OF HALF SUBTRACTOR IN FPGA

AIM:

To design, synthesize, simulate, implement, and program the Half subtractor in FPGA.

TOOLS REQUIRED:


HARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, GPIO card – II

ALGORITHM:

1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog


THEORY:

HALF SUBRACTOR:

The Half subtractor consist of two input variables, the output variables produce the Difference (d) and Borrow (bo). The output ‘bo’ is 1 only when the input ‘a’ is at low level and other input ‘b’ is at higher level. The output ‘d’ is 1 only when only one of the inputs is 1. The Boolean expression for half subtractor is given by,

d = a ^ bbo = a’b

PROGRAM:

16

Verilog code for Half subtractor:

module Halfsub (i0,i1,bor,dif);output bor, dif;input i0,i1;wire ion;not(ion,i0);xor(dif,i0,i1);and(bor,ion,i1);endmodule

UCF file(User constraint file)

NET "i0" LOC = "p34" ;NET "i1" LOC = "p35" ;NET "dif" LOC = "p61" ;NET "bor" LOC = "p62" ;

PROCEDURE:

17

Software part

1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC.

2. Draw the half subtractor and full subtractor circuit by choosing schematic as top

level source module.

3. Check syntax, view RTL schematic and note the device utilization summary by

double clicking on the synthesis in the process window.

4. Perform the functional simulation using Xilinx ISE simulator.

5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.

6. Implement the design by double clicking on the implementation tool selection.

7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part

1. Connect the power supply cable to the FPGA kit using power supply adapter.

2. Connect FPGA board to parallel port of PC using parallel port cable.

3. Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC

cable.

4. Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC

cable.


18


19

SIMULATION REPORT:

TRUTH TABLE:

Input Output

i0 i1 diff bor

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

RESULT:

Thus the half subtractor is designed using schematic entry and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. NO: 5

20

DATE:

IMPLEMENTATION OF FULL SUBTRACTOR IN FPGA

AIM:

To design full subtractor using schematic entry and to synthesize, simulate, implement the same in FPGA.

TOOLS REQUIRED:



THEORY:

FULL SUBTRACTOR:

A full subtractor is a multiple output combinational logical network which performs a subtraction between two binary bits considering that a ‘1’ might have been borrowed by a lower significant stage. Along with the minuend ‘a’ and the subtrahend ‘b’, the third input is the borrow bit ‘c’, from the previous stage of subtraction. The combinational logic network of the full subtractor thus has three inputs and two outputs. The two outputs produced are the difference bit output‘d’ and a final borrow ‘bo’ respectively. The Boolean expression for full subtractor is given by,

d = a ^ b ^ c bo = a’b + a’c + bc

PROCEDURE:

21

Software part


2. Draw the half subtractor and full subtractor circuit by choosing schematic as top

level source module.

3. Check syntax, view RTL schematic and note the device utilization summary by

double clicking on the synthesis in the process window.

4. Perform the functional simulation using Xilinx ISE simulator.

5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.

6. Implement the design by double clicking on the implementation tool selection.

7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part

1. Connect the power supply cable to the FPGA kit using power supply adapter.

2. Connect FPGA board to parallel port of PC using parallel port cable.

3. Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC

cable.

4. Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC

cable.

22

PROGRAM:

Verilog code for full subtractor

module fullsub (b_in,i1,i0,b_out,dif);

input b_in;input i1;input i0;output b_out;output dif;wire x,y,z,w,v;xor ( x,b_in,i1);xor (dif,x,i0);not (y,x);not (w,b_in);and (z,y,i0);and (v,w,i1);or(b_out,,z,v);

endmodule


NET "b_in" LOC = "p34" ;NET "i0" LOC = "p35" ;NET "i1" LOC = "p36" ;NET "diff" LOC = "p62" ;NET "b_out" LOC = "p63" ;

23



24

SIMULATION REPORT: (FOR FULL SUBTRACTOR)

TRUTH TABLE:

RESULT:

Thus the full subtractor is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

25

Input Output

b_in i0 i1 dif bor

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

EX. NO: 6 DATE:

IMPLEMENTATION OF 4:1 MUX IN FPGA

AIM:To design, synthesize, simulate, implement and program 4:1 multiplexer in FPGA.

TOOLS REQUIRED:



ALGORITHM:1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.5. Terminate the program.

THEORY:

MULTIPLEXER

A Multiplexer is a Combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The set of selection of a particular line is controlled by selection lines. Normally there are 2n input lines and n selection lines whose bit combinations determine which input is selected.

The 4:1 MUX has four inputs I0, I1, I2 and I3 and select lines S0 and S1. The select lines s0 and s1 are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the one line output Y.

26

PROGRAM:

Verilog code for 4 to 1 Multiplexer

module mux(en, a, y,sel);

input en;input [3:0] a;input[1:0] sel;output y;

reg y;

always@(en or a)

beginif(!en)y=1'b0;else case(sel)

2'b00 : y = a[3];2'b01 : y = a[2];2'b10 : y = a[1];2'b11 : y = a[0];

endcase

end

endmodule


NET "a[0]" LOC = "p34" ;NET "a[1]" LOC = "p35" ;NET "a[2]" LOC = "p36" ;NET "a[3]" LOC = "p37" ;NET "en" LOC = "p38";NET "sel[0]" LOC = "p39" ;NET "sel[1]" LOC = "p40" ;NET "y" LOC = "p61";

27

PROCEDURE:

Software part



Hardware part



cable.


28


SIMULATION REPORT:

29

TRUTH TABLE:

RESULT:

Thus the 4:1 mux is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

30

Select lines output

Sel[0] Sel[1] y

0 0 a[0]

0 1 a[1]

1 0 a[2]

1 1 a[3]

EX. NO: 7 DATE:

IMPLEMENTATION OF 1:4 DEMUX IN FPGA

AIM:To design, synthesize, simulate, implement and program 1:4 demultiplexer in

FPGA.

TOOLS REQUIRED:



ALGORITHM:1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog


THEORY:

DEMULTIPLEXER

A Demultiplexer is a Combinational circuit that selects binary information from one of input line and directs it to many output line. The set of selection of a particular output is controlled by selection lines. Normally there are 1 input line and 2n selection lines whose bit combinations determine the output.

The 1:4 DEMUX has one input and select lines S0 and S1. The select lines s0 and s1 are decoded to select a particular AND gate. The outputs of the AND gates provides the various line output Y1, Y2, Y3 and Y4.

31

PROGRAM:

Verilog code for 1 to 4 Demultiplexer

module demux(a, en, y, sel);

input a;input en;output [3:0] y;input [1:0] sel;

reg [3:0]y;

always@(a or en)

beginif(!en)y = 4'b0000;elsecase(sel)

2'b00 : beginy[3]=a;y[2:0]=3'b0;end

2'b01 : beginy[2]=a;y[3]=1'b0;y[1:0]=2'b0;end

2'b10 : beginy[1]=a;y[3:2]=2'b0;y[0]=1'b0;end

2'b11 : beginy[0]=a;y[3:1]=3'b0;end

endcase

end

endmodule

32


NET "a" LOC = "p34" ;NET "en" LOC = "p35" ;NET "sel[0]" LOC = "p36" ;NET "sel[1]" LOC = "p37" ;NET "y[0]" LOC = "p61" ;NET "y[1]" LOC = "p62" ;NET "y[2]" LOC = "p63" ;NET "y[3]" LOC = "p64" ;

PROCEDURE:

Software part



Hardware part



cable.

33



34

SIMULATION REPORT:

TRUTH TABLE:

STATUS OUTPUTS

a S0 S1 Y3 Y2 Y1 Y0

a[0] 0 0 0 0 0 1

a[1] 0 1 0 0 1 0

a[2] 1 0 0 1 0 0

a[3] 1 1 1 0 0 0

RESULT:

35

Thus the 1:4 demux is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. NO: 8 DATE:

IMPLEMENTATION OF ENCODER IN FPGA

AIM: To design, synthesize, simulate, implement and program the encoder in FPGA.

TOOLS REQUIRED:




THEORY:

ENCODER

An Encoder is a digital circuit that has 2n (or fewer) input lines and n output lines. The output lines generate the binary the binary code corresponding to the input value. In encoder it is assumed that only one input has a value of 1 at any given time.

36

PROGRAM:

Verilog code for Encoder

module encoder(a, en, y);

input [3:0] a;input en;output [1:0] y;

reg[1:0] y;

always@(en or a)

beginif (!en)y = 2'b0;elsecase (a)

4'b0001 : y = 2'b00;4'b0010 : y = 2'b01;4'b0100 : y = 2'b10;4'b1000 : y = 2'b11;

endcase

end

endmodule


NET "a[3]" LOC = "p34" ;NET "a[2]" LOC = "p35" ;NET "a[1]" LOC = "p36" ;NET "a[0]" LOC = "p37" ;NET "en" LOC = "p38" ;NET "y[0]" LOC = "p61" ;NET "y[1]" LOC = "p62" ;

37

PROCEDURE:

Software part



Hardware part



cable.


38


SIMULATION REPORT: (FOR ENCODER)

39

TRUTH TABLE:

Input Output

en a[3] a[2] a[1] a[0] y[1] y[0]

1 0 0 0 1 0 0

1 0 0 1 0 0 1

1 0 1 0 0 1 0

1 1 0 0 0 1 1

RESULT:

Thus the encoder is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

40

EX. NO: 9 DATE:

IMPLEMENTATION OF DECODER IN FPGA

AIM: To design, synthesize, simulate, implement and program the decoder in FPGA.

TOOLS REQUIRED:




THEORY:

DECODER

Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is capable of representing up to 2n distinct elements of coded information. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n bit coded information unused combinations. The decoder may have fewer than 2n outputs.

The decoder are also called ‘n’ to ‘m’ line decoders, where is less than or equal to 2n. Their purpose is to generate the 2n (or fewer) minterms of input variables. The name decoder is also used in conjunction with other code converters such as BCD to SEVEN SEGMENT decoder.

41

PROGRAM:

Verilog code for Decoder

module decoder(a, en, y);

input[1:0] a;input en;output[3:0] y;

reg[3:0] y;

always@(en or a)

beginif(!en)y= 4'b0000;elsecase(a)

2'b00 : y = 4'b0001;2'b01 : y = 4'b0010;2'b10 : y = 4'b0100;2'b11 : y = 4'b1000;default :y = 4'b0000;

endcase

end

endmodule


NET "a[0]" LOC = "p34" ;NET "a[1]" LOC = "p35" ;NET "en" LOC = "p36" ;NET "y[0]" LOC = "p61" ;NET "y[1]" LOC = "p62" ;NET "y[2]" LOC = "p63" ;NET "y[3]" LOC = "p64" ;

42

PROCEDURE:

Software part


2. Write the Verilog code by choosing HDL as top level source module.3. Check syntax, view RTL schematic and note the device utilization summary by


Hardware part

8. Connect the power supply cable to the FPGA kit using power supply adapter.9. Connect FPGA board to parallel port of PC using parallel port cable.10. Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using

FRC cable.11. Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using

FRC cable.


43


SIMULATION REPORT: (FOR DECODER)

44

TRUTH TABLE:

INPUTS OUTPUTS

E a[0] a[1] Y[3] Y[2] Y[1] Y[0]

0 X X 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

RESULT:

Thus the decoder is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

45

EX. NO: 10 DATE:

IMPLEMENTATION OF 4 – BIT COUNTER IN FPGA

AIM:

To design, synthesize, simulate, implement and program the 4 – bit counter in FPGA.

TOOLS REQUIRED:



ALGORITHM:


THEORY:

4 - BIT COUNTER

This is a device for counter operation. It consists of a single user Flip Flop and a 3 bit Asynchronous Counter. This arrangement is for flexibility. Synchronous ones can also be used. It can be used as Module 8 Counter using only the 3 bit counter operation portion. It also provides gate reset inputs. This done can be configured as a decode counter by asynchronous recycling by using the gate reset inputs for the partial decoding.

46

PROCEDURE

Software part


double clicking on the synthesis in the process window.4. Perform the functional simulation using ModelSim XE simulator.5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.6. Implement the design by double clicking on the implementation tool selection.7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part



cable.

47

PROGRAM:Verilog code for 4-bit counter

module counter(clk, reset, count);input clk;input reset;output [3:0] count;reg[3:0] count;integer timer_count1 = 0,timer_count2 = 0;reg clk_msec,clk_sec;

always@(posedge clk)begin

if(timer_count1==3999)begin

timer_count1=0;clk_msec=1'b1;

endelsebegin

timer_count1=timer_count1+1;clk_msec=1'b0;

endendalways@(posedge clk_msec)begin

if(timer_count2==999)begin

timer_count2=0;clk_sec=1'b1;

endelsebegin

timer_count2=timer_count2+1;clk_sec=1'b0;

endendalways@(posedge clk_sec)begin

if(~reset)count = 4'b0000;

elsecount = count+1;

endendmodule

48


NET "clk" LOC = "p34";NET "count[0]" LOC = "p61" ;NET "count[1]" LOC = "p62" ;NET "count[2]" LOC = "p63" ;NET "count[3]" LOC = "p64" ;NET "reset" LOC = "p35";



49

SIMULATION REPORT:

50

RESULT:

Thus the 4 – bit counter were designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. NO: 11 DATE:

IMPLEMENTATION OF D –FLIP FLOP IN FPGA

AIM:

To design, synthesize, simulate, implement and program the D- Flip flop in FPGA.

TOOLS REQUIRED:


HARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card - I

ALGORITHM:

1. Start the program.2. Declare the input and output variables3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog


51

THEORY:

The D-flipflop has only a single data input. That data input is connected to the S input of an RS-flip flop, while the inverse of D is connected to the R input. This prevents that the input combination ever occurs. To allow the flipflop to be in a holding state, a D-flip flop has a second input called “Enable”. The Enable-input is AND-ed with the D-input, such that when Enable=0, the R and S inputs of the RS-flip flop are 0 and the state is held. When the Enable-input is 1, the S input of the RS flipflop equals the D input and R is the inverse of D. Hence, the value of D determines the value of the output Q when Enable is 1. When Enable returns to 0, the most recent input D is “remembered”.

PROCEDURE

Software part



Hardware part



cable.

PROGRAM:

Verilog code for D-Flip Flop

module dflipflop(data,clk,reset,q);

52

input data, clk, reset;output q;reg q;

always @ (postage clk)

if(~reset) begin q<=1’b0;end

else beginq<=data;end

endmodule

UCF file (User constraint file):

NET "data” LOC = "p34" ;

NET "clk" LOC = "p35";

NET "reset” LOC = "p36" ;

NET "q" LOC = "p63";

OUTPUT:

RTL S chematic Representation Top-Level:

53

RTL S chematic Representation Gate-Level:

SIMULATION REPORT:

54

TRUTH TABLE:

RESULT:

Thus the D-flip flop is designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. NO: 12 DATE:

IMPLEMENTATION OF MULTIPLIER IN FPGA

AIM: To design, synthesize, simulate pipelined multiplier to multiply two 8 bit signed numbers and to implement and program the same in FPGA.

55

Input Ouput

Clk d q

1 0 0

1 1 1

TOOLS REQUIRED:


HARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card – I

ALGORITHM:


THEORY:

A multiplier that accepts two 8-bit numbers in digital form and gives their product in the same digital form, usually by making repeated additions; the multiplying process is simpler if the numbers are in binary form wherein digits are represented by a 0 or 1.

PROCEDURE

Software part


2. Write the Verilog code by choosing HDL as top level source module.3. Check syntax, view RTL schematic and note the device utilization summary by


56

Hardware part



cable.

PROGRAM:

Verilog code for multiplier:

module mul(p,x,y); output [15:0]p;input [7:0]x,y; reg [15:0]p;reg [15:0]a;integer i;

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always @(x , y)begin a=x; p=0; // needs to zeroed for(i=0;i<8;i=i+1) begin if(y[i]) p=p+a; // must be a blocking assignment a=a<<1; end

end

endmodule

UCF file (User constraint file):

NET "x[0]” LOC = "p34" ;NET "x[1]" LOC = "p35";NET "x[2]” LOC = "p36" ;NET "x[3]” LOC = "p37" ;NET "x[4]" LOC = "p38";NET "x[5]” LOC = "p39" ;NET "x[6]” LOC = "p40" ;NET "x[7]" LOC = "p41";

NET "y[0]" LOC = "p42";

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NET "y[1]” LOC = "p43" ;NET "y[2]" LOC = "p44"; NET "y[3]" LOC = "p45";NET "y[4]” LOC = "p46" ;NET "y[5]" LOC = "p47";NET "y[6]" LOC = "p48";NET "y[7]” LOC = "p49" ;

NET "p[0]" LOC = "p61";NET "p[1]" LOC = "p62";NET "p[2]" LOC = "p63";NET "p[3]" LOC = "p64";NET "p[4]" LOC = "p65";NET "p[5]" LOC = "p66";NET "p[6]" LOC = "p67";NET "p[7]" LOC = "p68";NET "p[8]" LOC = "p69";NET "p[9]" LOC = "p70";NET "p[10]" LOC = "p71";NET "p[11]" LOC = "p72";NET "p[12]" LOC = "p73";NET "p[13]" LOC = "p74";NET "p[14]" LOC = "p75";NET "p[15]" LOC = "p76";


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SIMULATION REPORT: (Using ModelSim)

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RESULT:

Thus the 8 – bit multiplier was designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. NO: 13 DATE:

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DESIGN AND TESTING ONBOARD SWITCHES AND LED’S IN FPGA

AIM:

To simulate and test onboard switches and LED’s using Verilog code and to implement the same in FPGA.

TOOLS REQUIRED:



ALGORITHM:


THEORY:

TESTING ON BOARD LED’S AND SWITCHES:

XC3S400 is an array of Configurable Logic Blocks (CLB’s) and is embedded within a set of horizontal and vertical channels that contain Routing that can be personalized to interconnect CLB’s. The configuration of the interconnect is achieved by turning ON ‘n’ channel pass transistors. The state that determines a given interconnect pattern is held in the Static RAM cells distributed across the chip close to the controlled elements. The CLB’s and routing channels are surrounded by a set of programmable Inputs / Outputs.

PROGRAM:

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Verilog Code for Testing Onboard Switches and LEDs in FPGA

module buffer(a, y);

input [7:0] a;output [7:0] y;reg [7:0]y;

always@(a)begin

y=a;end

endmodule


NET "a[0]" LOC = "p34" ;NET "a[1]" LOC = "p35" ;NET "a[2]" LOC = "p36" ;NET "a[3]" LOC = "p37" ;NET "a[4]" LOC = "p38" ;NET "a[5]" LOC = "p39" ;NET "a[6]" LOC = "p40" ;NET "a[7]" LOC = "p41" ;NET "y[0]" LOC = "p61" ;NET "y[1]" LOC = "p62" ;NET "y[2]" LOC = "p63" ;NET "y[3]" LOC = "p64" ;NET "y[4]" LOC = "p65" ;NET "y[5]" LOC = "p66" ;NET "y[6]" LOC = "p67" ;NET "y[7]" LOC = "p68" ;

PROCEDURE:

Software part

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Hardware part



cable.

RTL Schematic Representation

SIMULATION REPORT:

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RESULT:

Thus the on board switches and LEDs were designed using Verilog HDL and it was simulated and tested in the FPGA device.

JNN INSTITUTE OF ENGINEERING

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Approved by AICTE, Affiliated to Anna University- Chennai

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

COMPUTER NETWORKS LABORATORY –EC2356

NAME : REG NO :

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JNN INSTITUTE OF ENGINEERINGMANAGEG BY: ALAMELU AMMAL EDUCATIONAL TRUST

Ushaa Garden, No 90, kannigaipair Village, Uttukottaitaluk – 601 102,Thiruvallur Dist. Tamilnadu. Ph: 27629613 WWW.jnnie.in

LABORATORY RECORD ELECTRONICS & COMMUNICATION ENGINEERING 2011-2012

This is to certify that bonafide record of practical work done by Mr./Ms

……………………………Register Number …………………………………….. of the

year ………….…………. B.E. Department of

………………………………………………………………………………………………

……………………………………..in

the…………………………………………………….………………………….laboratory

for the ………………………………………. Semester.

University Examination held on …………………….

Staff-in-charge Head of the Department

Internal Examiner External Examiner

CERTIFICATE

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Verilog Code for Basic Logic Gates

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