Verilog and test bench code for flipflops
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Transcript of Verilog and test bench code for flipflops
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1.Verilog Code for SR Flipflop
module sr_ff(clk,reset,s,r,q,qb);
parameter HOLD=2'b00,
SET=2'b10,RESET=2'b01,INVALID=2'b11;
input clk,reset,s,r;
output reg q;output qb;
always@(posedge clk or posedge reset )begin
if(reset)q
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// Step 3. Understand the clock generation logic
initialbegin
clk = 1'b0;forever#(cycle/2) clk=~clk;
end
//Step 4. Write a task to reset dut
task rst_dut();begin
reset=1'b1;
#10;reset=1'b0;end
endtask
//Step 5. write a task to send input combinations.
task din(input x,y);begin
@(negedge clk);s=x;
r=y;end
endtask
//Step 6. Run the test bench and assign inputs
initialbegin
rst_dut;din(0,0);
din(0,1);din(1,0);din(1,1);din(1,0);din(0,0);din(0,1);din(1,1);din(0,1);#10;$finish;
End
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// Step 4. Use $monitor to display the various inputs and outputs in batch mode
initial$monitor("clk=%b,Input-> SR =%b%b, Reset = %b, Output-> Q =%b, Qbar=%b",clk,s,r,reset,q,qb);
endmodule
2.Verilog Code for JK Flipflop
module jk_ff(clk,reset,j,k,q,qb);
parameter HOLD=2'b00,SET=2'b10,RESET=2'b01,
TOGGLE=2'b11;
input clk,reset,j,k;
output reg q;output qb;
always@(posedge clk or posedge reset )begin
if(reset)
q
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// Step 1. Define a parameter with name "cycle" which is equal to 10
parameter cycle=10;
// Step 2. Instantiate the sr_ff design
jk_ff JK1 (clk,reset,j,k,q,qb);
// Step 3. Understand the clock generation logic
initialbegin
clk = 1'b0;forever
#(cycle/2) clk=~clk;end
//Step 4. Write a task to reset dut
task rst_dut();begin
reset=1'b1;#10;reset=1'b0;
endendtask
//Step 5. write a task to send input combinations.
task din(input x,y);begin
@(negedge clk);j=x;k=y;
end
endtask
//Step 6. Run the test bench and assign inputs
initialbegin
rst_dut;din(0,0);din(0,1);din(1,0);
din(1,1);din(1,0);
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din(0,0);din(0,1);din(1,1);din(0,1);#10;
$finish;end
// Step 7. Use $monitor to display the various inputs and outputs in batch mode
initial$monitor("clk=%b, Input ->JK=%b%b, Reset = %b, Output ->Q =%b, Qbar=%b",clk,j,k,reset,q,qb);
endmodule
3. Verilog Code for D Flipflop:
module d_ff(clk,reset,d,q,qb);
input clk,reset,d;output reg q;output qb;
always@(posedge clk or posedge reset)begin
if(reset)begin
q
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// Step 2. Instantiate the dff design
d_ff D1 (clk,reset,d,q,qb);
// Step 3. Understand the clock generation logic
alwaysbegin
clk = 1'b0;#(cycle/2)clk=1'b1;#(cycle/2);
end
//Step 4. Write a task to reset dut
task rst_dut();begin
reset=1'b1;#10;reset=1'b0;
endendtask
//Step 5. write a task to send input combination.
task din(input i);begin
@(negedge clk);d=i;
endendtask
//Step 6. Run the test bench and assign inputs
initialbegin
rst_dut;din(0);din(1);din(0);din(1);din(1);rst_dut;din(0);din(1);
#10;$finish;
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end
// Step 5. Use $monitor to display the various inputs and outputs
initial
$monitor("clk=%b,Input D = %b, Reset = %b, Output q =%b, ~q=%b",clk,d, reset,q,qb);
endmodule
4. Verilog Code for MS Flipflop (using D Latch)
Module d_latch (en,d,q);
Input en d;
Output reg q;
always@(*)
begin
if(en)
begin
q=d;
end
end
endmodule
module ms_ff (clk,d,q,qb);
input clk,d;
output q,qb;
wire w1;
d_latch MASTER (~clk,d,w1);
d_latch SLAVE (clk,w1,q);
assign qb=~q;
endmodule
Test Bench Code for MS Flipflop
module ms_ff_tb();
reg clk,d;wire q,qb;
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// Step 1. Define a parameter with name "cycle" which is equal to 10
parameter cycle=10;
// Step 2. Instantiate the dff design
ms_ff MS1 (clk,d,q,qb);
// Step 3. Understand the clock generation logic
alwaysbegin
clk = 1'b0;#(cycle/2)clk=1'b1;
#(cycle/2);end
//Step 4. write a task to send input combination.
task din(input i);begin
@(negedge clk);d=i;
endendtask
//Step 5. Run the test bench and assign inputs
initialbegin
din(0);din(1);din(0);din(1);din(1);
din(0);din(1);#10;$finish;
End
// Step 6. Use $monitor to display the various inputs and outputs
initial
$monitor("clk=%b,Input D = %b,Output q =%b, ~q=%b",clk,d,q,qb);
endmodule
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5. Verilog code for T Flipflop:
module t_ff(clk,reset,t,q,qb);
parameter HOLD=1'b0,
TOGGLE=1'b1;
input clk,reset,t;output reg q;output qb;
always@(posedge clk or posedge reset)begin
if(reset)begin
q
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// Step 1. Define a parameter with name "cycle" which is equal to 10
parameter cycle=10;
// Step 2. Instantiate the dff design
t_ff T1 (clk,reset,t,q,qb);
// Step 3. Understand the clock generation logic
alwaysbegin
clk = 1'b0;#(cycle/2)clk=1'b1;#(cycle/2);
end
//Step 4. Write a task to reset dut
task rst_dut();begin
reset=1'b1;#10;reset=1'b0;
endendtask
//Step 5. write a task to send input combination.
task din(input i);begin
@(negedge clk);t=i;
endendtask
//Step 6. Run the test bench and assign inputs
initialbegin
rst_dut;din(0);din(1);din(0);din(1);din(1);rst_dut;din(0);din(1);#10;$finish;
end
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// Step 5. Use $monitor to display the various inputs and outputs
Initial$monitor("clk=%b,Input D = %b, Reset = %b, Output q =%b, ~q=%b",clk,t, reset,q,qb);
endmodule
