Verifying an SSD Controller from IP Block to Full SoC · —Re-use available verification IP SoC...

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Jason Polychronopoulos Ben Whitehead Verifying an SSD Controller from IP Block to Full SoC MemCon, Santa Clara Oct 2016

Transcript of Verifying an SSD Controller from IP Block to Full SoC · —Re-use available verification IP SoC...

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Jason Polychronopoulos

Ben Whitehead

Verifying an SSD Controller from IP Block to Full SoC

MemCon, Santa Clara

Oct 2016

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What is Storage?

All non-volatile memory devices and enclosure systems.— HDD— SSD — USB Thumb Drives— Backup (LTO)— Storage Systems

– NAS– SAN– SDS

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SSD Controller SOCVerification Considerations and Challenges

3

NAND Array

ONFI ONFI ONFI ONFI

ONFI ONFI ONFI ONFI

RAM

Host Controller Interface

SSD Controller SOC

Logical to Physical

Translation

CPU/RISC Processors

Wear Leveling

Read & Program Disturb

ECCEngine

NANDMemory

Interface

Defect Management,

Garbage Collection

XOR engines

DDR Controller

Write Abort

Encrypt/Decrypt Engine

Host Interface

DDR3 /DDR4 /DDR…

Software/Firmware

•ECC

•Wear Leveling

•Parity Checks (LDPC)

•DFT

HW, Algorithm & Features

• Functionality

• Size: TerabytesNAND

• PCIe/NVMe

• SATA

• SAS

Host protocols

• Firmware

• Device Drivers

• Applications

Software

• Performance

• Power

• Architecture

System

SoC sizes and complexity are increasing

How do you Verify this?

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Initial Verification Plan

Use simulation to achieve coverage

Block level— Thorough code and functional coverage targets— Use UVM with constrained random and directed tests— Re-use available verification IP

SoC— Connectivity tests— Functional coverage targeting interactions between blocks— Code coverage to ensure all blocks are excercised

– But not necessarily all code in a block

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Definition and separation of verification environment— Test from Test Bench (Env)— Config, Register Model, Agents, Interfaces— Enables test and component interoperability and re-use

Industry standard— Open source SV base class library— Widely adopted and supported— Enables tools and engineering expertise

UVM enables verification re-use

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Simplifies UVM

Reduces Effort

Minimizes Project Risk

UVM Framework provides re-useable infrastructure

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VIP requirements— Capture comprehensive protocol knowledge

– Complete protocol checking, coverageand debug functionality

— Ease of use– Standard SV UVM architecture with efficient APIs for test writing

— Performance– Behavioural and synthesisable models for simulation and acceleration

Verification IP provides protocol expertise

Protocol reading Testbench developmentProductive Verification

Productive Verification

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VIP Configurator

Configuration GUI for protocols and memory models

Configure multiple QVIPs in one session

Generate a complete UVM testbench

QVIPLibrary Files QVIPConfig_policy

Connectivitymodules

Connectivitymodules

DUT

HDL Top Testbench

UVM TestbenchConfigurator

Generate VIP configuration templates or complete testbenches.

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Configurator for Memory Models

Select by vendor, memory type and part number

Generate a pre-configured model

Hundreds of parts to choose from

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Generated memory module template

Parameters with specific instance pre-fix.

(Most are on default settings)

Wire declarations with specific instance naming

Instance declaration with explicit parameter assignment

and signal mapping

Simply include within a testbench module

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VIP Configurator Integration into UVM Framework

IntegrationUVM Framework QVIP Configurator

• Simplifies UVM• Code generators• Provides use model

• Minimizes project risk• Less debugging• UVMF environments

with standard protocols

• Questa VIP protocols• GUI• Customize protocols

QVIP Configurator

UVM Framework

Testbench

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Block_c Environment Block Diagram

AXI4

S

P

AXI4

PCIe

APB3

S

axi4_master_0

pcie_ep

axi4_slave

Class: blk_c_predictorInst: blk_c_pred

Type: In-order SBInst: cpb_sb

def custom_serial_bus

abc custom_parallel_bus

S

S

AXI4axi4_master_1

Type: In-order SBInst: csb_sb

Type: Out-of-order SBInst: axi4_slave_sb

Type: In-order SBInst: apb3_cfg_sb

apb3_config_master

Class: block_c_environment

abccpb_in

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Block_c Environment Block Diagram

AXI4

S

P

AXI4

PCIe

APB3

S

axi4_master_0

pcie_ep

axi4_slave

Class: blk_c_predictorInst: blk_c_pred

Type: In-order SBInst: cpb_sb

1

2

3

4

5

6

7

def custom_serial_bus

abc custom_parallel_bus

S

S

AXI4axi4_master_1

Type: In-order SBInst: csb_sb

Type: Out-of-order SBInst: axi4_slave_sb

Type: In-order SBInst: apb3_cfg_sb

apb3_config_master

Class: qvip_agents_environmentInst: qvip_env

Class: block_c_environment

8

9

10

0abccpb_in

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Generate environment containing configured VIP

• Use GUI to select VIP for standard protocols • VIP can be configured through GUI• Generate creates directory folder• uvmf/qvip_agents.pkg.sv

Configurator

UVMF

Testbench

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Configurator Integration into Framework

• Import functions from configurator into UVMF• Use provided functions from configurator package file• addQvipSubEnv, addQvipBfm• Add design specific VIP connections• addQvipConnection

Configurator

UVMF

Testbench

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Configurator Integration into Framework

• Run testbench• Set environment variable

• TOP_DIR_NAME• Simulate!

• Make design specific changes• Pin wiggling and monitoring within interface• Create golden model• Instantiate DUT and create test suite

Configurator

UVMF

Testbench

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Waveform of block c simulation

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VIP checks for protocol and timing errors

Exhaustive checking— e.g. 600+ assertions for DDRx

Control to enable/disable individual assertions

Detailed description of error along with reference to specification

** ERROR DDR-60058 check_cfg_timers:11.178 /top/ddr_if_memoryDDR_CFG_TPAR_ALERT_RESP_VIOLATION:63 - tPAR_ALERT_RESP illegal value. tPAR_ALERT_RESP has to be set as per spec.“(See DDR4 JESD79-4 Protocol Specification Section 12.3 Table 101-102)"

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Instant protocol debug capability via the VIP

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Coverage Analysis

Re-use function coverage plan from VIP

Functional Coverage monitor stores results in UCDB

Can merge to determine degree of closure

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Testing at Buttonwillow Raceway Park

Zero to testbench in 4.2 seconds

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Zero to testbench in 2 hours

Increased productivity with reduced risk— UVM framework provides testbench infrastructure— Create a running testbench without writing any SV code!— Configurator automates integration of VIP

VIP provides protocol expertise— Protocol checking, coverage & debug— Highly configurable memory models— Exhaustive test suites

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Storage Technology Trends

Software complexity continuing to increase ….— Complex NAND management tasks moving into Firmware (Garbage Collection, Read/Write

wear leveling, File Translation Table management— Performance tuning— Firmware schedules expanding

Hardware more processor centric (HW/SW co-sim) — Simplifies the Hardware— Pushes complexity into the Firmware

Storage Controller Schedules are, will be, and always have been Aggressive.

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17X increase inSW Developers

Storage firmware content is increasing exponentially

Source: IBS, 2013

Verifying an SSD Controller from IP Block to Full SoC, Oct 2016

0

100

200

300

400

500

600

700

800

90nm 65nm 45/40nm 32/28nm 22/20nm 16/14nm

En

gin

ee

rin

g Y

ea

rs

Software Development Effort

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Verification can no longer ignore software

Software is now part of the functionality of what is delivered— The whole system needs to work, not just the hardware

HW bugs escape— Despite the most advanced verification methodologies— Running software in a realistic manner will always find problems missed by

hardware-only verification

System level problems can only be seen at the system level— Executing software in a realistic manner on the complete system

HW being replaced with SW

Russell Klein 2016

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bjw 201626

How to manage the full system simulations?

How to develop and verify Software?

How to manage the complexity?

How do you Verify this?

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Extended Verification Plan

Use simulation to achieve coverage— Block level— SoC

– Connectivity tests– Functional coverage targeting interactions between blocks– Code coverage to ensure all blocks are excercised

– But not necessarily all code in a block

Use Emulation for early firmware testing

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SSD Controller Emulation Environment – ICE

29

SAS

SATA

PCIe

SSD Controller

DRAM Soft Model(DDR3/DDR4/etc)

NAND Soft Model Array

ONFI ONFI ONFI ONFI

ONFI ONFI ONFI ONFI

NOR Soft Model

SSD Controller SOC

Logical to Physical Translation

CPU/RISC Processors

Wear Leveling

Read & Program Disturb

ECCEngine

NANDMemory

Interface

Defect Management, Garbage

Collection

XOR

engines

DDR Controller

Write Abort

Encrypt/Decrypt Engine

Host Interfaac

e

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The Old Way, the Tired Way, (but we know it well)

bjw - 201630

Keep on keepin’ on.

Push your system simulations further.Push the FPGA prototyping further.

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SSD Controller Emulation Environment – ICE

31

SAS

SATA

PCIe

SSD Controller

DRAM Soft Model(DDR3/DDR4/etc)

NAND Soft Model Array

ONFI ONFI ONFI ONFI

ONFI ONFI ONFI ONFI

NOR Soft Model

SSD Controller SOC

Logical to Physical Translation

CPU/RISC Processors

Wear Leveling

Read & Program Disturb

ECCEngine

NANDMemory

Interface

Defect Management, Garbage

Collection

XOR

engines

DDR Controller

Write Abort

Encrypt/Decrypt Engine

Host Interfaac

e

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SSD Controller Emulation Environment – ICE

Host Interface— iSolve SAS, SATA, and PCIe devices translate from real-world interfaces

running at-speed to Veloce-capable speeds– Fast side operates at-speed to connect to available HBAs and host-based testers– Slow side operates at Veloce-based speeds. All speeds and widths supported on the

slow side

— Enables replacing actual ASIC- or FPGA-based design with Veloce-based design with minimal changes to the system

— Transactors and Virtual devices also available

DRAM soft model— Soft models available for full complement of DRAM-based devices— Easily integrates with any design

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SSD Controller Emulation Environment – ICE

NOR soft model

NAND soft model— Full BMEM or Hardware Sparse models available for instantiation inside

Veloce– Choice depends on system configuration, number of instances required– Number of instances limited only based on available number of AVB2s

— Software full models also available– Requires access to co-model host– May not be available when connected to external iSolve devices

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Software Debug on Veloce

SW Debug on Veloce - RAK - 12/2015

One user at a time

JTAG Debugging— Software debug is primarily spent

examining a stopped system— With JTAG debuggers the emulation

resources cannot be shared

Many users at the same time

Codelink Debugging— Emulation runs to completion with no user

intervention— Software debug takes place off-line enabling

Veloce to be shared between many more software developers

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Codelink

Waveform ViewIntegrated Software Debugger

Veloce

Software is “replayed” after being traced during emulation run

Cross domain visibility into waveforms, hardware, and multiple processors with timing synchronization

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Virtual JTAG Probe

SW Debug on Veloce - RAK - 12/2015

Design

Memory

Memory

Memory

Memory

PCIe / USB Peripheral

Port

CORE1

CORE0

JTAGInterface

Embedded Debugger

SCE-MI Interface VirtualJTAG Probe

Co-model Host ProcessNo hardware needed

RS

P

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Codelink + Sourcery Analyzer

Hynix SA demo

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Warpcore

Moves CPU/memory subsystem from the emulator into a virtual machine

Software Debug Suite - RAK - April 2016

DMA

SRAM

GPIO

UART

IP

VeloceWarpcore

TBX

DDR

DRAM

Timer Block

DRAM

DDR

Timer Block

WarpcoreSynchronizer

Software Debug

Core 0

Core 1Core 1 BIM

Core 0BIM

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Your Initials, Presentation Title, Month Year39

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BACKUP SLIDES

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Physical JTAG Probe

Verifying an SSD Controller from IP Block to Full SoC, Oct 2016

Design

Memory

Memory Memory

Memory

PCIe / USB Peripheral

Port

JTAG

CORE1

CORE0

JTAGInterface

Embedded Debugger

RS

P

JTAG probeiSolve JTAG

JTAGI/O Cable

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Storage Metrics

IOPS (throughput)

Latency

Capacity

Power (IOPS/Watt)

Storage Considerations:— Scalability— $/GB— Total Cost of Ownership— Capital Expenditure

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Storage Technology Trends (continued)

New memory technologies — 3D XPoint – Completely changing the SSD controller’s functions— RRAM— NV-DIMM

Chip size— Growing steadily, but fits well-within Veloce— 20-50M gates typical— Traditional System Simulation has Hit the Wall

Power— Every year Power must be reduced 10-15%

Security— Full Disk Encryption

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A Complete Library for ASIC and FPGA Designs

Questa Verification IP Protocol Support

Questa VIP Library

Serial

Family

Ethernet

Family

100G

40G

10G

1G

100M

10M

MIPI ®

Family

USB

Family

USB 3.0

USB 2.0

JTAG

SmartCard

Display

Family

I2C

I2S

SPI 4.2

SPI

UART

Unipro

LLI

CSI-2 / CSI-3

HDMI 2.0

HDMI 1.4

DSI

DigRF

HDCP

HDMI 1.3

USB 1.1

eHCI

CEC

oHCI

xHCI

SSIC

3.1 Serial

3.1 Pipe

MPHY

MPHY

I3C

UFS25/50G

HSI

USB PD

eDP

V-by-One

Automotive

CPHY

DPHY

AMBA ®

Family

AHB5

AXI3

AXI4

PCIe ®

Family

PCIe 3.0

PCIe 2.0

MPHY

PCIe 1.0

ACE

AHB MRIOV

PIE8

RMII

PCIe 4.0

AHCI

NVMe

APB3 DisplayPort

Verifying an SSD Controller from IP Block to Full SoC, Oct 2016

AMBA 5

CHI

CHI 5

Mil-Aero

Family

Spacewire

1553b

I3C

400G

HyperBusTM

HyperRAM

HyperFlash

Automotive

Family

CAN

5G Family

JESD204B

Questa Memory Library

DRAM

Family

DDR2

DDR4

LPDDR4

LPDDR3

LPDDR2

DDR3

DFI

WIDEIO

HBM2

HMC

Flash

Family

SDCard 4.2

eMMc 5.1

ONFI 4.0

UFS

SDIO 4.1

DIMM

Toggle

ParallelNOR

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QVIP EZ-VIP architecture for rapid productivity

Consistent, standard SV UVM architecture— Protocol agents with simple SV configuration— Connectivity modules

Verilog memory models

Configuration and TB generation GUI

Become productive in hours rather than days:

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DUT Connections VIP Configuration Productive Verification

Productive Verification

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Benefits of a VIP Configuration tool

• Environments containing off the shelf VIP componentsAutomation

• Select protocols

• Configuration detailsIntuitive GUI

• Minimize errorsReduces Risk

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Time to Get Testbench Up and Running

weeks

days

hours

With integrated VIP Configurator & UVM FrameworkUsing UVM & VIP Only

UVM Skill

Pro

toco

l &

VIP

k

no

wle

dg

e

Novice Medium Advanced

Ad

va

nce

dM

ed

ium

No

vic

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Verifying an SSD Controller from IP Block to Full SoC, Oct 201648

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Verifying an SSD Controller from IP Block to Full SoC, Oct 201649


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DATElibertyyes.homestead.com/2-1-Brothers/Verifying...TAW 720121 Bydir 980-310 263 68 SOC. SEC. 11. EMBOSSING PLATE IMPRESSION RUTHERFORD Thomas M (Middle ) NO. CONTINUED SUPPLNENTAL

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