Verifying A SOC Based on the AMBA Interconnect Using … Chiang Mentor...on the AMBA Interconnect...

Albert Chiang

Product Marketing Manger, DVT

DVClub Shanghai

Verifying A SOC Based on the AMBA Interconnect Using Graph Stimulus

June 2014

www.mentor.com © 2014 Mentor Graphics Corp. Company Confidential

Verification Challenges

Block level — LPDDR2, eMMC, Flash — USB 2.0, HDMI — MIPI DSI, DigRF, CSI-2 — I2S, SDIO, UART

Sub-System level — Interconnect/Bridge — Throughput/Latency/QoS — Low power — CDC

System — HW : All of the above — Software

– App, OS, Driver

— Real world conditions (speed, use cases, …)

How do you verify HW, SW, & System?


Mentor Enterprise Verification Platform


Agenda

Interconnect in SOCs

Interconnect Verification Challenges

Interconnect Verification Solutions

Conclusion


CHI

ACE

AXI4

AXI3

AMBA Bus Advancement

AHB

• Bus -> Switch • Independent addr and data channels • Separate addr/cntl and data phases • Out-of-order completion of bursts

• 256 beats of data per burst • QoS (AWQOS, ARQOS)

• +3 channels to AXI for coherency • Coherent address channel (ACADDR) • Coherent response channel (CRRESP) • Coherent data channel (CDATA) • CCI-400 limited to ACE (2S), ACE-Lite

(2S,3M)

• ARMv8 64-bit, big.LITTLE • QoS, L3 Cache • CCN-504 expanded to 4 CHI, 18 ACE-

LITE, 2 DMC


AMBA Bus Verification Complexity

AHB

AXI3

AXI4

ACE

CHI

Verifica

tion C

om

ple

xity

not-

to-s

cale

/ log


Environment (UVM)

AMBA Interconnect Verification Flow

ACE VIP

Cache Coherent Interconnect

ACE-LITE VIP

ACE-LITE VIP ACE-LITE VIP

Stimulus Stimulus

Response Response

Data

Inte

grity

Perf

orm

ance

Analy

sis

Cohere

ncy

cfg cfg

cfg cfg

Traffic Generator

Pro

toco

l Check

ing

Verifica

tion P

lan

Pro

toco

l Debug


Stimulus Generation

ACE-LITE VIP

Stimulus

1. Directed Test 2. SystemVerilog – randsequence() 3. UVM/OVM – Sequence & Virtual Sequencer 4. Graphs

ACE VIP

Stimulus

Cache Coherent Interconnect

Traffic Generator


Why Graphs?

Easier to create & shape stimulus

Easier to debug stimulus

Easier to synchronize stimulus

Easier to create stimulus coverage

Speed up simulation*


Graphs : Easier To Create & Shape Stimulus

Traditional Stimulus Description — SystemVerilog Constraints — Text Based — Can be complicated

10


Graphs : Easier To Create & Debug Stimulus

32 bits of Address 4 billion values

Read or Write 2 operations

Burst Length 1 or 2 or 3 or 4

Constraint length constrains size

Burst Size 1 or 2 or 3 or 4

Graph Stimulus Description — Graph Based — Easy to Create & Read — Can Import SV Constraints

11

Stimulus Set & Members

Pre-Randomize

Post-Randomize

Conditional Constraint


Traditional Stimulus Coverage Modeling

Traditional Stimulus Description — SystemVerilog Constraints — Text Based — Complicated

Traditional Coverage Model — SystemVerilog Covergroups — Text Based — Match constraint?

How do you know your constraints match your covergroups?

12


Graphs : Easier To Create Accurate Coverage

13

Stimulus Description

Coverage Model

Time Wasted Generating tests you

don’t care about

Poor Stimulus - Missed Coverage

Will never achieve coverage here


Graphs : Easier To Create Stimulus Coverage

Coverage Model — Graph Based — Easy to Create & Read — Can Export SV Covergroups

32 bits of Address Don’t care

Run Randomly

Read or Write Cover both operations

Auto Generate Coverpoint

Burst Length & Size Cover all legal combinations Auto Generate Covergroup

14

Don’t Cover

Cover State

Cover Legal

Crosses



Constraints Coverage

Graph -> coverage



Stimulus Description Coverage

Model

16

Stimulus Description

Coverage Model

Time Wasted Generating tests you

don’t care about

Missed Coverage Will never achieve

coverage here


Graphs : Easier To Synchronize Stimulus

Simultaneously launch transactions on multiple ports that can be synchronized to start on the same clock

All of these features can be used to produce any number of worst case scenarios to thoroughly examine the capabilities of the interconnect

4 sync’d masters

Each master has its

own graph


Graphs : Speed Up Simulation*

Actual Results — Eliminates unwanted redundancy

— Targets functional coverage

— 10X to 100X faster coverage

Scalable Architecture — Efficiently leverage simulation farm

Easy to Adopt — UVM

— Re-use existing VIP

— Broad verification language support

— Integrates quickly

0

10

20

30

40

50

60

70

80

90

100

0 500 1000 1500 2000

Co

ve

rag

e (

%)

Simulation Time (ms)

0

10

20

30

40

50

60

70

80

90

100

0

30

0

60

0

90

0

12

00

15

00

18

00

21

00

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00

26

00

29

00

32

00

35

00

38

00

41

00

44

00

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00

50

00

53

00

56

00

590

0

62

00

65

00

68

00

71

00

74

00

77

00

800

0

83

00

86

00

89

00

92

00

95

00

98

00

Simulation Time After Initialization (ms)

Covera

ge (

%)

51%

10%

100%

CRT

inFact

10%

100%

CRT

inFact

18

* Questa InFact graph based stimulus


Real World Graphs on AXI


Customer Design : Interconnect Protocol Variety Makes Traffic Very Difficult to Control

Interconnect fabric for AMBA® protocols

PCI-E

USB

Ethernet

NAND

ROM

SYSCTL

APB I/O

DDR

CPU

AXI

20

AXI

AXI

AHB

AXI

AXI

AXI

APB


AXI VIP m

Multi-Level Interconnect Graphs Simultaneously Create UVM/OVM Sequences & Embedded C Tests to Drive CPU

Interconnect fabric for AMBA

protocols

AXI VIP

AXI VIP

AHB VIP

AXI VIP

AXI VIP

APB VIP

DDR

CPU

s m

s m

s

s m

s m

s m

s m

s m

s m

s

m

AXI VIP

mon mon Scoreboard

21


Interconnect Traffic Generation Traffic Control and Modulation

Traffic Scenario Goals — Operate fabric under normal and expected conditions — Put fabric under as many conditions of duress as

possible

Corner Case Traffic Conditions — Slows down to unacceptable performance — Blocks out certain masters or slaves — Causes system lock ups

Traffic Modulation — Allows traffic shaping into scenarios — Create light, normal, heavy, & variable traffic

22


Interconnect Traffic Generation Traffic Coordinating Graph

Can Control All Other Graphs — UVM/OVM VIP protocol graphs — Embedded C test program graph

Can Continuously Adjust Settings — Enables each master to

modulate local traffic

Can Precisely Control Other Graphs — Enables synchronous traffic

generation on multiple masters

Can Loosely Control Other Graphs — Enable asynchronous traffic

generation on multiple masters

23


Interconnect Traffic Scenario Generation Requires Sparse, Normal, Heavy, & Variable Traffic

Normal Traffic Scenario — Bus activity is dense

during a buffer transfer — Bus activity goes quiet

while waiting new for transfers to start

Heavy Traffic Scenario — Minimal quiet time

between large transfers

24

Burst Len

Idle

Sync


Interconnect Traffic Control Scenarios Targets Features and Performance as a Fabric Instead of as an Array of Ports

25


Graph Can Be Easily Extended to ACE

ACE Master (Cache)

ACE Master

Fabric/Switch/Interconnect

ACE Slave (Mem)

CCI Monitor


Graph Based Stimulus

“… we are keenly aware users want their design and verification data to be as portable as possible …” Dennis Brophy, Mentor

But standardization, not technology/ROI/interest, has been a road block to adoption

Accellera Portable Stimulus Proposed Working Group formed


Portable Stimulus Proposed Working Group

DVCon: Mentor proposes new Accellera Working Group — Announce intent to donate inFact language specification

May 7th: Proposed Working Group launch meeting — 18 participants (Users & EDA Vendors) — 9 companies

June 3rd : DAC Birds of a Feather meeting — 15 participants — 11 companies

June 16th: Started weekly meetings — Assembling and discussing requirements


Conclusion

AMBA bus -> interconnect -> network increases & shifts verification challenges

Traffic generation is key in verifying protocol, data integrity, coherency, and performance

Many ways to generate traffic

Graph based approach makes creating, debug, synchronization, coverage easier

Accellera Portable Stimulus Proposed Working Group formed to accelerate the adoption of graph based stimulus


THANK YOU!

Verifying A SOC Based on the AMBA Interconnect Using … Chiang Mentor...on the AMBA Interconnect...

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