Verification Futures 2016 · Assertions, XProp, Super Linting Incisive-VSP Hybrid with...

Nick Heaton, Distinguished Engineer, Cadence Design Systems

Verification Futures 2016

2 © 2015 Cadence Design Systems, Inc. All rights reserved.

Update on Challenges presented in 2015, namely

• Scalability of the verification engines

• The rise of Use-Case Driven Verification

• SW as part of SoC Verification

Agenda


Challenges today’s SoC developers face

• Many IPs

− Standard I/O − WiFi, USB, PCI Express® (PCIe®), etc.

− System infrastructure − Interconnect, interrupt control, UART, timers…

− Differentiators − Custom accelerators, modem…

• Many cores

− Both symmetric and asymmetric

− Both homogeneous and heterogeneous

• Lots of software

− Part of core functionality − Communication stack, DSP software, GPU

microcode…

− User application software infrastructure − Android, Linux…

Application Specific Components

SoC interconnect fabric – ARM or ithers

ARM V8 CPUSubsystem

3D

GFX

DSP

A/V

High speed, wired interface peripherals

DDR

3

PHY

Other peripherals

SAT

A MIPI

HDMI

WLA

N LTE Low-speed

peripheral

subsystem

Low speed peripherals

PM

U MIPI JTA

G

INT

C I2C

SPI Tim

er

GPI

O Display

UAR

T

Boot

process

or

ARM M0

Modem

Cortex

-A53

L2 cache

USB3.

0

3.

0 P

H

Y

2.

0 P

H

Y

PCIe

Gen

2,3

PHY

Eth

er

net

PH

Y

Cortex

-A53

Cortex

-A57

L2 cache

Cortex

A57

Cache coherent fabric

SoC

Software

Bare

meta

l

so

ftw

are

DS

P s

oft

ware

Init

So

ftw

are

fo

r

bo

ot,

po

wer,

secu

rity

RTOS

Drivers

Communications L2

Communications L1

Firmware / HAL

Communications L3

Operating Systems (OS)

Drivers

Applications

Middleware

Firmware / HAL

Low-Speed

Peripherals

General-

Purpose

Peripherals

High Speed,

Wired Interface

Peripherals

Customer’s

Application-Specific Components

Processor

Subsystem


Common Customer Use Models Leveraging Integrated Suite Enables optimized verification and SW development flows

Incisive® VSP

SystemC / Virtual

Prototyping

Stratus™

High-level

Synthesis

JasperGold®

Formal

Verification

Incisive

Simulation

Palladium™

Acceleration &

Emulation

Protium™

FPGA Based

Prototyping

Solutions: Metric Driven Verification, ARM-based Development (Server, Mobile, IoT),

Low Power & Mixed Signal, Functional Safety, TLM Design & Verification

Verification IP Verification IP

Indago™, SimVision™ Debug & Analysis

vManager™ Plan & Management

Perspec™ System-level Use-Case Verification

Acceleration

Palladium XP

Workstation

RTL

TB

RTL

Design

Emulation

Palladium XP

RTL

Design

Palladium XP

TB RTL

Design

VSP/Palladium Hybrid

Palladium XP

Workstation

TLM RTL

Design

VSP/IES Mixed VP

Workstation

TLM RTL

Design

C/C++/FPGA Hybrid

FPGA Prototype

Workstation

C/C++ RTL

Design

Palladium/Protium Hybrid

Palladium XP

RTL

Design

FPGA Prototype

RTL

Design

Simulation

Workstation

TB RTL

Design

FPGA Based Prototyping

FPGA Prototype

RTL

Design

TB/RTL

TLM / RTL

TLM / RTL

TLM/RTL RTL/RTL


Incisive® VSP

SystemC / Virtual

Prototyping

Stratus™

High-level

Synthesis

JasperGold®

Formal

Verification

Incisive

Simulation

Palladium™

Acceleration &

Emulation

Protium™

FPGA Based

Prototyping







Verification Acceleration with Hot

Swap, Coverage Merge, UPF/CPF

Connection Points within the suite of engines

Assertions, XProp, Super Linting

Incisive-VSP Hybrid with Palladium/Incisive

Common front-end

with Multi Fabric Compiler

Assertion Based VIP


Capabilities combining simulation and emulation

Incisive® VSP

SystemC /

Virtual

Prototyping

Stratus™

High-level

Synthesis

JasperGold®

Formal

Verification

Incisive

Simulation

Palladium™

Acceleration &

Emulation

Protium™

FPGA Based

Prototyping







Acceleration

Palladium XP

Workstation

RTL

TB

RTL

Design

TB/RTL

Hot-swap Balance software and hardware based

execution

Time to point of interest

Common Compile

Ease of transition

Coverage Merge Faster coverage closure

Gate-level acceleration Validate gate-level synthesis with

minimal capacity overhead

Accelerated VIP Migrate from simulation with VIPs to acceleration with AVIPs with common

library (roadmap)

In-circuit acceleration

Re-use Environment

Mix abstractions Balance by model availability


Palladium Z1 Announced Q4 2015


4 to 576MG User capacity

Up to 4MHz Max perf.

1152 GBytes User memory

56 Gbps Per ports

1152 GBytes Debug memory

Up to 140MG

per hour Compile perf.

Palladium Z1 Model S18L

38"

(0.97m)

• Unmatched engineering productivity – Up to 5X greater emulation throughput

– Up to 2.5X greater workload efficiency

– Up to 2X faster compilation speed

– Up to 50% higher average performance

• Scalable datacenter-class emulation system – IP to full SoC emulation: 4 to 576 million per rack

– Scales up to 9.2BG with up to 2,304 parallel jobs

– Rack-based form factor: setup in existing data center

– Redundancy: reliability and availability

• Virtualization – Virtual target relocation

– Advanced job reshaping

– Emulation Development Kits (EDK)

– Virtual Verification Machine (VVM)

• Best in class total cost of ownership (TCO) – 8X higher gate density

– 92% smaller footprint

– 44% better power density

– 22 use models

Key characteristics Delivering up to 5X greater emulation throughput

24"

(0.61m)


JasperGold® formal verification platform

Visualize™ Interactive UI & Debug JasperGold Apps

JasperGold Platform Core Technologies

Programmable Interface via TCL

Parallel & Multiple Engines with ProofGrid™ Manager

Links to System Development Suite™ (Incisive, Palladium, Metric-Driven Verification, Debug…)

Assertion Based Verification IPs for AMBA and other common protocols

Connectivity

Verification App

X-Propagation

Verification App

Control/Status

Register Verif. App

Automatic Formal

Linting App

Design Coverage

Verification App

Low Power

Verification App

Security Path

Verification App

Sequential Equivalence

Checking App

Coverage

Unreachability App

Formal Property

Verification App

Clock Domain

Crossing App

Functional Safety

Verification App


Cross-platform Infrastructure

Indago™ Debug Infrastructure Incisive® Metrics Center

Verification IP Catalog

Formal

Assisted

Verification

Closure

Formal

Assisted

Debug

Formal

Assisted

Simulation

Formal

Assisted

Emulation

Tight integration with System Development Suite

Palladium®

Emulation &

Acceleration

IDA

SimVision™

ESWD

Visualize Formal Verification View

Incisive

Simulation

Engines

IEEE Standard Languages & Industry Standard APIs

JasperGold®

Formal Engines

vManager

Plan

Construct

Execute

Measure/

Analyze

• Incisive® front-end

and irun integration

• Assertion export to

Incisive

• Assertion-Based

VIP support

• Assertion export

to Palladium®

• vManager™

integration

• Coverage

unreachability

• Visualize™ features

in Indago™ for

simulation users


Scope AFL

XPROP CSR FPV ABVIP UNR FSV SEC SPV LPV CDC CONN

SoC (Multi-CPU)

w/Sim Sub-

System (Single-CPU)

w/Sim

Cluster (Peripherals

on bus)

Unit (Multi-

blocks)

Block

JasperGold apps: design scope = now

= near future


SoC verification needs to address:

Diverse Platforms

Virtual Platform Simulation Emulation FPGA Prototype Silicon Board

Diverse Users

Architect HW

Developer

SW

Developer

Verification

Engineer

SW Test

Engineer

Post-silicon

Validation

Engineer

Diverse Scopes

(Integration)

IP

Sub-System

OS & Drivers

Bare Metal SW

System on Chip

(HW + SW)

Middleware

(Graphics, Audio,

etc..)

Vert

ical R

euse

Horizontal Reuse

Use Case Reuse

Application Specific Components

SoC interconnect fabric

ARM V8 CPUSubsystem

3D

GFX

DSP

A/V

High speed, wired interface peripherals

DDR3

PHY

Other peripherals

SATA

MIPI

HDMI

WLAN

LTE Low-speed peripheral

subsystem

Low speed peripherals

PMU

MIPI

JTAG

INTC

I2C

SPI

Timer

GPIO

Display

UART

Boot

processor

ARM M0

Modem

Cortex

-A53

L2 cache

USB3.0

3.0 PHY

2.0 PHY

PCIe

Gen 2,3

PHY

Ether

net

PHY

Cortex

-A53

Cortex

-A57

L2 cache

Cortex

A57

Cache coherent fabric

Perspec

takes use cases

defined by users

Generates code

that runs on

embedded CPUs

Exercising the

system through

diverse relevant

scenarios


The Solution: Perspec ™ System Verifier

Diverse Platforms

Virtual Platform Simulation Emulation FPGA Prototype Silicon Board

Diverse Users

Architect HW

Developer

SW

Developer

Verification

Engineer

SW Test

Engineer

Post-silicon

Validation

Engineer V

ert

ical R

euse

Horizontal Reuse

Use Case Reuse

Diverse Scopes

(Integration)

IP

Sub-System

OS & Drivers

Bare Metal SW

System on Chip

(HW + SW)

Middleware

(Graphics, Audio,

etc..)

Abstract Model

3D

GFX DSP

A/V Boot

Proc Comm

Procs Multi-cluster

Apps Processors

Many cores

Powerful

Solvers

Multi-core Verification OS

C test SV test C test Scripts

Mapping to Targets

Perspec™

System Verifier

Reusable Use Cases

Generated code

Delivers 10x Productivity Gain

Modeling: Library provides built in content (e.g. coherency stressing)

Generation Automation: Tests capture user intent & use cases


A constraint driven model-based approach aligned with Perspec semantics and

supporting graph-based descriptions of stimulus and test scenarios

To learn more about the portable stimulus working group, visit web site

New Portable Stimulus Specification (PSS) Standard Accellera PSWG is working on developing this standard

Cadence & Mentor Contribution

Enabling industry alignment on a Portable Stimulus Specification

Contribution will help accelerate development of a standard that meets

both vertical and horizontal stimulus and test reuse requirements

http://accellera.org/activities/working-groups/portable-stimulus/

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