Ver i Log Introduction
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System Specification Using VerilogHDL
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Number Specification
When specifying constants, whether they be singlebit or multi-bit, you should use an explicit syntax toavoid confusion:
The general syntax is: {bit width}{base}{value}
4d14//4-bit value, specified in decimal
4he//4-bit value, specified in hex 4b1110//4-bit value, specified in binary
4b10xz//4-bit value, with x and z, in binary
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Gate Delays
nand #(prop_delay)
nand #(t_rise, t_fall)
nand #(t_rise, t_fall, t_off)
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Delay Control
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Switch Level Modeling
nmos name (out, data, ctrl);
pmos name (out, data, ctrl);
ctrl
outdata
ctrl
outdata
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CMOS Inverter Switch Network
module cmosinverter (out, in);
input in;
output out;supply1 vdd;
supply0 gnd;
pmos p1 (vdd, out, in);
nmos n1 (gnd, out, in);
endmodule
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NMOS NOR with pullup Primitives
module nor2 (out, a, b);
input a, b;
output out;supply0 gnd;
nmos na (gnd, out, a);
nmos nb (gnd, out, b);pullup (out);
endmodule
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Data Type
There are two main data types in Verilog. These datatypes may be single bit or multi-bit.
Wires
Wires are physical connections between devices and are
continuously assigned. Nets do not remember, or store, information -This behaves
much like an electrical wire...
Registers Regs are procedurally assigned values and remember, or
store, information until the next value assignment is made.
It is nothardware register
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Data Type DeclarationWire (wire) Definition
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Data Type Declaration
Register (reg) Definition
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Variable Declaration
con
stant
s
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Verilog Arithmetic Operator
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Verilog Relational Operator
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Verilog Bitwise Operator
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Verilog Logical Operator
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Verilog Concatenation Operator
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Example 1
Example 2
Continuous Assignment
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Procedural Constructs
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Syntax Example
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Sensitivity List
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Procedural Constructs
Combinational logic using operators:
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Procedural Constructs
Combinational logic using if-else:
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Procedural Constructs
Combinational logic using case:
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System Tasks
The $sign denotes Verilog system tasks, there area large number of these, most useful being:
$display(The value of a is %b, a); Used in procedural blocks for text output. The %b is the value format (binary, in this case)
$finish; Used to finish the simulation.
Use when your stimulus and response testing is done.
$stop; Similar to $finish, but doesnt exit simulation.
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Event Control
Event Control Edge Triggered Event Control
Level Triggered Event Control
Edge triggered Event Control
Level Triggered Event Control
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Loop Statement
Loop Statement
Repeat
While
For
Repeat Loop
Example
repeat (count)sum = sum + 6;
If condition is a x orz is treated as o
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Loop Statement (cont.)
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Conditional statement
ifStatement
Format:if(condition)
procedural_statement
else if( condition)
procedural_statement
Example
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Case Statement
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Structural
module mux21(a, b, s, y);
input a, b, s;
output y;
wire m, n, p;and g1(m, b, s);
not g2(n, s);
and g3(p, a, n);
or g4(y, m, p);
endmodule
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Behavioral
module mux21(A, B, S, Y);
input A, B, S;
output Y;
reg Y;always @(A orB or S)begin
if(S==0) Y = A;
else Y = B;
end
endmodule
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Compiler Directives
include used to include another file
Example
include ./pqp_fetch.v
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Suggested Coding Style
Write one module per file, and name the file thesame as the module. Break larger designs intomodules on meaningful boundaries.
Always use formal port mapping of sub-modules.
Use parameters for commonly used constants.
Be careful to create correct sensitivity lists.
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Dont ever just sit down and code. Think aboutwhathardware you want to build, how to describe it,andhow you should test it.
You are not writing a computer program, you aredescribing hardware Verilog is not C!
Only you know what is in yourhead. If you needhelp from others, you need to be able to explainyour design -- either verbally, or by detailedcomments in your code.
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The End