VDMOSFET MODEL PARAMETER EXTRACTION BASED ON...

Active and Passive Eiec. Comp., 2001, Vol. 23, pp. 185-195 2001 OPA (Overs Publisher Aoziation) N.V.Reprints available directly from the publisher Published by liceme underPhotocopying permitted by license only the Gordon and Breach Science

Publisher imprint.

VDMOSFET MODEL PARAMETEREXTRACTION BASED ON ELECTRICALAND OPTICAL MEASUREMENTS

C.-T. SALAME*, C. RIZK and G. JELIAN

Radiation Technology, lnterfaculty Reactor Institute, Delft Universityof Technology, Mekelweg 15, 2629 JB Delft, The Netherlands

(Received 22 August 2000; In finalform 13 September 2000)

Lateral Device parameters for VDMOSFET (Vertical double diffused metal oxide’miconductor field effect transistor) with hexagonal cells has been extracted by anoriginal model based on electrical and optical measurements. Using microscopicobservation for the ship of the device and by C-V characterization, the lateral devicestructure parameters could be extracted. Values of the extracted parameters are in goodcorrelation with the values given by the manufactured. Advantage of this model the highprecision results with a low cost. Perhaps, the most important point in this model, thatwe can replace the other techniques usually employed in this study where we destroyedthe device for cut and cross section ofthe structure. The proposed technique in this papercan be very useful for analyzing any complex geometrical structure of VDMOStransistors (hexagonal, triangular, square etc...).

Keywords: VDMOSFET; Parameter extraction; Lateral parameters; Hexagonal cell

1. INTRODUCTION

The n-channel MOSFETs are the most popular for use in powerswitching circuits and applications. Various manufacturers producepower MOSFETs under the names HEXFET (International rectifier),VMOS (Phillips), SIPMOS (Siemens) and all consist of variousphysical designs diffused into an epitaxial substrate in multiple parallel

*Corresponding author. Tel.: + 31 15 278 3776, Fax: + 31 15 278 6442, e-mail:[email protected]

185

186 C.-T. SALAME et al.

configurations [1-3]. VDMOSFET with hexagonal cells (HEXFET)has a complex geometrical structure. The size of these components isspecially adapted by the manufacturers in response to the needs of thepower [4- 7]. Technical progress of microelectronic integration involvealso an evolution towards the miniaturization which requires newstructural modifications to answer the sub-micronics parasitic effects[8-111.

Lateral parameters of these devices are needed for softwaresimulation models for the components structure. In order to describeour methodology, electrical measurements of the capacitance voltagerelationship at a high frequency and optical measurements areperformed.The VDMOSFET structure and the measurements techniques are

discussed in part 2. Part 3 deals with the extraction methodology basedon the capacitance- voltage characterization and the microscopicobservation.

2. DEVICE STRUCTURE AND MEASUREMENTSTECHNIQUES

An approximation of the internal structure of an VDMOSFET is

shown in Figure 1. Drain and source connections are made to higherconduction high doped regions. The metal gate is electrically isolatedfrom the p-type substrate by a layer of non-conducting silicon oxide(SiO2). When a positive voltage is applied to the gate with respect tothe source an electric field will be created pointing away from the baseand across the p-region directly under the base. The electric field willcause positive charges in the p-region to move away from the baseinducing or enhancing a n-region in its place. Conduction can thentake place between the n+ (drain) n (enhanced region) n + (source).Increasing or decreasing the gate voltage will cause the induced n-channel to grow or decrease in size thus controlling conduction. Thedrive voltage or voltage applied between gate and source to switchthe MOSFET ON must exceed a threshold value of Vth. Reducing thedrive voltage to below Vth will cause the MOSFET to turn OFF.The equivalent circuit of an enhancement MOSFET is shown in

Figure 2a. Two parasitic eapacitance’s between gate to source and gate

VDMOSFET 187

Source

Gate

N+

Drain

Metal

Si02

Induced N

HEXFETD

N+

N/

FIGURE Approximation of the internal structure of an VDMOSFET.

Drain_

cs_L lGate.Cgs,.-’T- Rbe_iSource

npmparasitictransistor

FIGURE 2a The equivalent electrical circuit of an enhancement VDMOSFET.


to drain will cause switching delays if the gate driver cannot supportlarge initial currents. A further parasitic capacitance and bipolar npntransistor exist between drain and source but due to the internalstructure the transistor appears as a diode and capacitor connectedbetween drain and source as shown in Figure 2b. Unfortunately theparasitic diode does not have the structure of a fast diode and must beneglected and a separate fast diode used in a high speed switchingcircuit.The parallel connection ofMOSFETs allows higher load currents to

be handled by sharing the current between the individual switches.Because MOSFETs have a positive temperature coefficient they can beparalleled without the need for source resistors (BJTs need smallemitter resistors that provide negative feedback). If one MOSFETstarts to draw slightly more current than the others it heats up andits impedance increases which results in the current through it decreas-ing. Parallel MOSFETs should be mounted close together so thatthe gate drive impedances are the same and all transistors switch atthe same time.By a C-V measurement between the gate and the drain the

capacitance’s values for the n--layer, the n-channel and the overlap(source region n+ under the gate oxide) can be determined.Microscopic observation for the device area is realized to determinethe source (Ls) and the gate (Lg) lengths of one cell. In the opticalmeasurements the gate length is the distance between two cells.

Combination between this two measurement is used to extract thedifferent lateral parameters.

_ ’gd

__TL gs

Drain

i._.J SiGate.-- D

Cd _L :.:"-I N+/

SolrceFIGURE 2b The equivalent circuit of a VDMOSFET where the bipolar npn transistorappears as a diode and capacitor connected between drain and source.

VDMOSFET 189

3. EXTRACTION METHODOLOGY

The cross-sectional view of the device is shown in Figure 3, the gateand the source lengths are determined by the microscopic observation.The capacitance measurement between the gate and the drain, Cov, isused in order to extract the device parameters. The experimental set-upfor the CV measurements is shown Figure 4. An HP4192A is used inthe CV measurement. A small a.c voltage at 1 MHz is applied betweenthe High (gate) and the low (drain) potential electrodes. Thecapacitance through the grounded source electrode is not include in

Gate

Drain

FIGURE 3 VDMOSFET Structure: top view and cut section.


FIGURE 4 The gate-drain capacitance (COD) measurement set-up.

the measurement because the small a.c voltage is not applied to thesource electrode.The measured capacitance COD is shown in Figure 5 and the

conceptional charge distributions with the applied d.c gate biases areshown in the Figure 6a, b.When an the applied gate voltage is lower than the threshold voltage

of n- region VTD, the n- region, p region and n/ region show inver-sion, accumulation and depletion modes, respectively (Fig. 6a). Forthis gate voltage values, the hole of the strongly inverted n- region

2000

1800

1600

’ 1400

1200

lOOO

800

ACgd

Cgd(min)VTD th

600-4 -3 -2 -1 0 1 2 3 4 5 6

Vgd(V)FIGURE 5 The measured gate-drain capacitance curve (CGD).

VDMOSFET 191

G

(a)

D

G

(b)

D

FIGURE 6 The conceptional charge distribution in VDMOSFET with the differentapplied gate biases: (a) V3 < VTD and (b) Vo > Vth.


cannot be supplied from the p region (the p region is floated at a. c). Inthis case, CD is the minimum value consisted of metal-oxide- n-structure capacitance and its value CD-i is written by:

Cox CDUN (Cox" Co). A;

Where, Cox (= eox/tox) is the gate capacitance per unit area, A isthe area of the n- region, N the total number of the device cells, CDis the depletion capacitance per unit area in the n- region given by:

CDM e (2)

where ND is the doping concentration of n- epitaxial layer, generallycalled the lightly doped drain region is about 3 x 10TM em- [12], i isthe surface potential in the strong inverted n- region.

Sine all the cells are mounted in parallel the unit cell capacitance areobtained dividing the measured device capacitance by the totalnumber of cells (N).When the gate voltage is larger than Vta, which is the maximum

threshold voltage of channel, the electrons in the accumulated n+

region (Overlap) as well as the p region (channel n) are supplied fromthe n- region (Fig. 6b). Therefore, COD undergoes sudden increase at

Vos Vth and the capacitance variation at Vth, ACoD, is the same asthe oxide capacitance of the n/ region written by:

+ACoD/N Cox.An(overlap), (3)

+where An(overlap) is the area of the n+ source region under the gateoxide. In the case of Vos > Vth, Con is the same as the entire gateoxide capacitance and its value, COD(max), is represented by:

CGD(max)/N Cox" Agate, (4)

where Agate is the total gate area.The threshold voltage Vt was determined in the saturation region

where the drain current of the VDMOSFET is given [13] by’

lDS(sat) nCoxW/L(VGs- Vth)2

VDMOSFET 193

By plotting versus Vts (for a given VDS > VDs@at)), the thresholdvoltage can be deduced from the linvarly vxtrapolatod valu at theaxis (Fig. 7).

Structure of the unit hexagonal cell is approximate to cylinder (seeFig. 8) for the facility of the mathematical equations resolve. Thisapproximation doesn’t affect much the results precision since theparameters values determinate with our method have 96% of thevalues given by the device manufactured.

In the approximate unit cell of cylinder type, the total gate areaAgate, the n+ source area (Overlap) An+source and the n- region areaAn_ are represented by:

(6)

(7)

(8)

Lg Ln+source + Lch + Ln- (9)

0,28

0,24, 0,20

0,16

0,12

0,08

0,04

0,00

/

1 ,_1

1,4 1,6 1,8 2,0 2,2 2,4 2,6 2,8 3,0 3,2

V(d,)(V)FIGURE 7 Determination of the threshold voltage of the VDMOSFET by electricalmeasurement.


DRAIN

FIGURE 8 Structure of the unit hexagonal cell approximate to cylinder.

Where r+ Lg is the unit cell radius, Ln+source is the n+ source length(Overlap), Lch is the channel length and Ln- is the n- region length.The total gate length (Lg) is the sum of these length. Coomax, ACoDand CoDCmin in the unit cell are 0.1698, 0.0188 and 0.0698pF,respectively. From Coo(max) and Eqs. (4) and (6), the gate oxidethickness of 98 nm is extracted and his value is in excellent agreementwith the expected oxide thickness from the process (100 nm). Ln + sourc

TABLE I The comparison of the real dimensions and theextracted dimensions

Real lateral dimension Extracted lateral dimension

dox 100nm 98 nmLn. 9 8,42Lch ttm 0,98L,+ 0,7 0,6 lam

VDMOSFET 195

is extracted from (3) and (7) and Lch is extracted from (1) and (8).Then Ln. is extracted from the determined Ln+ source, Lch and (9).The device parameter lengths extracted using the propose method in

this paper, are listed in Table I.

4. CONCLUSION

An original model for power MOSFETs lateral parameters extractionhave been presented. Values of the extracted parameters are inexcellent agreement with the values Oven by the devices fabricant.These parameters are very important for device structure simulationand modulation to evaluate degradation properties cased by electricalstress, radiation effects etc...

Reference$

[1] Baliga, B. J. (1981). "Silicon Power Field Controlled Devices", Silicon IntegratedCircuits, Part B, Academic Press, New York, pp. 158-174.

[2] Baliga, B. J. (1982). "High-Voltage Device Terminaison Techniques- A Com-parative Review", IEEE Proc., 129, 173 179.

[3] Baliga, B. J., "Modern Power Devices", John Wiley, New York, 1987.[4] Gagnard, X., Taurin, M. and Bonnaud, O. (1999). "New rapid method for lifetime

determination of gate oxide validated with Bipolar/CMOS/DMOS technology"ESREF99 Conference Proceeding, pp. 785-790.

[5] Arnould, J. et Merle, P., "Dispositifs de l’lectronique de puissance", Trait desnouvelles technologies (Electronique), Hermes, Paris, 1992.

[6] Chang, H. R. and Baliga, J. (1987). "Impact of cell breakdown upon powerDMOSFET on-resistance". IEEE Transactions on Electron Devices, ED-34.

[7] Goodenough, F., "Power MOSFET and bipolar technologies merge to get the bestof both worlds", Electronic Design, pp. 53-56, juillet, 1983.

[8] "Power MOS Derides-data book"-I dition-SGS-THOMSON-juin, 1988.[9] Rossel, P. (1984). "Power MOS Device", Microelectron, Reliab., 24, 339-366.

[10] Lee, J. C., Chen, I.-C. and Hu, C., "Modelling and characterisation of gateoxide reliability", IEEE Transactions on Electron Devices, 35(12), December, 1988,2268- 2278.

[11] Cunningham, J. A., "The Use and Evaluation of Yield Models in IntegratedCircuit Manufacturing", In: IEEE Trans. On Semiconductor Manufacturing, 3(2),60-71.

[12] Chung-Min Liu and James B. Kuo (1995). "Turn-offTransient Analysis of DoubleDiffused Metal-Oxide-Semiconducteur Device Considering Quasi Saturation",Appl. Phys., 34, 869-873.

[13] Sze, S. M., Physics ofSemiconductor Devices, Ch. 8, John Wiley, New York, 1981.

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