VALUE-ADDED PACKAGING

INTEGRATION FOR

MOBILE AND WEARABLE

APPLICATIONS

JEDEC Mobile & IOT Forum

Copyright © 2016

Wei H. Koh, PhD

Huawei Technologies Co. Ltd.

PACKAGING SYSTEM PROPOSITION

High cost of 1x and sub 1x nm shrink morph into

More Moore and More than Moore (MtM)

(ITRS)

HITRS

PACKAGING WHITE KNIGHT RESCUE

HELP!!

Here I

come !!

OUTLINE

• Value-added, Complex, Advanced Packaging System Integration (PSI) for MtM

– “Revival” of Packaging System Integration

• Leading–edge Advanced Packaging Technologies:

– Package on Package (PoP)

– Wafer Level Fan-out Packages

– System in Packages (SiP)

– Embedded Solutions (Emerging)

• Design and Assembly Considerations

– High temperature reflow warpage

– JEDEC Standards

• Challenges/Industry Needs

• Summary and Conclusions

VALUE-ADDED PACKAGING DRIVERS

• CMOS scaling near Moore’s Law limit :

– tick-tock, tick-tock-tock, tock-tock-tock

• Device size/design limit :

– iPhone refresh cycle 2- to 3-year?

• Need high performance, more bandwidth, multiple functions; small form factor

• Advanced IC Packages: finer routing, fine pitch interconnect, more I/O, multichip stacking, multichip package, 3D stacking, and 3D WLP

• Front-end FABs and Back-end OSATs merging to “Mid-end” wafer level processing

• Modular applications for mobile and IoT:

Security ID modules, camera modules (CIS), MEMS sensors, Health sensors, RF modules, PM modules

PSI: NEW “CINDERELLA”

• Front-end: Costly, classy, clean

• Back-end: Cheap, ugly, dirty

• Mid-end: Advanced Package System Integration (PSI)

• MtM: Adding value and functions

– Die-level integration: c2c, 3D stack

– Wafer Level integration: Fan-in, Fan-out

– Substrate Level integration: embedded chip and passives

– Board Level integration: embedded IC, embedded MCP, embedded SiP, embedded Multi-die Interconnect Bridge (EMIB)

– System level integration

• Huge market needs and growth potential (>30% CAGR)

VERSATILE PACKAGING TECHNOLOGY

• Interconnect: wire bond, flip chip,

copper pillar, ACF, TSV

• Integration: multi-die, passives,

sensors, MEMS

• Modularization: CPU/GPU, RF, PM,

Opto, etc.

• Smaller form factors: IC scaling,

shrinking passives, sensors

• Integrated packages: PoP, SiP,

FOWLP, Embedded

PACKAGING SYSTEMS

Lead Frame

SoJ

SOC

PLCC

PQFP

QFN

Area Array

FC

BGA

uBGA

LGA

CSP

Modules

MCM

MCP

PoP

SiP

2.5D TXV

3D TXV

Wafer Level

Fan-in

Fan-out

Stacked

SIP

FHE

Nano

Flex

3D Print

IF PACKAGES WERE WEARABLES

Leaded BGA CSP WLP 3D TSV FHE

heavy rounded thin tight expensive 3 in 1

wrapped balanced elegant functional sexy curves

MOBILE AND WEARABLE MARKETS

• Post-PC era:

• Smartphone major driver for innovation: mobile SOC solutions

• Wearable/fitness expanding (41% CAGR, Prismark)

• IoT promises high volume of smart client devices

• Heterogeneous integration SiP as “virtual”, partitioned SOC

WERABLE AND FITNESS DEVICES

Huawei Smart watches and

TalkBand (fitness trackers)

ADVANCED PACKAGING PLATFORM

(Yole 2015)

PoP/SOC in SAMSUNG S7

• Qualcomm Snapdragon 820

SOC

• SK Hynix LPDDR4 memory

(3733Mbps)

• 4x2 rows with 342 balls

APPLE A8/A9 PoP

AMKOR PoP TECHNOLOGY

SAMSUNG EPOP

• Embedded PoP-Single package of eMCP (eMMC, DRAM) and AP for wearable

• 60% space saving, 1.4mm thick

POP ISSUES/CHALLENGES

(Samsung)

Assembly yield concern

- Finer ball pitch

- Reflow warping

HD-FOWLP

• High Density Fan-out Advantages:

– Eliminate TSV interposer– Small form factor, high performance– Replacing larger BGA – 3D stackable for PoP application– Wafer level processing– Multi-die and heterogeneous

integration (SiP)– Potential for panel processing

• Infineon eWLB• Amkor SLIM, SWIFT• SPILL SLIT, NTI• TSMC InFO• Deca M-series

MOTHER OF ALL FAN-OUTs: eWLB

FOWLP INTEGRATION

(Yole 2015)

AMKOR SWIFT TECHNOLOGY

TSMC INFO WLP/PoP

Chip-package codesign/co-fabrication

Chip-first, RDL line/space 5/5 to 2/2 um

15x15 mm

SIP FOR WEARABLES

Moto 360 Apple Watch

Challenges

1. Thin coreless substrates

2. Tiny components (01005)

3. Tight spacing

4. Ultra thin mold

5. Warpage control

6. Repair/rework

RELIABILITY QUALIFICATION

Amkor

PoP

Dimensions

(mm)

PSvfB

GA

10x10 to

15x15

PSfcC

SP

12x12 to

13x13

TMV 12x12 to

14x14

Package Level Test Test Conditions

Moisture Resistance JEDEC L3 @260ºC x 4 reflow

Temperature Cycling

Test

-55 to 125ºC, 1000 cycles

Temperature/Humidity 85/85, 1000 h

High Temperature

Storage

150ºC, 1000 h

HAST 130ºC/85% RH, 96 h

Board Level Test

Temperature Cycling -40 to 125ºC, 1000 cycles

(Amkor

Technology)

HIGH TEMPERATURE DYNAMIC WARPAGE

• Achilles’ heel in SMT assembly: solder joint defects: NWO, HiP, SBB (bridging)

• Root-cause: reflow dynamic warpage

• Process and material optimization to mitigate defects

• Warpage control:

– Reduce CTE mismatch

– Optimize substrate routing design

– Low CTE coreless substrates

– Embed IC inside substrate

– Use WLP (lower intrinsic warp)

– Reduce residual stress

WARPAGE-RELATED STANDARDS

• JEDEC Publication 95, SPP-024 (Mar 2009) Reflow Flatness Requirements for Ball Grid Array Packages

• JEDEC JESD22-B112 Package Warpage

Measurement of Surface-Mount Integrated Circuits at elevated Temperature

• JEITA ED-7306, Measurement methods of

package warpage at elevated temperature and the maximum permissible warpage

• JESD22-B108, Coplanarity Test for Surface-

Mount Semiconductor Devices

ACCEPTABLE CRITERIA NEEDS UPDATE!

SPP-024 REQUIREMENT

Many EMS companies consider requirements inadequate(Collaboration between OEM and EMS to combat head-in-pillow, SMT Aug. 2015)

iNEMI HIGH TEMPERTURE WARPGAE DATA

(Recent Trends in Package Warpage, iNEMI 2015)

NEW SUGGESTION: RFR Level

Typical Package Type and

Size

RFR

Level

Maximum Value

(example only) *

PoP, FOWLP

< 15mm x 15 mm1 -0.09 / +0.09 mm

SiP, FCBGA

< 25 x 25 mm2 -0.12 / +0.15 mm

PBGA, large SiP modules

40 x 40 mm 3 -0.18 / +0.20 mm

Reflow Flatness Requirement Levels Various types of package show different dynamic warpage values

* Value may depend on ball size/pitch

NEEDS/CHALLENGES

• Standardization of package integration platform

• Modularization in specific functions for package and system integration

• Embedded, system in module (SIM)

• Panel Processing for FOWLP

• SEMI SIG: ESiPAT (European Semiconductor Integrated Packaging and Test)

• Challenges: electromigtration, thermal, EDA tools, equipment

• DFM: Design for manufacturing, fine pitch SMT assembly and warpage control

SUMMARY/CONCLUSIONS

• New Packaging Paradigm: Packaging system integration/system platform for MtM– Value-added function integration, high performance,

size reduction, and system cost benefit

• Innovation in design, materials, and process– Thinner PoP with finer pitch, more I/O

– Stackable FOWLP for PoP and 2.5D/3D SiP

• SiP/WLP: modularization for mobile, wearable, IoT, automotives, and medical

• Needs: Enhanced industry Standards, warpage control criteria, acceptable warpage RFR levels, assembly equipment, design/test tools